URL
https://opencores.org/ocsvn/gpio/gpio/trunk
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Rev 55 → Rev 56
/trunk/bench/verilog/gpio_testbench.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.1 2003/11/30 12:28:19 gorand |
// small "names" modification... |
// |
// Revision 1.5 2003/11/29 16:22:05 gorand |
// small changes, for VATS... |
// |
92,7 → 95,7
wire err; // Failed cycle termination |
wire [gw-1:0] gpio_aux; // GPIO auxiliary signals |
wire [gw-1:0] gpio_in; // GPIO inputs |
wire gpio_eclk; // GPIO external clock |
wire gpio_eclk; // GPIO external clock |
wire [gw-1:0] gpio_out; // GPIO outputs |
wire [gw-1:0] gpio_oen; // GPIO output enables |
wire [ 3 : 0 ] tag_o ; |
/trunk/bench/verilog/gpio_mon.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2003/11/10 23:23:57 gorand |
// tests passed. |
// |
// Revision 1.1 2001/08/21 21:39:27 lampret |
// Changed directory structure, port names and drfines. |
// |
67,7 → 70,7
// |
output [gw-1:0] gpio_aux; // Auxiliary |
output [gw-1:0] gpio_in; // GPIO inputs |
output gpio_eclk; // GPIO external clock |
output gpio_eclk; // GPIO external clock |
input [gw-1:0] gpio_out; // GPIO outputs |
input [gw-1:0] gpio_oen; // GPIO output enables |
|
76,7 → 79,7
// |
reg [gw-1:0] gpio_aux; |
reg [gw-1:0] gpio_in; |
reg gpio_eclk; |
reg gpio_eclk; |
|
initial gpio_eclk = 0; |
|
110,7 → 113,6
end |
endtask |
|
|
// |
// Get gpio_out |
// |
/trunk/bench/verilog/tb_tasks.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/11/30 12:28:19 gorand |
// small "names" modification... |
// |
// Revision 1.8 2003/11/19 14:22:43 gorand |
// small changes, to satisfy VATS.. |
// |
192,6 → 195,29
endtask |
|
// |
// Set RGPIO_ECLK register |
// |
task seteclk; |
input [31:0] val; |
|
begin |
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_ECLK<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// |
// Set RGPIO_NEC register |
// |
task setnec; |
input [31:0] val; |
|
begin |
#100 gpio_testbench.wb_master.wr(`GPIO_RGPIO_NEC<<sh_addr, val, 4'b1111); |
end |
|
endtask |
|
// Display RGPIO_IN register |
// |
task showin; |
297,6 → 323,33
endtask |
|
// |
// Display RGPIO_ECLK register |
// |
task showeclk; |
|
reg [31:0] tmp; |
begin |
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp); |
$write(" RGPIO_ECLK:%h", tmp); |
end |
|
endtask |
|
// |
// Display RGPIO_NEC register |
// |
task shownec; |
|
reg [31:0] tmp; |
begin |
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp); |
$write(" RGPIO_NEC:%h", tmp); |
end |
|
endtask |
|
|
// |
// Compare parameter with RGPIO_IN register |
// |
task comp_in; |
413,6 → 466,30
endtask |
|
// |
// Get RGPIO_ECLK register |
// |
task geteclk; |
output [31:0] tmp; |
|
begin |
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_ECLK<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Get RGPIO_NEC register |
// |
task getnec; |
output [31:0] tmp; |
|
begin |
#100 gpio_testbench.wb_master.rd(`GPIO_RGPIO_NEC<<sh_addr, tmp); |
end |
|
endtask |
|
// |
// Calculate a random and make it narrow to fit on GPIO I/O pins |
// |
task random_gpio; |
449,6 → 526,8
|
// Reset GPIO_CTRL |
setctrl(0); |
seteclk ( 32'h00000000 ) ; |
setnec ( 32'h00000000 ) ; |
|
// Wait for time to advance |
@(posedge gpio_testbench.clk); |
464,8 → 543,9
// |
|
// Set GPIO to use external clock, NEC bit cleared |
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK); |
|
//setctrl(1 << `GPIO_RGPIO_CTRL_ECLK); |
seteclk ( 32'hffffffff ) ; |
setnec ( 32'h00000000 ) ; |
// Put something else on gpio_in pins |
random_gpio(r2); |
gpio_testbench.gpio_mon.set_gpioin(r2); |
504,6 → 584,8
// |
// Compare phases |
// |
//$display ( "data : " ) ; |
//$display ( " l1 = %h r1 = %h l2 = %h r2 = %h l3 = %h ", l1,r1,l2,r2,l3); |
if (l1 == r1 && l2 == r2 && l2 == l3) |
$write("."); |
else |
530,8 → 612,9
@(posedge gpio_testbench.clk); |
|
// Set GPIO to use external clock and set RGPIO_CTRL[NEC] |
setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC); |
|
//setctrl(1 << `GPIO_RGPIO_CTRL_ECLK | 1 << `GPIO_RGPIO_CTRL_NEC); |
seteclk ( 32'hffffffff ) ; |
setnec ( 32'hffffffff ) ; |
// Put random on gpio inputs |
random_gpio(r1); |
gpio_testbench.gpio_mon.set_gpioin(r1); |
600,6 → 683,8
|
// Set GPIO to use WB clock |
setctrl(0); |
seteclk ( 32'h00000000 ) ; |
setnec ( 32'h00000000 ) ; |
|
err = 0; |
for (i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i +1) begin |
765,6 → 850,8
|
// Disable spurious interrupt monitor |
ints_disabled = 0; |
seteclk ( 32'h00000000 ) ; |
setnec ( 32'h00000000 ) ; |
|
err = 0; |
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin |
854,6 → 941,8
|
// Disable spurious interrupt monitor |
ints_disabled = 0; |
seteclk ( 32'h00000000 ) ; |
setnec ( 32'h00000000 ) ; |
|
err = 0; |
for( i = 0; i < 10 * `GPIO_VERIF_INTENSITY; i = i + 1) begin |
/trunk/rtl/verilog/gpio_defines.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.7 2003/12/01 17:10:44 simons |
// ifndef directive is not supported by all tools. |
// |
// Revision 1.6 2003/11/06 13:59:07 gorand |
// added support for 8-bit access to registers. |
// |
96,7 → 99,12
// |
`define GPIO_IOS 31 |
|
//depending on number of GPIO_IOS, define this... |
// for example: if there is 26 GPIO_IOS, define GPIO_LINES26 |
// |
|
`define GPIO_LINES31 |
|
// |
// Undefine this one if you don't want to remove GPIO block from your design |
// but you also don't need it. When it is undefined, all GPIO ports still |
131,7 → 139,7
|
// |
// Define to avoid using negative edge clock flip-flops for external clock |
// (caused by RGPIO_CTRL[NEC] bit. Instead an inverted external clock with |
// (caused by NEC register. Instead an inverted external clock with |
// positive edge clock flip-flops will be used. |
// |
// By default it is not defined. |
195,8 → 203,8
// |
// WISHBONE address bits used for full decoding of GPIO registers. |
// |
`define GPIO_ADDRHH 6 |
`define GPIO_ADDRHL 5 |
`define GPIO_ADDRHH 7 |
`define GPIO_ADDRHL 6 |
`define GPIO_ADDRLH 1 |
`define GPIO_ADDRLL 0 |
|
203,7 → 211,7
// |
// Bits of WISHBONE address used for partial decoding of GPIO registers. |
// |
// Default 4:2. |
// Default 5:2. |
// |
`define GPIO_OFS_BITS `GPIO_ADDRHL-1:`GPIO_ADDRLH+1 |
|
218,14 → 226,16
// and the register will not be implemented. Instead a fixed default value will |
// be used. |
// |
`define GPIO_RGPIO_IN 3'h0 // Address 0x00 |
`define GPIO_RGPIO_OUT 3'h1 // Address 0x04 |
`define GPIO_RGPIO_OE 3'h2 // Address 0x08 |
`define GPIO_RGPIO_INTE 3'h3 // Address 0x0c |
`define GPIO_RGPIO_PTRIG 3'h4 // Address 0x10 |
`define GPIO_RGPIO_AUX 3'h5 // Address 0x14 |
`define GPIO_RGPIO_CTRL 3'h6 // Address 0x18 |
`define GPIO_RGPIO_INTS 3'h7 // Address 0x1c |
`define GPIO_RGPIO_IN 4'h0 // Address 0x00 |
`define GPIO_RGPIO_OUT 4'h1 // Address 0x04 |
`define GPIO_RGPIO_OE 4'h2 // Address 0x08 |
`define GPIO_RGPIO_INTE 4'h3 // Address 0x0c |
`define GPIO_RGPIO_PTRIG 4'h4 // Address 0x10 |
`define GPIO_RGPIO_AUX 4'h5 // Address 0x14 |
`define GPIO_RGPIO_CTRL 4'h6 // Address 0x18 |
`define GPIO_RGPIO_INTS 4'h7 // Address 0x1c |
`define GPIO_RGPIO_ECLK 4'h8 // Address 0x20 |
`define GPIO_RGPIO_NEC 4'h9 // Address 0x24 |
|
// |
// Default values for unimplemented GPIO registers |
237,14 → 247,110
`define GPIO_DEF_RGPIO_PTRIG `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_AUX `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_CTRL `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_ECLK `GPIO_IOS'h0 |
`define GPIO_DEF_RGPIO_NEC `GPIO_IOS'h0 |
|
|
// |
// RGPIO_CTRL bits |
// |
// To comply with the GPIO IP core specification document they must go from |
// bit 0 to bit 3 in the following order: ECLK, NEC, INTE, INT |
// bit 0 to bit 1 in the following order: INTE, INT |
// |
`define GPIO_RGPIO_CTRL_ECLK 0 |
`define GPIO_RGPIO_CTRL_NEC 1 |
`define GPIO_RGPIO_CTRL_INTE 2 |
`define GPIO_RGPIO_CTRL_INTS 3 |
`define GPIO_RGPIO_CTRL_INTE 0 |
`define GPIO_RGPIO_CTRL_INTS 1 |
|
`ifdef GPIO_LINES32 |
`define GPIO_LINES31 |
`endif |
`ifdef GPIO_LINES31 |
`define GPIO_LINES30 |
`endif |
`ifdef GPIO_LINES30 |
`define GPIO_LINES29 |
`endif |
`ifdef GPIO_LINES29 |
`define GPIO_LINES28 |
`endif |
`ifdef GPIO_LINES28 |
`define GPIO_LINES27 |
`endif |
`ifdef GPIO_LINES27 |
`define GPIO_LINES26 |
`endif |
`ifdef GPIO_LINES26 |
`define GPIO_LINES25 |
`endif |
`ifdef GPIO_LINES25 |
`define GPIO_LINES24 |
`endif |
`ifdef GPIO_LINES24 |
`define GPIO_LINES23 |
`endif |
`ifdef GPIO_LINES23 |
`define GPIO_LINES22 |
`endif |
`ifdef GPIO_LINES22 |
`define GPIO_LINES21 |
`endif |
`ifdef GPIO_LINES21 |
`define GPIO_LINES20 |
`endif |
`ifdef GPIO_LINES20 |
`define GPIO_LINES19 |
`endif |
`ifdef GPIO_LINES19 |
`define GPIO_LINES18 |
`endif |
`ifdef GPIO_LINES18 |
`define GPIO_LINES17 |
`endif |
`ifdef GPIO_LINES17 |
`define GPIO_LINES16 |
`endif |
`ifdef GPIO_LINES16 |
`define GPIO_LINES15 |
`endif |
`ifdef GPIO_LINES15 |
`define GPIO_LINES14 |
`endif |
`ifdef GPIO_LINES14 |
`define GPIO_LINES13 |
`endif |
`ifdef GPIO_LINES13 |
`define GPIO_LINES12 |
`endif |
`ifdef GPIO_LINES12 |
`define GPIO_LINES11 |
`endif |
`ifdef GPIO_LINES11 |
`define GPIO_LINES10 |
`endif |
`ifdef GPIO_LINES10 |
`define GPIO_LINES9 |
`endif |
`ifdef GPIO_LINES9 |
`define GPIO_LINES8 |
`endif |
`ifdef GPIO_LINES8 |
`define GPIO_LINES7 |
`endif |
`ifdef GPIO_LINES7 |
`define GPIO_LINES6 |
`endif |
`ifdef GPIO_LINES6 |
`define GPIO_LINES5 |
`endif |
`ifdef GPIO_LINES5 |
`define GPIO_LINES4 |
`endif |
`ifdef GPIO_LINES4 |
`define GPIO_LINES3 |
`endif |
`ifdef GPIO_LINES3 |
`define GPIO_LINES2 |
`endif |
`ifdef GPIO_LINES2 |
`define GPIO_LINES1 |
`endif |
|
/trunk/rtl/verilog/gpio_top.v
45,6 → 45,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.15 2003/11/10 23:21:22 gorand |
// bug fixed. all tests passed. |
// |
// Revision 1.14 2003/11/06 13:59:07 gorand |
// added support for 8-bit access to registers. |
// |
205,9 → 208,9
// GPIO Control Register (or no register) |
// |
`ifdef GPIO_RGPIO_CTRL |
reg [3:0] rgpio_ctrl; // RGPIO_CTRL register |
reg [1:0] rgpio_ctrl; // RGPIO_CTRL register |
`else |
wire [3:0] rgpio_ctrl; // No register |
wire [1:0] rgpio_ctrl; // No register |
`endif |
|
// |
220,40 → 223,60
`endif |
|
// |
// GPIO Enable Clock Register (or no register) |
// |
`ifdef GPIO_RGPIO_ECLK |
reg [gw-1:0] rgpio_eclk; // RGPIO_ECLK register |
`else |
wire [gw-1:0] rgpio_eclk; // No register |
`endif |
|
// |
// GPIO Active Negative Edge Register (or no register) |
// |
`ifdef GPIO_RGPIO_NEC |
reg [gw-1:0] rgpio_nec; // RGPIO_NEC register |
`else |
wire [gw-1:0] rgpio_nec; // No register |
`endif |
|
// |
// Internal wires & regs |
// |
wire rgpio_out_sel; // RGPIO_OUT select |
wire rgpio_oe_sel; // RGPIO_OE select |
wire rgpio_inte_sel; // RGPIO_INTE select |
wire rgpio_ptrig_sel;// RGPIO_PTRIG select |
wire rgpio_aux_sel; // RGPIO_AUX select |
wire rgpio_ctrl_sel; // RGPIO_CTRL select |
wire rgpio_ints_sel; // RGPIO_INTS select |
wire latch_clk; // Latch clock |
wire full_decoding; // Full address decoding qualification |
wire [gw-1:0] in_muxed; // Muxed inputs |
wire wb_ack; // WB Acknowledge |
wire wb_err; // WB Error |
wire wb_inta; // WB Interrupt |
reg [dw-1:0] wb_dat; // WB Data out |
wire rgpio_out_sel; // RGPIO_OUT select |
wire rgpio_oe_sel; // RGPIO_OE select |
wire rgpio_inte_sel; // RGPIO_INTE select |
wire rgpio_ptrig_sel;// RGPIO_PTRIG select |
wire rgpio_aux_sel; // RGPIO_AUX select |
wire rgpio_ctrl_sel; // RGPIO_CTRL select |
wire rgpio_ints_sel; // RGPIO_INTS select |
wire rgpio_eclk_sel ; |
wire rgpio_nec_sel ; |
wire full_decoding; // Full address decoding qualification |
wire [gw-1:0] in_muxed; // Muxed inputs |
wire wb_ack; // WB Acknowledge |
wire wb_err; // WB Error |
wire wb_inta; // WB Interrupt |
reg [dw-1:0] wb_dat; // WB Data out |
`ifdef GPIO_REGISTERED_WB_OUTPUTS |
reg wb_ack_o; // WB Acknowledge |
reg wb_err_o; // WB Error |
reg wb_inta_o; // WB Interrupt |
reg [dw-1:0] wb_dat_o; // WB Data out |
reg wb_ack_o; // WB Acknowledge |
reg wb_err_o; // WB Error |
reg wb_inta_o; // WB Interrupt |
reg [dw-1:0] wb_dat_o; // WB Data out |
`endif |
wire [gw-1:0] out_pad; // GPIO Outputs |
wire [gw-1:0] out_pad; // GPIO Outputs |
`ifdef GPIO_REGISTERED_IO_OUTPUTS |
reg [gw-1:0] ext_pad_o; // GPIO Outputs |
reg [gw-1:0] ext_pad_o; // GPIO Outputs |
`endif |
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock |
wire pext_clk; // External clock for posedge flops |
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs |
wire [gw-1:0] extc_in; // Muxed inputs sampled by external clock |
wire [gw-1:0] pext_clk; // External clock for posedge flops |
reg [gw-1:0] pextc_sampled; // Posedge external clock sampled inputs |
`ifdef GPIO_NO_NEGEDGE_FLOPS |
`else |
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs |
reg [gw-1:0] nextc_sampled; // Negedge external clock sampled inputs |
`endif |
|
|
// |
// All WISHBONE transfer terminations are successful except when: |
// a) full address decoding is enabled and address doesn't match |
330,6 → 353,11
assign rgpio_ctrl_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_CTRL) & full_decoding; |
assign rgpio_ints_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_INTS) & full_decoding; |
|
assign rgpio_eclk_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_ECLK) & full_decoding; |
assign rgpio_nec_sel = wb_cyc_i & wb_stb_i & (wb_adr_i[`GPIO_OFS_BITS] == `GPIO_RGPIO_NEC) & full_decoding; |
|
|
|
// |
// Write to RGPIO_CTRL or update of RGPIO_CTRL[INT] bit |
// |
336,13 → 364,13
`ifdef GPIO_RGPIO_CTRL |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_ctrl <= #1 4'b0; |
rgpio_ctrl <= #1 2'b0; |
else if (rgpio_ctrl_sel && wb_we_i) |
rgpio_ctrl <= #1 wb_dat_i[3:0]; |
rgpio_ctrl <= #1 wb_dat_i[1:0]; |
else if (rgpio_ctrl[`GPIO_RGPIO_CTRL_INTE]) |
rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] <= #1 rgpio_ctrl[`GPIO_RGPIO_CTRL_INTS] | wb_inta_o; |
`else |
assign rgpio_ctrl = 4'h01; // RGPIO_CTRL[EN] = 1 |
assign rgpio_ctrl = 2'h01; // RGPIO_CTRL[EN] = 1 |
`endif |
|
// |
581,7 → 609,107
assign rgpio_aux = `GPIO_DEF_RPGIO_AUX; // RGPIO_AUX = 0x0 |
`endif |
|
|
// |
// Write to RGPIO_ECLK |
// |
`ifdef GPIO_RGPIO_ECLK |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_eclk <= #1 {gw{1'b0}}; |
else if (rgpio_eclk_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_eclk <= #1 wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_eclk [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_eclk [23:16] <= #1 wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_eclk [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_eclk [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_eclk [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_eclk [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_eclk [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; |
`endif |
end |
|
|
`else |
assign rgpio_eclk = `GPIO_DEF_RPGIO_ECLK; // RGPIO_ECLK = 0x0 |
`endif |
|
|
|
// |
// Write to RGPIO_NEC |
// |
`ifdef GPIO_RGPIO_NEC |
always @(posedge wb_clk_i or posedge wb_rst_i) |
if (wb_rst_i) |
rgpio_nec <= #1 {gw{1'b0}}; |
else if (rgpio_nec_sel && wb_we_i) |
begin |
`ifdef GPIO_STRICT_32BIT_ACCESS |
rgpio_nec <= #1 wb_dat_i[gw-1:0]; |
`endif |
|
`ifdef GPIO_WB_BYTES4 |
if ( wb_sel_i [3] == 1'b1 ) |
rgpio_nec [gw-1:24] <= #1 wb_dat_i [gw-1:24] ; |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_nec [23:16] <= #1 wb_dat_i [23:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES3 |
if ( wb_sel_i [2] == 1'b1 ) |
rgpio_nec [gw-1:16] <= #1 wb_dat_i [gw-1:16] ; |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_nec [15:8] <= #1 wb_dat_i [15:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES2 |
if ( wb_sel_i [1] == 1'b1 ) |
rgpio_nec [gw-1:8] <= #1 wb_dat_i [gw-1:8] ; |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_nec [7:0] <= #1 wb_dat_i [7:0] ; |
`endif |
`ifdef GPIO_WB_BYTES1 |
if ( wb_sel_i [0] == 1'b1 ) |
rgpio_nec [gw-1:0] <= #1 wb_dat_i [gw-1:0] ; |
`endif |
end |
|
|
`else |
assign rgpio_nec = `GPIO_DEF_RPGIO_NEC; // RGPIO_NEC = 0x0 |
`endif |
|
|
// |
// Latch into RGPIO_IN |
// |
`ifdef GPIO_RGPIO_IN |
597,8 → 725,138
// |
// Mux inputs directly from input pads with inputs sampled by external clock |
// |
assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i; |
//assign in_muxed = rgpio_ctrl[`GPIO_RGPIO_CTRL_ECLK] ? extc_in : ext_pad_i; |
|
|
`ifdef GPIO_LINES32 |
assign in_muxed [31] = rgpio_eclk [31] ? extc_in[31] : ext_pad_i[31] ; |
`endif |
|
`ifdef GPIO_LINES31 |
assign in_muxed [30] = rgpio_eclk [30] ? extc_in[30] : ext_pad_i[30] ; |
`endif |
|
`ifdef GPIO_LINES30 |
assign in_muxed [29] = rgpio_eclk [29] ? extc_in[29] : ext_pad_i[29] ; |
`endif |
|
`ifdef GPIO_LINES29 |
assign in_muxed [28] = rgpio_eclk [28] ? extc_in[28] : ext_pad_i[28] ; |
`endif |
|
`ifdef GPIO_LINES28 |
assign in_muxed [27] = rgpio_eclk [27] ? extc_in[27] : ext_pad_i[27] ; |
`endif |
|
`ifdef GPIO_LINES27 |
assign in_muxed [26] = rgpio_eclk [26] ? extc_in[26] : ext_pad_i[26] ; |
`endif |
|
`ifdef GPIO_LINES26 |
assign in_muxed [25] = rgpio_eclk [25] ? extc_in[25] : ext_pad_i[25] ; |
`endif |
|
`ifdef GPIO_LINES25 |
assign in_muxed [24] = rgpio_eclk [24] ? extc_in[24] : ext_pad_i[24] ; |
`endif |
|
`ifdef GPIO_LINES24 |
assign in_muxed [23] = rgpio_eclk [23] ? extc_in[23] : ext_pad_i[23] ; |
`endif |
|
`ifdef GPIO_LINES23 |
assign in_muxed [22] = rgpio_eclk [22] ? extc_in[22] : ext_pad_i[22] ; |
`endif |
|
`ifdef GPIO_LINES22 |
assign in_muxed [21] = rgpio_eclk [21] ? extc_in[21] : ext_pad_i[21] ; |
`endif |
|
`ifdef GPIO_LINES21 |
assign in_muxed [20] = rgpio_eclk [20] ? extc_in[20] : ext_pad_i[20] ; |
`endif |
|
`ifdef GPIO_LINES20 |
assign in_muxed [19] = rgpio_eclk [19] ? extc_in[19] : ext_pad_i[19] ; |
`endif |
|
`ifdef GPIO_LINES19 |
assign in_muxed [18] = rgpio_eclk [18] ? extc_in[18] : ext_pad_i[18] ; |
`endif |
|
`ifdef GPIO_LINES18 |
assign in_muxed [17] = rgpio_eclk [17] ? extc_in[17] : ext_pad_i[17] ; |
`endif |
|
`ifdef GPIO_LINES17 |
assign in_muxed [16] = rgpio_eclk [16] ? extc_in[16] : ext_pad_i[16] ; |
`endif |
|
`ifdef GPIO_LINES16 |
assign in_muxed [15] = rgpio_eclk [15] ? extc_in[15] : ext_pad_i[15] ; |
`endif |
|
`ifdef GPIO_LINES15 |
assign in_muxed [14] = rgpio_eclk [14] ? extc_in[14] : ext_pad_i[14] ; |
`endif |
|
`ifdef GPIO_LINES14 |
assign in_muxed [13] = rgpio_eclk [13] ? extc_in[13] : ext_pad_i[13] ; |
`endif |
|
`ifdef GPIO_LINES13 |
assign in_muxed [12] = rgpio_eclk [12] ? extc_in[12] : ext_pad_i[12] ; |
`endif |
|
`ifdef GPIO_LINES12 |
assign in_muxed [11] = rgpio_eclk [11] ? extc_in[11] : ext_pad_i[11] ; |
`endif |
|
`ifdef GPIO_LINES11 |
assign in_muxed [10] = rgpio_eclk [10] ? extc_in[10] : ext_pad_i[10] ; |
`endif |
|
`ifdef GPIO_LINES10 |
assign in_muxed [9] = rgpio_eclk [9] ? extc_in[9] : ext_pad_i[9] ; |
`endif |
|
`ifdef GPIO_LINES9 |
assign in_muxed [8] = rgpio_eclk [8] ? extc_in[8] : ext_pad_i[8] ; |
`endif |
|
`ifdef GPIO_LINES8 |
assign in_muxed [7] = rgpio_eclk [7] ? extc_in[7] : ext_pad_i[7] ; |
`endif |
|
`ifdef GPIO_LINES7 |
assign in_muxed [6] = rgpio_eclk [6] ? extc_in[6] : ext_pad_i[6] ; |
`endif |
|
`ifdef GPIO_LINES6 |
assign in_muxed [5] = rgpio_eclk [5] ? extc_in[5] : ext_pad_i[5] ; |
`endif |
|
`ifdef GPIO_LINES5 |
assign in_muxed [4] = rgpio_eclk [4] ? extc_in[4] : ext_pad_i[4] ; |
`endif |
|
`ifdef GPIO_LINES4 |
assign in_muxed [3] = rgpio_eclk [3] ? extc_in[3] : ext_pad_i[3] ; |
`endif |
|
`ifdef GPIO_LINES3 |
assign in_muxed [2] = rgpio_eclk [2] ? extc_in[2] : ext_pad_i[2] ; |
`endif |
|
`ifdef GPIO_LINES2 |
assign in_muxed [1] = rgpio_eclk [1] ? extc_in[1] : ext_pad_i[1] ; |
`endif |
|
`ifdef GPIO_LINES1 |
assign in_muxed [0] = rgpio_eclk [0] ? extc_in[0] : ext_pad_i[0] ; |
`endif |
|
|
// |
// Posedge pext_clk is inverted by NEC bit if negedge flops are not allowed. |
// If negedge flops are allowed, pext_clk only clocks posedge flops. |
605,14 → 863,146
// |
`ifdef GPIO_NO_NEGEDGE_FLOPS |
`ifdef GPIO_NO_CLKPAD_LOGIC |
assign pext_clk = clk_pad_i; |
assign pext_clk = {gw{clk_pad_i}}; |
`else |
assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i; |
|
//assign pext_clk = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? ~clk_pad_i : clk_pad_i; |
|
|
`ifdef GPIO_LINES32 |
assign pext_clk [31] = rgpio_nec [31] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES31 |
assign pext_clk [30] = rgpio_nec [30] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES30 |
assign pext_clk [29] = rgpio_nec [29] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES29 |
assign pext_clk [28] = rgpio_nec [28] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES28 |
assign pext_clk [27] = rgpio_nec [27] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES27 |
assign pext_clk [26] = rgpio_nec [26] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES26 |
assign pext_clk [25] = rgpio_nec [25] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES25 |
assign pext_clk [24] = rgpio_nec [24] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES24 |
assign pext_clk [23] = rgpio_nec [23] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES23 |
assign pext_clk [22] = rgpio_nec [22] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES22 |
assign pext_clk [21] = rgpio_nec [21] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES21 |
assign pext_clk [20] = rgpio_nec [20] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES20 |
assign pext_clk [19] = rgpio_nec [19] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES19 |
assign pext_clk [18] = rgpio_nec [18] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES18 |
assign pext_clk [17] = rgpio_nec [17] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES17 |
assign pext_clk [16] = rgpio_nec [16] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES16 |
assign pext_clk [15] = rgpio_nec [15] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES15 |
assign pext_clk [14] = rgpio_nec [14] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES14 |
assign pext_clk [13] = rgpio_nec [13] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES13 |
assign pext_clk [12] = rgpio_nec [12] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES12 |
assign pext_clk [11] = rgpio_nec [11] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES11 |
assign pext_clk [10] = rgpio_nec [10] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES10 |
assign pext_clk [9] = rgpio_nec [9] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES9 |
assign pext_clk [8] = rgpio_nec [8] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES8 |
assign pext_clk [7] = rgpio_nec [7] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES7 |
assign pext_clk [6] = rgpio_nec [6] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES6 |
assign pext_clk [5] = rgpio_nec [5] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES5 |
assign pext_clk [4] = rgpio_nec [4] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES4 |
assign pext_clk [3] = rgpio_nec [3] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES3 |
assign pext_clk [2] = rgpio_nec [2] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES2 |
assign pext_clk [1] = rgpio_nec [1] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`ifdef GPIO_LINES1 |
assign pext_clk [0] = rgpio_nec [0] ? ~clk_pad_i : clk_pad_i ; |
`endif |
|
`endif |
`else |
assign pext_clk = clk_pad_i; |
assign pext_clk = {gw{clk_pad_i}}; |
`endif |
|
|
// |
// If negedge flops are allowed, ext_in is mux of negedge and posedge external clocked flops. |
// |
619,18 → 1009,399
`ifdef GPIO_NO_NEGEDGE_FLOPS |
assign extc_in = pextc_sampled; |
`else |
assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled; |
//assign extc_in = rgpio_ctrl[`GPIO_RGPIO_CTRL_NEC] ? nextc_sampled : pextc_sampled; |
|
|
`ifdef GPIO_LINES32 |
assign extc_in [31] = rgpio_nec [31] ? nextc_sampled[31] : pextc_sampled[31] ; |
`endif |
|
`ifdef GPIO_LINES31 |
assign extc_in [30] = rgpio_nec [30] ? nextc_sampled[30] : pextc_sampled[30] ; |
`endif |
|
`ifdef GPIO_LINES30 |
assign extc_in [29] = rgpio_nec [29] ? nextc_sampled[29] : pextc_sampled[29] ; |
`endif |
|
`ifdef GPIO_LINES29 |
assign extc_in [28] = rgpio_nec [28] ? nextc_sampled[28] : pextc_sampled[28] ; |
`endif |
|
`ifdef GPIO_LINES28 |
assign extc_in [27] = rgpio_nec [27] ? nextc_sampled[27] : pextc_sampled[27] ; |
`endif |
|
`ifdef GPIO_LINES27 |
assign extc_in [26] = rgpio_nec [26] ? nextc_sampled[26] : pextc_sampled[26] ; |
`endif |
|
`ifdef GPIO_LINES26 |
assign extc_in [25] = rgpio_nec [25] ? nextc_sampled[25] : pextc_sampled[25] ; |
`endif |
|
`ifdef GPIO_LINES25 |
assign extc_in [24] = rgpio_nec [24] ? nextc_sampled[24] : pextc_sampled[24] ; |
`endif |
|
`ifdef GPIO_LINES24 |
assign extc_in [23] = rgpio_nec [23] ? nextc_sampled[23] : pextc_sampled[23] ; |
`endif |
|
`ifdef GPIO_LINES23 |
assign extc_in [22] = rgpio_nec [22] ? nextc_sampled[22] : pextc_sampled[22] ; |
`endif |
|
`ifdef GPIO_LINES22 |
assign extc_in [21] = rgpio_nec [21] ? nextc_sampled[21] : pextc_sampled[21] ; |
`endif |
|
`ifdef GPIO_LINES21 |
assign extc_in [20] = rgpio_nec [20] ? nextc_sampled[20] : pextc_sampled[20] ; |
`endif |
|
`ifdef GPIO_LINES20 |
assign extc_in [19] = rgpio_nec [19] ? nextc_sampled[19] : pextc_sampled[19] ; |
`endif |
|
`ifdef GPIO_LINES19 |
assign extc_in [18] = rgpio_nec [18] ? nextc_sampled[18] : pextc_sampled[18] ; |
`endif |
|
`ifdef GPIO_LINES18 |
assign extc_in [17] = rgpio_nec [17] ? nextc_sampled[17] : pextc_sampled[17] ; |
`endif |
|
`ifdef GPIO_LINES17 |
assign extc_in [16] = rgpio_nec [16] ? nextc_sampled[16] : pextc_sampled[16] ; |
`endif |
|
`ifdef GPIO_LINES16 |
assign extc_in [15] = rgpio_nec [15] ? nextc_sampled[15] : pextc_sampled[15] ; |
`endif |
|
`ifdef GPIO_LINES15 |
assign extc_in [14] = rgpio_nec [14] ? nextc_sampled[14] : pextc_sampled[14] ; |
`endif |
|
`ifdef GPIO_LINES14 |
assign extc_in [13] = rgpio_nec [13] ? nextc_sampled[13] : pextc_sampled[13] ; |
`endif |
|
`ifdef GPIO_LINES13 |
assign extc_in [12] = rgpio_nec [12] ? nextc_sampled[12] : pextc_sampled[12] ; |
`endif |
|
`ifdef GPIO_LINES12 |
assign extc_in [11] = rgpio_nec [11] ? nextc_sampled[11] : pextc_sampled[11] ; |
`endif |
|
`ifdef GPIO_LINES11 |
assign extc_in [10] = rgpio_nec [10] ? nextc_sampled[10] : pextc_sampled[10] ; |
`endif |
|
`ifdef GPIO_LINES10 |
assign extc_in [9] = rgpio_nec [9] ? nextc_sampled[9] : pextc_sampled[9] ; |
`endif |
|
`ifdef GPIO_LINES9 |
assign extc_in [8] = rgpio_nec [8] ? nextc_sampled[8] : pextc_sampled[8] ; |
`endif |
|
`ifdef GPIO_LINES8 |
assign extc_in [7] = rgpio_nec [7] ? nextc_sampled[7] : pextc_sampled[7] ; |
`endif |
|
`ifdef GPIO_LINES7 |
assign extc_in [6] = rgpio_nec [6] ? nextc_sampled[6] : pextc_sampled[6] ; |
`endif |
|
`ifdef GPIO_LINES6 |
assign extc_in [5] = rgpio_nec [5] ? nextc_sampled[5] : pextc_sampled[5] ; |
`endif |
|
`ifdef GPIO_LINES5 |
assign extc_in [4] = rgpio_nec [4] ? nextc_sampled[4] : pextc_sampled[4] ; |
`endif |
|
`ifdef GPIO_LINES4 |
assign extc_in [3] = rgpio_nec [3] ? nextc_sampled[3] : pextc_sampled[3] ; |
`endif |
|
`ifdef GPIO_LINES3 |
assign extc_in [2] = rgpio_nec [2] ? nextc_sampled[2] : pextc_sampled[2] ; |
`endif |
|
`ifdef GPIO_LINES2 |
assign extc_in [1] = rgpio_nec [1] ? nextc_sampled[1] : pextc_sampled[1] ; |
`endif |
|
`ifdef GPIO_LINES1 |
assign extc_in [0] = rgpio_nec [0] ? nextc_sampled[0] : pextc_sampled[0] ; |
`endif |
|
`endif |
|
// |
// Latch using posedge external clock |
// |
always @(posedge pext_clk or posedge wb_rst_i) |
|
`ifdef GPIO_LINES32 |
always @(posedge pext_clk[31] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled <= #1 {gw{1'b0}}; |
pextc_sampled[31] <= #1 1'b0; |
else |
pextc_sampled <= #1 ext_pad_i; |
pextc_sampled[31] <= #1 ext_pad_i[31]; |
`endif |
|
`ifdef GPIO_LINES31 |
always @(posedge pext_clk[30] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[30] <= #1 1'b0; |
else |
pextc_sampled[30] <= #1 ext_pad_i[30]; |
`endif |
|
`ifdef GPIO_LINES30 |
always @(posedge pext_clk[29] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[29] <= #1 1'b0; |
else |
pextc_sampled[29] <= #1 ext_pad_i[29]; |
`endif |
|
`ifdef GPIO_LINES29 |
always @(posedge pext_clk[28] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[28] <= #1 1'b0; |
else |
pextc_sampled[28] <= #1 ext_pad_i[28]; |
`endif |
|
`ifdef GPIO_LINES28 |
always @(posedge pext_clk[27] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[27] <= #1 1'b0; |
else |
pextc_sampled[27] <= #1 ext_pad_i[27]; |
`endif |
|
`ifdef GPIO_LINES27 |
always @(posedge pext_clk[26] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[26] <= #1 1'b0; |
else |
pextc_sampled[26] <= #1 ext_pad_i[26]; |
`endif |
|
`ifdef GPIO_LINES26 |
always @(posedge pext_clk[25] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[25] <= #1 1'b0; |
else |
pextc_sampled[25] <= #1 ext_pad_i[25]; |
`endif |
|
`ifdef GPIO_LINES25 |
always @(posedge pext_clk[24] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[24] <= #1 1'b0; |
else |
pextc_sampled[24] <= #1 ext_pad_i[24]; |
`endif |
|
`ifdef GPIO_LINES24 |
always @(posedge pext_clk[23] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[23] <= #1 1'b0; |
else |
pextc_sampled[23] <= #1 ext_pad_i[23]; |
`endif |
|
`ifdef GPIO_LINES23 |
always @(posedge pext_clk[22] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[22] <= #1 1'b0; |
else |
pextc_sampled[22] <= #1 ext_pad_i[22]; |
`endif |
|
`ifdef GPIO_LINES22 |
always @(posedge pext_clk[21] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[21] <= #1 1'b0; |
else |
pextc_sampled[21] <= #1 ext_pad_i[21]; |
`endif |
|
`ifdef GPIO_LINES21 |
always @(posedge pext_clk[20] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[20] <= #1 1'b0; |
else |
pextc_sampled[20] <= #1 ext_pad_i[20]; |
`endif |
|
`ifdef GPIO_LINES20 |
always @(posedge pext_clk[19] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[19] <= #1 1'b0; |
else |
pextc_sampled[19] <= #1 ext_pad_i[19]; |
`endif |
|
`ifdef GPIO_LINES19 |
always @(posedge pext_clk[18] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[18] <= #1 1'b0; |
else |
pextc_sampled[18] <= #1 ext_pad_i[18]; |
`endif |
|
`ifdef GPIO_LINES18 |
always @(posedge pext_clk[17] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[17] <= #1 1'b0; |
else |
pextc_sampled[17] <= #1 ext_pad_i[17]; |
`endif |
|
`ifdef GPIO_LINES17 |
always @(posedge pext_clk[16] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[16] <= #1 1'b0; |
else |
pextc_sampled[16] <= #1 ext_pad_i[16]; |
`endif |
|
`ifdef GPIO_LINES16 |
always @(posedge pext_clk[15] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[15] <= #1 1'b0; |
else |
pextc_sampled[15] <= #1 ext_pad_i[15]; |
`endif |
|
`ifdef GPIO_LINES15 |
always @(posedge pext_clk[14] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[14] <= #1 1'b0; |
else |
pextc_sampled[14] <= #1 ext_pad_i[14]; |
`endif |
|
`ifdef GPIO_LINES14 |
always @(posedge pext_clk[13] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[13] <= #1 1'b0; |
else |
pextc_sampled[13] <= #1 ext_pad_i[13]; |
`endif |
|
`ifdef GPIO_LINES13 |
always @(posedge pext_clk[12] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[12] <= #1 1'b0; |
else |
pextc_sampled[12] <= #1 ext_pad_i[12]; |
`endif |
|
`ifdef GPIO_LINES12 |
always @(posedge pext_clk[11] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[11] <= #1 1'b0; |
else |
pextc_sampled[11] <= #1 ext_pad_i[11]; |
`endif |
|
`ifdef GPIO_LINES11 |
always @(posedge pext_clk[10] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[10] <= #1 1'b0; |
else |
pextc_sampled[10] <= #1 ext_pad_i[10]; |
`endif |
|
`ifdef GPIO_LINES10 |
always @(posedge pext_clk[9] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[9] <= #1 1'b0; |
else |
pextc_sampled[9] <= #1 ext_pad_i[9]; |
`endif |
|
`ifdef GPIO_LINES9 |
always @(posedge pext_clk[8] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[8] <= #1 1'b0; |
else |
pextc_sampled[8] <= #1 ext_pad_i[8]; |
`endif |
|
`ifdef GPIO_LINES8 |
always @(posedge pext_clk[7] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[7] <= #1 1'b0; |
else |
pextc_sampled[7] <= #1 ext_pad_i[7]; |
`endif |
|
`ifdef GPIO_LINES7 |
always @(posedge pext_clk[6] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[6] <= #1 1'b0; |
else |
pextc_sampled[6] <= #1 ext_pad_i[6]; |
`endif |
|
`ifdef GPIO_LINES6 |
always @(posedge pext_clk[5] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[5] <= #1 1'b0; |
else |
pextc_sampled[5] <= #1 ext_pad_i[5]; |
`endif |
|
`ifdef GPIO_LINES5 |
always @(posedge pext_clk[4] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[4] <= #1 1'b0; |
else |
pextc_sampled[4] <= #1 ext_pad_i[4]; |
`endif |
|
`ifdef GPIO_LINES4 |
always @(posedge pext_clk[3] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[3] <= #1 1'b0; |
else |
pextc_sampled[3] <= #1 ext_pad_i[3]; |
`endif |
|
`ifdef GPIO_LINES3 |
always @(posedge pext_clk[2] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[2] <= #1 1'b0; |
else |
pextc_sampled[2] <= #1 ext_pad_i[2]; |
`endif |
|
`ifdef GPIO_LINES2 |
always @(posedge pext_clk[1] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[1] <= #1 1'b0; |
else |
pextc_sampled[1] <= #1 ext_pad_i[1]; |
`endif |
|
`ifdef GPIO_LINES1 |
always @(posedge pext_clk[0] or posedge wb_rst_i) |
if (wb_rst_i) |
pextc_sampled[0] <= #1 1'b0; |
else |
pextc_sampled[0] <= #1 ext_pad_i[0]; |
`endif |
|
// |
// Latch using negedge external clock |
// |
647,7 → 1418,7
// Mux all registers when doing a read of GPIO registers |
// |
always @(wb_adr_i or rgpio_in or rgpio_out or rgpio_oe or rgpio_inte or |
rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints) |
rgpio_ptrig or rgpio_aux or rgpio_ctrl or rgpio_ints or rgpio_eclk or rgpio_nec) |
case (wb_adr_i[`GPIO_OFS_BITS]) // synopsys full_case parallel_case |
`ifdef GPIO_READREGS |
`GPIO_RGPIO_OUT: begin |
662,12 → 1433,18
`GPIO_RGPIO_PTRIG: begin |
wb_dat[dw-1:0] = rgpio_ptrig; |
end |
`GPIO_RGPIO_NEC: begin |
wb_dat[dw-1:0] = rgpio_nec; |
end |
`GPIO_RGPIO_ECLK: begin |
wb_dat[dw-1:0] = rgpio_eclk; |
end |
`GPIO_RGPIO_AUX: begin |
wb_dat[dw-1:0] = rgpio_aux; |
end |
`GPIO_RGPIO_CTRL: begin |
wb_dat[3:0] = rgpio_ctrl; |
wb_dat[dw-1:4] = {dw-4{1'b0}}; |
wb_dat[1:0] = rgpio_ctrl; |
wb_dat[dw-1:2] = {dw-2{1'b0}}; |
end |
`endif |
`GPIO_RGPIO_INTS: begin |
767,3 → 1544,4
`endif |
|
endmodule |
|
/trunk/doc/gpio_spec.pdf
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/doc/src/gpio_spec.doc
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/trunk/sim/rtl_sim/log/ncelab.log
1,4 → 1,4
TOOL: ncelab 04.10-b001: Started on Dec 09, 2003 at 12:18:09 |
TOOL: ncelab 04.10-b001: Started on Dec 17, 2003 at 12:34:14 |
ncelab |
-f ncelab.args |
-MESSAGES |
20,26 → 20,26
streams: 2, words: 1034 |
worklib.gpio_mon:v <0x50b5485b> |
streams: 6, words: 1408 |
worklib.gpio_testbench:v <0x2b2f512c> |
worklib.gpio_testbench:v <0x26ac113d> |
streams: 2, words: 300 |
worklib.gpio_top:v <0x2a4cd65a> |
streams: 72, words: 55544 |
worklib.tb_tasks:v <0x3e6d21f9> |
streams: 33, words: 52966 |
worklib.wb_master:v <0x2119db6d> |
streams: 38, words: 21648 |
worklib.gpio_top:v <0x566f67ec> |
streams: 205, words: 164573 |
worklib.tb_tasks:v <0x0ae72b6b> |
streams: 39, words: 57166 |
worklib.wb_master:v <0x008f4b18> |
streams: 38, words: 21666 |
Loading native compiled code: .................... Done |
Building instance specific data structures. |
Design hierarchy summary: |
Instances Unique |
Modules: 6 6 |
Registers: 122 122 |
Scalar wires: 23 - |
Vectored wires: 14 - |
Always blocks: 24 24 |
Registers: 130 130 |
Scalar wires: 85 - |
Vectored wires: 13 - |
Always blocks: 56 56 |
Initial blocks: 3 3 |
Cont. assignments: 10 17 |
Pseudo assignments: 2 43 |
Cont. assignments: 40 79 |
Pseudo assignments: 2 49 |
Simulation timescale: 10ps |
Writing initial simulation snapshot: worklib.bench:rtl |
TOOL: ncelab 04.10-b001: Exiting on Dec 09, 2003 at 12:18:10 (total: 00:00:01) |
TOOL: ncelab 04.10-b001: Exiting on Dec 17, 2003 at 12:34:15 (total: 00:00:01) |
/trunk/sim/rtl_sim/log/ncvlog.log
1,4 → 1,4
TOOL: ncvlog 04.10-b001: Started on Dec 09, 2003 at 12:18:08 |
TOOL: ncvlog 04.10-b001: Started on Dec 17, 2003 at 12:34:13 |
ncvlog |
-f ncvlog.args |
-CDSLIB ../bin/cds.lib |
33,4 → 33,4
file: ../../../bench/verilog/gpio_testbench.v |
module worklib.gpio_testbench:v |
errors: 0, warnings: 0 |
TOOL: ncvlog 04.10-b001: Exiting on Dec 09, 2003 at 12:18:09 (total: 00:00:01) |
TOOL: ncvlog 04.10-b001: Exiting on Dec 17, 2003 at 12:34:14 (total: 00:00:01) |
/trunk/sim/rtl_sim/log/ncsim.log
1,4 → 1,4
TOOL: ncsim 04.10-b001: Started on Dec 09, 2003 at 12:18:10 |
TOOL: ncsim 04.10-b001: Started on Dec 17, 2003 at 12:34:15 |
ncsim |
-LICQUEUE |
-f ./ncsim.args |
12,6 → 12,10
|
Loading snapshot worklib.bench:rtl .................... Done |
ncsim> source /shared/tools/ncsim/tools/inca/files/ncsimrc |
ncsim> database -open waves -shm -into ../out/waves.shm |
Created SHM database waves |
ncsim> probe -create -database waves gpio_testbench -shm -all -depth all |
Created probe 1 |
ncsim> run |
|
### |
38,6 → 42,6
|
report (deaddead) |
exit (00000000) |
/projects/highland/gorand/gpio/bench/verilog/tb_tasks.v:1009 $finish(0); |
/projects/highland/gorand/gpio/bench/verilog/tb_tasks.v:1095 $finish(0); |
ncsim> quit |
TOOL: ncsim 04.10-b001: Exiting on Dec 09, 2003 at 12:21:32 (total: 00:03:22) |
TOOL: ncsim 04.10-b001: Exiting on Dec 17, 2003 at 12:35:10 (total: 00:00:55) |
/trunk/sim/rtl_sim/run/ncsim.tcl
1,2 → 1,4
database -open waves -shm -into ../out/waves.shm |
probe -create -database waves gpio_testbench -shm -all -depth all |
run |
quit |