URL
https://opencores.org/ocsvn/ion/ion/trunk
Subversion Repositories ion
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- This comparison shows the changes necessary to convert path
/
- from Rev 55 to Rev 56
- ↔ Reverse comparison
Rev 55 → Rev 56
/ion/trunk/src/mips_mpu1_template.vhdl
82,14 → 82,17
constant BRAM_SIZE : integer := @code_table_size@; |
constant BRAM_ADDR_SIZE : integer := log2(BRAM_SIZE); |
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type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0); |
--type t_bram is array(0 to BRAM_SIZE-1) of std_logic_vector(7 downto 0); |
type t_bram is array(0 to (BRAM_SIZE)-1) of t_word; |
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-- bram0 is LSB, bram3 is MSB |
signal bram3 : t_bram := (@code3@); |
signal bram2 : t_bram := (@code2@); |
signal bram1 : t_bram := (@code1@); |
signal bram0 : t_bram := (@code0@); |
--signal bram3 : t_bram := (@ code3@); |
--signal bram2 : t_bram := (@ code2@); |
--signal bram1 : t_bram := (@ code1@); |
--signal bram0 : t_bram := (@ code0@); |
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signal bram : t_bram := (@code-32bit@); |
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subtype t_bram_address is std_logic_vector(BRAM_ADDR_SIZE-1 downto 0); |
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signal bram_rd_addr : t_bram_address; |
180,11 → 183,12
begin |
if clk'event and clk='1' then |
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bram_rd_data <= |
bram3(conv_integer(unsigned(bram_rd_addr))) & |
bram2(conv_integer(unsigned(bram_rd_addr))) & |
bram1(conv_integer(unsigned(bram_rd_addr))) & |
bram0(conv_integer(unsigned(bram_rd_addr))); |
--bram_rd_data <= |
-- bram3(conv_integer(unsigned(bram_rd_addr))) & |
-- bram2(conv_integer(unsigned(bram_rd_addr))) & |
-- bram1(conv_integer(unsigned(bram_rd_addr))) & |
-- bram0(conv_integer(unsigned(bram_rd_addr))); |
bram_rd_data <= bram(conv_integer(unsigned(bram_rd_addr))); |
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end if; |
end process fpga_ram_block; |
/ion/trunk/src/bin2hdl.py
65,7 → 65,7
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# Write the data for each of the four column tables as a VHDL byte |
# constant table. |
vhdl_data_strings = [" "*indent_size]*6 |
vhdl_data_strings = [" "*indent_size]*7 |
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for j in range(4): |
col = 0 |
83,7 → 83,7
vhdl_data_strings[j] = vhdl_data_strings[j] + item |
vhdl_data_strings[j] = "\n" + vhdl_data_strings[j] |
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# ok, now build init strings for 16-bit wide memorier, split in 2 byte |
# ok, now build init strings for 16-bit wide memories, split in 2 byte |
# columns: an odd column with bytes 3:1 and an even column with bytes 2:0 |
byte_order = [3,1,2,0] |
for j in range(2): |
107,6 → 107,32
vhdl_data_strings[4+j] = vhdl_data_strings[4+j] + item |
vhdl_data_strings[4+j] = "\n" + vhdl_data_strings[4+j] |
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# finally, build init strings for 32-bit wide memories not split into |
# byte columns; useful for read-only 32-bit wide BRAMs |
byte_order = [3,2,1,0] |
col = 0 |
word_count = len(tables[0]) |
for i in range(word_count): |
w3 = tables[byte_order[0]][i] |
w2 = tables[byte_order[1]][i] |
w1 = tables[byte_order[2]][i] |
w0 = tables[byte_order[3]][i] |
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word_count = word_count - 1 |
if word_count > 0: |
item = "X\"%02X%02X%02X%02X\"," % (w3, w2, w1, w0) |
else: |
item = "X\"%02X%02X%02X%02X\"" % (w3, w2, w1, w0) |
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col = col + 1 |
if col == 4: |
col = 0 |
item = item + "\n" + " "*indent_size |
vhdl_data_strings[6] = vhdl_data_strings[6] + item |
vhdl_data_strings[6] = "\n" + vhdl_data_strings[6] |
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return vhdl_data_strings |
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def main(argv): |
224,8 → 250,10
# ...and build the keyword and replacement tables |
keywords = ["@code0@","@code1@","@code2@","@code3@", |
"@code31@", "@code20@", |
"@code-32bit@", |
"@data0@","@data1@","@data2@","@data3@", |
"@data31@", "@data20@", |
"@data-32bit@", |
"@entity_name@","@arch_name@", |
"@sim_len@", |
"@xram_size@", |