URL
https://opencores.org/ocsvn/pci/pci/trunk
Subversion Repositories pci
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- from Rev 55 to Rev 56
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Rev 55 → Rev 56
/trunk/rtl/verilog/pci_target32_sm.v
42,6 → 42,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/09/24 18:30:00 mihad |
// Changed state machine encoding to true one-hot |
// |
// Revision 1.5 2002/08/22 09:07:06 mihad |
// Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. |
// |
59,8 → 62,6
// |
// |
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`define P_FSM_BITS 2 // number of bits needed for FSM states |
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`include "pci_constants.v" |
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// synopsys translate_off |
454,8 → 455,8
.clk_enable (pcit_sm_clk_en) |
); |
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reg [(`P_FSM_BITS - 1):0] c_state ; //current state register |
reg [(`P_FSM_BITS - 1):0] n_state ; //next state input to current state register |
reg [2:0] c_state ; //current state register |
reg [2:0] n_state ; //next state input to current state register |
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// state machine register control |
always@(posedge clk_in or posedge reset_in) |