OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 55 to Rev 56
    ↔ Reverse comparison
  •

Rev 55 → Rev 56

/sdhc-sc-core/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
98,6 → 98,7
 
function automatic void calcCrc();
logic[39:0] temp;
crc = 0;
 
temp[39] = startbit;
temp[38] = transbit;
132,7 → 133,7
ICmd.cb.Cmd <= arg[i];
end
 
for (int i = 5; i >= 0; i--) begin
for (int i = 6; i >= 0; i--) begin
@ICmd.cb;
ICmd.cb.Cmd <= crc[i];
end
/sdhc-sc-core/trunk/src/grpSd/pkgSd/src/Sd-p.vhdl
35,7 → 35,7
crc7 : std_ulogic_vector(6 downto 0); -- CRC of content
endbit : std_ulogic; --cSdEndBit
end record aSdCmdToken;
 
-- Types for entities
type aSdCmdFromController is record
Content : aSdCmdContent;
46,6 → 46,9
Ack : std_ulogic; -- Gets asserted when crc was sent, but endbit was
-- not. This way we can minimize the wait time between sending 2 cmds.
Receiving : std_ulogic;
CmdContent : aSdCmdContent;
Valid : std_ulogic; -- gets asserted when CmdContent is valid (therefore
-- a cmd was received)
end record aSdCmdToController;
 
-- command ids
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
36,17 → 36,17
begin // driver for SdCardModel
card.init();
 
for (int i = 0; i < `cCmdCount; i++) begin
/*for (int i = 0; i < `cCmdCount; i++) begin
@$root.Testbed.CardRecv;
 
$display("driver2: %0d", i);
card.recv();
end
end*/
end
 
begin // checker
@$root.Testbed.InitDone;
 
/*
for (int i = 0; i < `cCmdCount; i++) begin
@$root.Testbed.CmdReceived;
$display("checker: %0d", i);
56,7 → 56,7
recvCmd.checkFromHost();
assert(recvCmd.equals(sendCmd) == 1);
-> $root.Testbed.GenCmd;
end
end*/
end
 
join;
/sdhc-sc-core/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
14,6 → 14,7
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/state
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextstate
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/serialcrc
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crccorrect
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/counter
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextcounter
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/output
22,8 → 23,20
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/ifromcontroller
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/iclk
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/receivedtoken
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/nextreceivedtoken
add wave -noupdate -divider Crc
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/iclear
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/idatain
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/idata
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/oiscorrect
add wave -noupdate -format Logic /Testbed/top/sdcmd_inst/crc7_inst/oserial
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/crc7_inst/oparallel
add wave -noupdate -format Literal /Testbed/top/sdcmd_inst/crc7_inst/regs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {365 ns} 0}
WaveRestoreCursors {{Cursor 1} {2937 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
38,4 → 51,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {20068053 ns} {20069966 ns}
WaveRestoreZoom {1133 ns} {3046 ns}
/sdhc-sc-core/trunk/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
29,7 → 29,8
 
architecture Rtl of SdCmd is
 
type aSdCmdState is (idle, startbit, transbit, cmdid, arg, crc, endbit);
type aSdCmdState is (idle, startbit, transbit, cmdid, arg, crc, endbit,
recvtransbit, recvcmdid, recvarg, recvcrc, recvendbit, recvcrcerror);
 
type aCrcOut is record
Clear : std_ulogic;
44,13 → 45,16
end record aSdCmdOut;
 
signal State, NextState : aSdCmdState;
signal SerialCrc : std_ulogic;
signal SerialCrc, CrcCorrect : std_ulogic;
signal Counter, NextCounter : unsigned(integer(log2(real(32))) - 1 downto 0);
signal Output : aSdCmdOut;
 
constant cDefaultOut : aSdCmdOut := ((cInactivated, cInactivated,
cInactivated), (Ack => cInactivated, Receiving => cInactivated), 'Z');
constant cDefaultOut : aSdCmdOut := ((cInactivated, cInactivated,cInactivated),
(Ack => cInactivated, Receiving => cInactivated, Valid => cInactivated,
CmdContent => (id => (others => '0'), arg => (others => '0'))), 'Z');
 
signal ReceivedToken, NextReceivedToken : aSdCmdToken;
 
begin
 
ioCmd <= Output.Cmd;
65,11 → 69,12
elsif iClk'event and iClk = cActivated then
State <= NextState;
Counter <= NextCounter;
ReceivedToken <= NextReceivedToken;
end if;
end process CmdStateReg;
 
-- Comb. process
NextStateAndOutput : process (iFromController, ioCmd, SerialCrc, State, Counter)
NextStateAndOutput : process (iFromController, ioCmd, SerialCrc, CrcCorrect, State, Counter)
 
procedure NextStateWhenAllSent (constant nextlength : in natural; constant toState : in aSdCmdState) is
begin
81,40 → 86,56
end if;
end procedure NextStateWhenAllSent;
 
procedure ShiftIntoCrc(constant data : in std_ulogic) is
begin
Output.Crc.DataIn <= cActivated;
Output.Crc.Data <= data;
end procedure;
 
procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector;
constant toState : in aSdCmdState; constant nextlength : in natural) is
begin
Output.Cmd <= container(to_integer(Counter));
Output.Crc.Data <= container(to_integer(Counter));
Output.Crc.DataIn <= cActivated;
ShiftIntoCrc(container(to_integer(Counter)));
NextStateWhenAllSent(nextlength, toState);
end procedure SendBitsAndCalcCrc;
 
procedure RecvBitsAndCalcCrc (signal container : inout std_ulogic_vector;
constant toState : in aSdCmdState; constant nextlength : in natural) is
begin
container(to_integer(Counter)) <= ioCmd;
ShiftIntoCrc(ioCmd);
NextStateWhenAllSent(nextlength, toState);
end procedure RecvBitsAndCalcCrc;
 
 
begin
-- CRC calculation needs one cycle. Therefore we have to start it
-- ahead of putting the data on ioCmd.
 
-- defaults
NextState <= State;
NextCounter <= Counter;
NextReceivedToken <= ReceivedToken;
Output <= cDefaultOut;
Output.Controller.CmdContent <= ReceivedToken.content;
 
case State is
when idle =>
if (iFromController.Valid = cActivated) then
-- Start receiving or start transmitting
if (ioCmd = cSdStartBit) then
ShiftIntoCrc(ioCmd);
NextReceivedToken.startbit <= ioCmd;
NextState <= recvtransbit;
elsif (iFromController.Valid = cActivated) then
NextState <= startbit;
end if;
 
when startbit =>
Output.Cmd <= cSdStartBit;
Output.Crc.DataIn <= cActivated;
Output.Crc.Data <= cSdStartBit;
ShiftIntoCrc(cSdStartBit);
NextState <= transbit;
 
when transbit =>
Output.Cmd <= cSdTransBitHost;
Output.Crc.DataIn <= cActivated;
Output.Crc.Data <= cSdTransBitHost;
ShiftIntoCrc(cSdTransBitHost);
NextCounter <= to_unsigned(iFromController.Content.id'high,
NextCounter'length);
NextState <= cmdid;
139,6 → 160,43
Output.Cmd <= cSdEndBit;
NextState <= idle; -- todo: receive response
 
when recvtransbit =>
Output.Controller.Receiving <= cActivated;
ShiftIntoCrc(ioCmd);
NextReceivedToken.transbit <= ioCmd;
NextCounter <= to_unsigned(NextReceivedToken.Content.id'high,
NextCounter'length);
NextState <= recvcmdid;
 
when recvcmdid =>
Output.Controller.Receiving <= cActivated;
RecvBitsAndCalcCrc(NextReceivedToken.Content.id, recvarg,
NextReceivedToken.Content.arg'high);
 
when recvarg =>
Output.Controller.Receiving <= cActivated;
RecvBitsAndCalcCrc(NextReceivedToken.Content.arg, recvcrc,
crc7'high-1);
 
when recvcrc =>
NextReceivedToken.crc7(to_integer(Counter)) <= ioCmd;
ShiftIntoCrc(ioCmd);
 
if (Counter > 0) then
NextCounter <= Counter - 1;
else
NextState <= recvendbit;
end if;
 
when recvendbit =>
NextReceivedToken.endbit <= ioCmd;
 
-- check
if (CrcCorrect = cActivated) then
Output.Controller.Valid <= cActivated;
end if;
NextState <= idle;
 
when others =>
report "SdCmd: State not handled" severity error;
end case;
151,6 → 209,7
iClear => Output.Crc.Clear,
iDataIn => Output.Crc.DataIn,
iData => Output.Crc.Data,
oIsCorrect => CrcCorrect,
oSerial => SerialCrc);
 
end architecture Rtl;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.