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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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    from Rev 551 to Rev 552
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Rev 551 → Rev 552

/trunk/or1ksim/testbench/mc_sync.h
21,6 → 21,9
#ifndef __MC_SYNC_H
#define __MC_SYNC_H
 
/* should configuration be read from MC? */
#define MC_READ_CONF
 
/* TEMPLATE SELECTION */
/* change #undef to #define */
#define _MC_TEST_TEMPLATE1
33,10 → 36,10
 
typedef struct MC_SYNC_CS
{
unsigned char M;
unsigned long M;
} MC_SYNC_CS;
 
MC_SYNC_CS mc_async_cs[8] = {
MC_SYNC_CS mc_sync_cs[8] = {
{ 0x02 /* SELect mask */
},
{ 0x04 },
/trunk/or1ksim/testbench/mc_async.h
21,6 → 21,9
#ifndef __MC_ASYNC_H
#define __MC_ASYNC_H
 
/* should configuration be readm from MC? */
#define MC_READ_CONF
 
/* TEMPLATE SELECTION */
/* change #undef to #define */
#define _MC_TEST_TEMPLATE1
33,8 → 36,8
 
typedef struct MC_ASYNC_CS
{
unsigned char BW;
unsigned char M;
unsigned long BW;
unsigned long M;
} MC_ASYNC_CS;
 
MC_ASYNC_CS mc_async_cs[8] = {
/trunk/or1ksim/testbench/mc_common.c
424,7 → 424,7
mc_clear_row(nFrom, nTo);
} /*for nSize*/
} /*for nSeq*/
report(0xDEADDEAD);
/*report(0xDEADDEAD);*/
} /*for nRun*/
 
return 0;
/trunk/or1ksim/testbench/mc_dram.c
26,10 → 26,17
#include "../peripheral/gpio.h"
#include "../peripheral/fields.h"
 
#define T_ROW_SIZE 8
#define T_ROW_OFF 5
#define T_ROWS 25
#define T_GROUPS 3
 
typedef volatile unsigned long *REGISTER;
 
/*
unsigned long nRowSize = 0;
unsigned long nColumns = 0;
*/
REGISTER mc_poc = (unsigned long*)(MC_BASE + MC_POC);
REGISTER mc_csr = (unsigned long*)(MC_BASE + MC_CSR);
REGISTER mc_ba_mask = (unsigned long*)(MC_BASE + MC_BA_MASK);
38,6 → 45,7
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
 
unsigned long lpoc;
unsigned char mc_cs;
 
unsigned long set_config()
{
58,6 → 66,33
return 0;
}
 
unsigned long get_config()
{
REGISTER mc_csc;
REGISTER mc_tms;
unsigned char ch;
 
mc_cs = 0;
for (ch=0; ch<8; ch++) {
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 0) &&
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
mc_sdram_cs[ch].MS = GET_FIELD(*mc_csc, MC_CSC, MS);
mc_sdram_cs[ch].BW = GET_FIELD(*mc_csc, MC_CSC, BW);
mc_sdram_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
mc_cs |= (1 << ch);
 
printf("get_config(%d) : MS=0x%0lx, BW=0x%0lx, M=0x%0lx\n", ch,
mc_sdram_cs[ch].MS,
mc_sdram_cs[ch].BW,
mc_sdram_cs[ch].M);
}
}
printf("get_config() : cs=0x%0x\n", mc_cs);
return 0;
}
 
int main()
{
unsigned long ret;
71,12 → 106,11
unsigned long nRows = 0;
unsigned long nRowSh = 0;
unsigned long nRowGrp = 0;
unsigned long nGroups = 0;
 
unsigned long nAddress;
unsigned long mc_sel;
REGISTER mc_tms;
REGISTER mc_cs;
REGISTER mc_csc;
 
*rgpio_out = 0xFFFFFFFF;
 
83,18 → 117,24
/* set configuration */
randomin(7435);
lpoc = *mc_poc;
/* MC configuration set in except_mc.S prior to execution of main()
if ( (ret = set_config()) != 0) {
exit(ret);
 
#ifdef MC_READ_CONF
if (get_config()) {
printf("Error reading MC configuration\n");
report(0x00000001);
return(1);
}
*/
#else
mc_cs = MC_SDRAM_CSMASK;
#endif
 
for (ch=0; ch<8; ch++) {
if (MC_SDRAM_CSMASK & (0x01 << ch) ) {
if (mc_cs & (0x01 << ch) ) {
printf ("--- Begin Test on CS%d ---\n", ch);
 
mc_cs = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
mc_sel = GET_FIELD(*mc_cs, MC_CSC, SEL);
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
SET_FIELD(*mc_tms, MC_TMS_SDRAM, OM, 0); /*normal op*/
SET_FIELD(*mc_tms, MC_TMS_SDRAM, CL, 3); /*CAS*/
133,15 → 173,15
}
 
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lX, rs = %lu, nr = %lu, sh = %lu, sel = %lu\n",
*mc_cs, *mc_tms, nRowSize, nRows, nRowSh, mc_sel);
*mc_csc, *mc_tms, nRowSize, nRows, nRowSh, mc_sel);
 
nRows -= MC_SDRAM_ROW_OFF;
/*nRows -= MC_SDRAM_ROW_OFF;*/
for (test=0; test<16; test++) {
/* configure MC*/
CLEAR_FLAG(*mc_cs, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_cs, MC_CSC, KRO); /* close row */
CLEAR_FLAG(*mc_cs, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_cs, MC_CSC, WP); /* write enable */
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_csc, MC_CSC, KRO); /* close row */
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
SET_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* single loc access */
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* sequential burst */
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 0); /* 1 */
153,22 → 193,22
case 1:
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST1) != MC_SDRAM_TEST1)
continue;
SET_FLAG(*mc_cs, MC_CSC, PEN); /* parity */
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
break;
case 2:
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST2) != MC_SDRAM_TEST2)
continue;
SET_FLAG(*mc_cs, MC_CSC, KRO); /* keep row */
SET_FLAG(*mc_csc, MC_CSC, KRO); /* keep row */
break;
case 3:
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST3) != MC_SDRAM_TEST3)
continue;
SET_FLAG(*mc_cs, MC_CSC, BAS); /* bank after row*/
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row*/
break;
case 4:
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST4) != MC_SDRAM_TEST4)
continue;
SET_FLAG(*mc_cs, MC_CSC, WP); /* RO */
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
break;
case 5:
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST5) != MC_SDRAM_TEST5)
236,7 → 276,7
case 15:
if ((MC_SDRAM_TESTS & MC_SDRAM_TEST15) != MC_SDRAM_TEST15)
continue;
SET_FLAG(*mc_cs, MC_CSC, KRO); /* keep row */
SET_FLAG(*mc_csc, MC_CSC, KRO); /* keep row */
CLEAR_FLAG(*mc_tms, MC_TMS_SDRAM, WBL); /* burst */
SET_FLAG(*mc_tms, MC_TMS_SDRAM, BT); /* interleaved burst */
SET_FIELD(*mc_tms, MC_TMS_SDRAM, BL, 1); /* 2 */
243,19 → 283,19
break;
} /*switch test*/
 
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_cs, *mc_tms);
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
 
if (MC_SDRAM_ACC & MC_SDRAM_SROW) {
/* perform sequential row access */
printf("Seuential Row\n");
for (j=MC_SDRAM_ROW_OFF; j<nRows/2; j++) {
for (j=0; j<T_ROWS; j++) {
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;
nAddress += (j << nRowSh);
nAddress += ( (j + T_ROW_OFF) << nRowSh);
 
gpio_pat ^= 0x00000008;
*rgpio_out = gpio_pat;
ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
 
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
 
271,14 → 311,14
if (MC_SDRAM_ACC & MC_SDRAM_RROW) {
/* perform random row access */
printf("Random Row\n");
for (j=MC_SDRAM_ROW_OFF; j<nRows/2; j++) {
nAddress = mc_sel << 21;
for (j=0; j<T_ROWS; j++) {
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;
nAddress += ( (MC_SDRAM_ROW_OFF + random(nRows)) << nRowSh);
 
nAddress += ( (T_ROW_OFF + random(nRows)) << nRowSh);
gpio_pat ^= 0x00000008;
*rgpio_out = gpio_pat;
ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
285,6 → 325,7
if (ret) {
gpio_pat ^= 0x00000080;
*rgpio_out = gpio_pat;
report(ret);
return ret;
}
}
294,11 → 335,10
/* perform sequential row in group access */
printf("Sequential Group ");
nGroups = MC_SDRAM_GROUPSIZE;
printf("Group Size = %lu\n", nGroups);
for (i=nRows/nGroups-1; i<nRows/nGroups; i++) {
nRowGrp = random(nRows - nGroups) + MC_SDRAM_ROW_OFF;
for (j=0; j<nGroups; j++) {
printf("Group Size = %d\n", MC_SDRAM_GROUPSIZE);
for (i=0; i<T_GROUPS; i++) {
nRowGrp = random(nRows - MC_SDRAM_GROUPSIZE) + T_ROW_OFF;
for (j=0; j<MC_SDRAM_GROUPSIZE; j++) {
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;
nAddress += ((nRowGrp+j) << nRowSh);
305,7 → 345,7
 
gpio_pat ^= 0x00000008;
*rgpio_out = gpio_pat;
ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
 
323,18 → 363,17
/* perform random row in group access */
printf("Random Group ");
 
nGroups = MC_SDRAM_GROUPSIZE;
printf("Group Size = %lu\n", nGroups);
for (i=(nRows/nGroups)-1; i<nRows/nGroups; i++) {
nRowGrp = random(nRows - nGroups) + MC_SDRAM_ROW_OFF;
for (j=0; j<nGroups; j++) {
printf("Group Size = %d\n", MC_SDRAM_GROUPSIZE);
for (i=0; i<T_GROUPS; i++) {
nRowGrp = random(nRows - T_GROUPS) + T_ROW_OFF;
for (j=0; j<MC_SDRAM_GROUPSIZE; j++) {
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;
nAddress += ((nRowGrp + random(nGroups)) << nRowSh);
nAddress += ((nRowGrp + random(MC_SDRAM_GROUPSIZE)) << nRowSh);
gpio_pat ^= 0x00000008;
*rgpio_out = gpio_pat;
ret = mc_test_row(nAddress, nAddress + nRowSize, MC_SDRAM_FLAGS);
ret = mc_test_row(nAddress, nAddress + T_ROW_SIZE, MC_SDRAM_FLAGS);
printf("\trow - %lu: nAddress = 0x%08lX, ret = 0x%08lX\n", j, nAddress, ret);
 
/trunk/or1ksim/testbench/mc_ssram.c
36,6 → 36,7
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
 
unsigned long lpoc;
unsigned char mc_cs;
 
unsigned long set_config()
{
56,6 → 57,29
return 0;
}
 
unsigned long get_config()
{
REGISTER mc_csc;
REGISTER mc_tms;
unsigned char ch;
 
mc_cs = 0;
for (ch=0; ch<8; ch++) {
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 1) &&
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
mc_ssram_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
mc_cs |= (1 << ch);
 
printf("get_config(%d) : M=0x%0lx\n", ch,
mc_ssram_cs[ch].M);
}
}
printf("get_config() : cs=0x%0x\n", mc_cs);
return 0;
}
 
int main()
{
unsigned long ret;
69,34 → 93,37
unsigned long mc_sel;
 
REGISTER mc_tms;
REGISTER mc_cs;
REGISTER mc_csc;
 
*rgpio_out = 0xFFFFFFFF;
 
/* set configuration */
/* MC configuration set by except_mc.S prior to execution of main()
if ( (ret = set_config()) != 0) {
exit(ret);
}
*/
#ifdef MC_READ_CONF
if (get_config()) {
printf("Error reading MC configuration\n");
report(0x000000001);
return(1);
}
#else
mc_cs = MC_SSRAM_CSMASK;
#endif
 
*rgpio_out = 0;
for (ch=0; ch<8; ch++) {
if (MC_SSRAM_CSMASK && (0x01 << ch) ) {
if (mc_cs & (0x01 << ch) ) {
printf ("--- Begin Test on CS%d ---\n", ch);
 
mc_cs = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
mc_sel = GET_FIELD(*mc_cs, MC_CSC, SEL);
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
 
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
*mc_cs, *mc_tms);
*mc_csc, *mc_tms);
for (test=0; test<4; test++) {
/* configure MC*/
CLEAR_FLAG(*mc_cs, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_cs, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_cs, MC_CSC, WP); /* write enable */
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
switch (test) {
case 0:
106,21 → 133,21
case 1:
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST1) != MC_SSRAM_TEST1)
continue;
SET_FLAG(*mc_cs, MC_CSC, PEN); /* parity */
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
break;
case 2:
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST2) != MC_SSRAM_TEST2)
continue;
SET_FLAG(*mc_cs, MC_CSC, BAS); /* bank after row */
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
break;
case 3:
if ((MC_SSRAM_TESTS & MC_SSRAM_TEST3) != MC_SSRAM_TEST3)
continue;
SET_FLAG(*mc_cs, MC_CSC, WP); /* RO */
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
break;
} /*switch test*/
 
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_cs, *mc_tms);
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
 
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;
/trunk/or1ksim/testbench/mc_dram.h
21,15 → 21,18
#ifndef __MC_DRAM_H
#define __MC_DRAM_H
 
/* should configuration be read from MC? */
#define MC_READ_CONF
 
/* TEMPLATE SELECTION */
/* change #undef to #define */
#define _MC_TEST_TEMPLATE1
#undef _MC_TEST_TEMPLATE2
#undef _MC_TEST_TEMPLATE1
#define _MC_TEST_TEMPLATE2
#undef _MC_TEST_TEMPLATE3
/* ------------------------ */
 
 
/* memory configuration that must reflect mcmem.cfg */
/* memory configuration that must reflect sim.cfg */
#define MC_SDRAM_CSMASK 0x02 /* 8 bit mask for 8 chip selects. 1 SDRAM at CS, 0 something else at CS */
/* bits: CS7|CS6|CS5|CS4|CS3|CS2|CS1|CS0 */
typedef struct MC_SDRAM_CS
41,10 → 44,10
 
MC_SDRAM_CS mc_sdram_cs[8] = {
{ 2, /* Bus Width : 0 - 8bit, 1 - 16bit, 2 - 32bit */
0, /* Memory Size : 0 - 64Mbit, 1 - 128Mbit, 2 - 256Mbit */
0x02 /* SELect mask */
2, /* Memory Size : 0 - 64Mbit, 1 - 128Mbit, 2 - 256Mbit */
0x20 /* SELect mask */
},
{ 1, 0, 0x00 },
{ 1, 0, 0x20 },
{ 2, 0, 0x06 },
{ 2, 0, 0x08 },
{ 2, 0, 0x0A },
117,7 → 120,7
#define MC_SDRAM_ROWS_7 25/* 512 */
#define MC_SDRAM_ROWS_8 25/* 256 */
 
#define MC_SDRAM_ROW_OFF 128
#define MC_SDRAM_ROW_OFF 5
#endif /*_MC_TEST_TEMPLATE1*/
 
/* TEMPLATE 2 */
128,28 → 131,27
 
/* memory sizes*/
#define MC_SDRAM_GROUPSIZE 5
/* MAX */
#define MC_SDRAM_ROWSIZE_0 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_1 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_2 8/* 8 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_3 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_4 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_5 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_6 8/* 32 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_7 8/* 32 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_8 8/* 32 * 1024 * 4 */
/* MAX */
#define MC_SDRAM_ROWS_0 25/* 512 */
#define MC_SDRAM_ROWS_1 25/* 256 */
#define MC_SDRAM_ROWS_2 25/* 256 */
#define MC_SDRAM_ROWS_3 25/* 1024 */
#define MC_SDRAM_ROWS_4 25/* 512 */
#define MC_SDRAM_ROWS_5 25/* 256 */
#define MC_SDRAM_ROWS_6 25/* 1024 */
#define MC_SDRAM_ROWS_7 25/* 512 */
#define MC_SDRAM_ROWS_8 25/* 256 */
#define MC_SDRAM_ROWSIZE_0 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_1 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_2 8 * 1024 * 4
#define MC_SDRAM_ROWSIZE_3 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_4 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_5 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_6 32 * 1024 * 4
#define MC_SDRAM_ROWSIZE_7 32 * 1024 * 4
#define MC_SDRAM_ROWSIZE_8 32 * 1024 * 4
#define MC_SDRAM_ROWS_0 512
#define MC_SDRAM_ROWS_1 256
#define MC_SDRAM_ROWS_2 256
#define MC_SDRAM_ROWS_3 1024
#define MC_SDRAM_ROWS_4 512
#define MC_SDRAM_ROWS_5 256
#define MC_SDRAM_ROWS_6 1024
#define MC_SDRAM_ROWS_7 512
#define MC_SDRAM_ROWS_8 256
 
#define MC_SDRAM_ROW_OFF 128
#endif /*_MC_TEST_TEMPLATE2*/
 
/* TEMPLATE 3 */
161,27 → 163,26
/* memory sizes*/
#define MC_SDRAM_GROUPSIZE 5
/* MAX */
#define MC_SDRAM_ROWSIZE_0 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_1 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_2 8/* 8 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_3 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_4 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_5 8/* 16 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_6 8/* 32 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_7 8/* 32 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_8 8/* 32 * 1024 * 4 */
#define MC_SDRAM_ROWSIZE_0 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_1 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_2 8 * 1024 * 4
#define MC_SDRAM_ROWSIZE_3 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_4 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_5 16 * 1024 * 4
#define MC_SDRAM_ROWSIZE_6 32 * 1024 * 4
#define MC_SDRAM_ROWSIZE_7 32 * 1024 * 4
#define MC_SDRAM_ROWSIZE_8 32 * 1024 * 4
/* MAX */
#define MC_SDRAM_ROWS_0 25/* 512 */
#define MC_SDRAM_ROWS_1 25/* 256 */
#define MC_SDRAM_ROWS_2 25/* 256 */
#define MC_SDRAM_ROWS_3 25/* 1024 */
#define MC_SDRAM_ROWS_4 25/* 512 */
#define MC_SDRAM_ROWS_5 25/* 256 */
#define MC_SDRAM_ROWS_6 25/* 1024 */
#define MC_SDRAM_ROWS_7 25/* 512 */
#define MC_SDRAM_ROWS_8 25/* 256 */
#define MC_SDRAM_ROWS_0 10/* 512 */
#define MC_SDRAM_ROWS_1 10/* 256 */
#define MC_SDRAM_ROWS_2 10/* 256 */
#define MC_SDRAM_ROWS_3 10/* 1024 */
#define MC_SDRAM_ROWS_4 10/* 512 */
#define MC_SDRAM_ROWS_5 10/* 256 */
#define MC_SDRAM_ROWS_6 10/* 1024 */
#define MC_SDRAM_ROWS_7 10/* 512 */
#define MC_SDRAM_ROWS_8 10/* 256 */
 
#define MC_SDRAM_ROW_OFF 128
#endif /*_MC_TEST_TEMPLATE3*/
 
#endif
/trunk/or1ksim/testbench/mc_ssram.h
21,6 → 21,9
#ifndef __MC_SSRAM_H
#define __MC_SSRAM_H
 
/* should configuration be read form MC? */
#define MC_READ_CONF
 
/* TEMPLATE SELECTION */
/* change #undef to #define */
#define _MC_TEST_TEMPLATE1
33,7 → 36,7
 
typedef struct MC_SSRAM_CS
{
unsigned char M;
unsigned long M;
} MC_SSRAM_CS;
 
MC_SSRAM_CS mc_ssram_cs[8] = {
/trunk/or1ksim/testbench/mc_sync.c
36,6 → 36,7
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
 
unsigned long lpoc;
unsigned char mc_cs;
 
unsigned long set_config()
{
47,7 → 48,7
for (ch=0; ch<8; ch++) {
if (MC_SYNC_CSMASK & (0x01 << ch) ) {
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
SET_FIELD(*mc_csc, MC_CSC, SEL, mc_async_cs[ch].M);
SET_FIELD(*mc_csc, MC_CSC, SEL, mc_sync_cs[ch].M);
SET_FIELD(*mc_csc, MC_CSC, BW, 2);
SET_FLAG(*mc_csc, MC_CSC, EN);
printf ("Channel Config %d - CSC = 0x%08lX\n", ch, *mc_csc);
57,6 → 58,29
return 0;
}
 
unsigned long get_config()
{
REGISTER mc_csc;
REGISTER mc_tms;
unsigned char ch;
 
mc_cs = 0;
for (ch=0; ch<8; ch++) {
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 3) &&
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
mc_sync_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
mc_cs |= (1 << ch);
 
printf("get_config(%d) : M=0x%0lx\n", ch,
mc_sync_cs[ch].M);
}
}
printf("get_config() : cs=0x%0x\n", mc_cs);
return 0;
}
 
int main()
{
unsigned long ret;
69,32 → 93,37
unsigned long nMemSize;
unsigned long mc_sel;
REGISTER mc_tms;
REGISTER mc_cs;
REGISTER mc_csc;
 
*rgpio_out = 0xFFFFFFFF;
/* set configuration */
/* MC configuration set by except_mc.S prior to execution of main()
if ( (ret = set_config()) != 0) {
exit(ret);
}
*/
 
#ifdef MC_READ_CONF
if (get_config()) {
printf("Error reading MC configuration.\n");
report(1);
return(1);
}
#else
mc_cs = MC_ASYNC_CSMASK;
#endif
 
*rgpio_out = 0;
for (ch=0; ch<8; ch++) {
if (MC_SYNC_CSMASK & (0x01 << ch) ) {
printf ("--- Begin Test on CS%d ---\n", ch);
 
mc_cs = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
mc_sel = GET_FIELD(*mc_cs, MC_CSC, SEL);
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
 
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
*mc_cs, *mc_tms);
*mc_csc, *mc_tms);
 
for (test=0; test<4; test++) {
/* configure MC*/
CLEAR_FLAG(*mc_cs, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_cs, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_cs, MC_CSC, WP); /* write enable */
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
switch (test) {
case 0:
104,21 → 133,21
case 1:
if ((MC_SYNC_TESTS & MC_SYNC_TEST1) != MC_SYNC_TEST1)
continue;
SET_FLAG(*mc_cs, MC_CSC, PEN); /* parity */
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
break;
case 2:
if ((MC_SYNC_TESTS & MC_SYNC_TEST2) != MC_SYNC_TEST2)
continue;
SET_FLAG(*mc_cs, MC_CSC, BAS); /* bank after row */
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
break;
case 3:
if ((MC_SYNC_TESTS & MC_SYNC_TEST3) != MC_SYNC_TEST3)
continue;
SET_FLAG(*mc_cs, MC_CSC, WP); /* RO */
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
break;
} /*switch test*/
 
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_cs, *mc_tms);
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
 
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;
/trunk/or1ksim/testbench/mc_async.c
36,6 → 36,7
REGISTER rgpio_in = (unsigned long*)(GPIO_BASE + RGPIO_IN);
 
unsigned long lpoc;
unsigned char mc_cs;
 
unsigned long set_config()
{
57,6 → 58,31
return 0;
}
 
unsigned long get_config()
{
REGISTER mc_csc;
REGISTER mc_tms;
unsigned char ch;
 
mc_cs = 0;
for (ch=0; ch<8; ch++) {
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
if ( (GET_FIELD(*mc_csc, MC_CSC, MEMTYPE) == 2) &&
(TEST_FLAG(*mc_csc, MC_CSC, EN) == 1 ) ) {
mc_async_cs[ch].BW = GET_FIELD(*mc_csc, MC_CSC, BW);
mc_async_cs[ch].M = GET_FIELD(*mc_csc, MC_CSC, SEL);
mc_cs |= (1 << ch);
 
printf("get_config(%d) : BW=0x%0lx, M=0x%0lx\n", ch,
mc_async_cs[ch].BW,
mc_async_cs[ch].M);
}
}
printf("get_config() : cs=0x%0x\n", mc_cs);
return 0;
}
 
int main()
{
unsigned long ret;
69,32 → 95,35
unsigned long nMemSize;
unsigned long mc_sel;
REGISTER mc_tms;
REGISTER mc_cs;
REGISTER mc_csc;
 
*rgpio_out = 0xFFFFFFFF;
/* set configuration */
/* MC initialization done in except_mc.S prior to execution of main()
if ( (ret = set_config()) != 0) {
exit(ret);
}
*/
#ifdef MC_READ_CONF
if (get_config()) {
printf("Error reading MC configuration.\n");
report(1);
return(1);
}
#else
mc_cs = MC_ASYNC_CSMASK;
#endif
 
for (ch=0; ch<8; ch++) {
if (MC_ASYNC_CSMASK & (0x01 << ch) ) {
if (mc_cs & (0x01 << ch) ) {
printf ("--- Begin Test on CS%d ---\n", ch);
 
mc_cs = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_csc = (unsigned long*)(MC_BASE + MC_CSC(ch));
mc_tms = (unsigned long*)(MC_BASE + MC_TMS(ch));
mc_sel = GET_FIELD(*mc_cs, MC_CSC, SEL);
mc_sel = GET_FIELD(*mc_csc, MC_CSC, SEL);
 
printf ("CS configuration : CSC - 0x%08lX, TMS - 0x%08lXu\n",
*mc_cs, *mc_tms);
*mc_csc, *mc_tms);
 
for (test=0; test<4; test++) {
/* configure MC*/
CLEAR_FLAG(*mc_cs, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_cs, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_cs, MC_CSC, WP); /* write enable */
CLEAR_FLAG(*mc_csc, MC_CSC, PEN); /* no parity */
CLEAR_FLAG(*mc_csc, MC_CSC, BAS); /* bank after column */
CLEAR_FLAG(*mc_csc, MC_CSC, WP); /* write enable */
switch (test) {
case 0:
104,21 → 133,21
case 1:
if ((MC_ASYNC_TESTS & MC_ASYNC_TEST1) != MC_ASYNC_TEST1)
continue;
SET_FLAG(*mc_cs, MC_CSC, PEN); /* parity */
SET_FLAG(*mc_csc, MC_CSC, PEN); /* parity */
break;
case 2:
if ((MC_ASYNC_TESTS & MC_ASYNC_TEST2) != MC_ASYNC_TEST2)
continue;
SET_FLAG(*mc_cs, MC_CSC, BAS); /* bank after row */
SET_FLAG(*mc_csc, MC_CSC, BAS); /* bank after row */
break;
case 3:
if ((MC_ASYNC_TESTS & MC_ASYNC_TEST3) != MC_ASYNC_TEST3)
continue;
SET_FLAG(*mc_cs, MC_CSC, WP); /* RO */
SET_FLAG(*mc_csc, MC_CSC, WP); /* RO */
break;
} /*switch test*/
 
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_cs, *mc_tms);
printf ("Begin TEST %lu : CSC - 0x%08lX, TMS - 0x%08lX\n", test, *mc_csc, *mc_tms);
 
nAddress = mc_sel << 21;
nAddress |= MC_MEM_BASE;

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