URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 555 to Rev 556
- ↔ Reverse comparison
Rev 555 → Rev 556
/openrisc/trunk/or1ksim/sim-config.h
152,6 → 152,11
|
struct |
{ |
int enabled; /* Are performance counters enabled? */ |
} pcu; |
|
struct |
{ |
int enabled; /* branch prediction buffer analysis */ |
int sbp_bnf_fwd; /* Static BP for l.bnf uses fwd predn */ |
int sbp_bf_fwd; /* Static BP for l.bf uses fwd predn */ |
/openrisc/trunk/or1ksim/Makefile.in
108,8 → 108,8
cpu/or1k/libor1k.la support/libsupport.la mmu/libmmu.la \ |
bpb/libbpb.la cache/libcache.la peripheral/libperipheral.la \ |
peripheral/channels/libchannels.la tick/libtick.la pm/libpm.la \ |
pic/libpic.la debug/libdebug.la vapi/libvapi.la cuc/libcuc.la \ |
softfloat/libsoftfloat.la port/libport.la |
pic/libpic.la debug/libdebug.la pcu/libpcu.la vapi/libvapi.la \ |
cuc/libcuc.la softfloat/libsoftfloat.la port/libport.la |
am_libor1ksys_la_OBJECTS = cpu-config.lo mprofiler.lo profiler.lo \ |
sim-cmd.lo sim-config.lo toplevel-support.lo |
libor1ksys_la_OBJECTS = $(am_libor1ksys_la_OBJECTS) |
347,6 → 347,7
pm \ |
pic \ |
debug \ |
pcu \ |
vapi \ |
cuc \ |
port \ |
384,6 → 385,7
pm/libpm.la \ |
pic/libpic.la \ |
debug/libdebug.la \ |
pcu/libpcu.la \ |
vapi/libvapi.la \ |
cuc/libcuc.la \ |
softfloat/libsoftfloat.la \ |
/openrisc/trunk/or1ksim/cpu/or32/insnset.c
711,12 → 711,17
uint16_t regno = PARAM1 | PARAM2; |
uorreg_t value = mfspr(regno); |
|
if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) |
if ((cpu_state.sprs[SPR_SR] & SPR_SR_SM) || |
// TODO: Check if this SPR should actually be allowed to be read with |
// SR's SM==0 and SUMRA==1 |
(!(cpu_state.sprs[SPR_SR] & SPR_SR_SM) && |
(cpu_state.sprs[SPR_SR] & SPR_SR_SUMRA))) |
SET_PARAM0(value); |
else { |
SET_PARAM0(0); |
PRINTF("WARNING: trying to read SPR while SR[SUPV] is cleared.\n"); |
sim_done(); |
else |
{ |
SET_PARAM0(0); |
PRINTF("WARNING: trying to read SPR while SR[SUPV] and SR[SUMRA] is cleared.\n"); |
sim_done(); |
} |
} |
INSTRUCTION (l_sys) { |
/openrisc/trunk/or1ksim/cpu/common/abstract.c
47,6 → 47,7
#include "dmmu.h" |
#include "immu.h" |
#include "execute.h" |
#include "pcu.h" |
|
/*! Global temporary variable to increase speed. */ |
struct dev_memarea *cur_area; |
486,13 → 487,16
return 0; |
} |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); /* 28/05/01 CZ */ |
|
phys_memaddr = dmmu_translate (memaddr, 0); |
if (except_pending) |
return 0; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_LA); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); |
|
if (config.dc.enabled) |
temp = dc_simulate_read (phys_memaddr, memaddr, 4); |
else |
499,7 → 503,7
temp = evalsim_mem32 (phys_memaddr, memaddr); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadData, temp); /* MM170901 */ |
*breakpoint += check_debug_unit (DebugLoadData, temp); |
|
return temp; |
} |
564,6 → 568,9
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugInstructionFetch, memaddr); |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_IF); |
|
if ((NULL != ic_state) && ic_state->enabled) |
temp = ic_simulate_fetch (phys_memaddr, memaddr); |
else |
593,13 → 600,16
return 0; |
} |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); /* 28/05/01 CZ */ |
|
phys_memaddr = dmmu_translate (memaddr, 0); |
if (except_pending) |
return 0; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_LA); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); |
|
if (config.dc.enabled) |
temp = dc_simulate_read (phys_memaddr, memaddr, 2); |
else |
606,7 → 616,7
temp = evalsim_mem16 (phys_memaddr, memaddr); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadData, temp); /* MM170901 */ |
*breakpoint += check_debug_unit (DebugLoadData, temp); |
|
return temp; |
} |
661,13 → 671,16
if (config.sim.mprofile) |
mprofile (memaddr, MPROF_8 | MPROF_READ); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); /* 28/05/01 CZ */ |
|
phys_memaddr = dmmu_translate (memaddr, 0); |
if (except_pending) |
return 0; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_LA); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadAddress, memaddr); |
|
if (config.dc.enabled) |
temp = dc_simulate_read (phys_memaddr, memaddr, 1); |
else |
674,7 → 687,7
temp = evalsim_mem8 (phys_memaddr, memaddr); |
|
if (config.debug.enabled) |
*breakpoint += check_debug_unit (DebugLoadData, temp); /* MM170901 */ |
*breakpoint += check_debug_unit (DebugLoadData, temp); |
return temp; |
} |
|
821,6 → 834,9
if (except_pending) |
return; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_SA); |
|
if (config.debug.enabled) |
{ |
*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */ |
902,6 → 918,9
if (except_pending) |
return; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_SA); |
|
if (config.debug.enabled) |
{ |
*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */ |
977,6 → 996,9
if (except_pending) |
return; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_SA); |
|
if (config.debug.enabled) |
{ |
*breakpoint += check_debug_unit (DebugStoreAddress, memaddr); /* 28/05/01 CZ */ |
/openrisc/trunk/or1ksim/configure.ac
335,7 → 335,7
-I\${top_srcdir}/peripheral/channels -I\${top_srcdir}/pm -I\${top_srcdir}/pic \ |
-I\${top_srcdir}/debug -I\${top_srcdir}/vapi -I\${top_srcdir}/support \ |
-I\${top_srcdir}/cuc -I\${top_srcdir}/port -I\${top_srcdir}/argtable2 \ |
-I\${top_srcdir}/softfloat" |
-I\${top_srcdir}/softfloat -I\${top_srcdir}/pcu" |
AC_SUBST(INCLUDES) |
|
AC_CONFIG_FILES([Makefile \ |
354,6 → 354,7
peripheral/channels/Makefile \ |
pm/Makefile \ |
pic/Makefile \ |
pcu/Makefile \ |
port/Makefile \ |
support/Makefile \ |
testsuite/Makefile \ |
/openrisc/trunk/or1ksim/cache/dcache-model.c
39,8 → 39,8
#include "abstract.h" |
#include "stats.h" |
#include "misc.h" |
#include "pcu.h" |
|
|
/* Data cache */ |
|
struct dc_set |
185,6 → 185,10
dc[set].way[minway].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.load_missdelay; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_DCM); |
|
|
tmp = |
dc[set].way[minway].line[(dataaddr & (config.dc.blocksize - 1)) >> 2]; |
if (width == 4) |
304,6 → 308,10
dc[set].way[i].lru--; |
dc[set].way[minway].lru = config.dc.ustates - 1; |
runtime.sim.mem_cycles += config.dc.store_missdelay; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_DCM); |
|
} |
} |
|
/openrisc/trunk/or1ksim/cache/icache-model.c
45,8 → 45,8
#include "misc.h" |
#include "stats.h" |
#include "sim-cmd.h" |
#include "pcu.h" |
|
|
#define MAX_IC_SETS 1024 |
#define MAX_IC_WAYS 32 |
#define MIN_IC_BLOCK_SIZE 16 |
175,6 → 175,11
} |
|
runtime.sim.mem_cycles += ic->missdelay; |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_ICM); |
|
|
return *(uint32_t *) & ic->mem[way | (reload_addr & ic->block_offset_mask)]; |
} |
|
/openrisc/trunk/or1ksim/doc/or1ksim.info
1441,6 → 1441,7
* Power Management Configuration:: |
* Branch Prediction Configuration:: |
* Debug Interface Configuration:: |
* Performance Counters Configuration:: |
|
|
File: or1ksim.info, Node: CPU Configuration, Next: Memory Configuration, Up: Core OpenRISC Configuration |
1472,7 → 1473,7
|
* Instruction cache present (0x00000004) |
|
* Data MMY present (0x00000008) |
* Data MMU present (0x00000008) |
|
* Instruction MMU present (0x00000010) |
|
1960,7 → 1961,7
|
|
|
File: or1ksim.info, Node: Debug Interface Configuration, Prev: Branch Prediction Configuration, Up: Core OpenRISC Configuration |
File: or1ksim.info, Node: Debug Interface Configuration, Next: Performance Counters Configuration, Prev: Branch Prediction Configuration, Up: Core OpenRISC Configuration |
|
3.3.8 Debug Interface Configuration |
----------------------------------- |
2013,6 → 2014,21
|
|
|
File: or1ksim.info, Node: Performance Counters Configuration, Prev: Debug Interface Configuration, Up: Core OpenRISC Configuration |
|
3.3.9 Performance Counters Configuration |
---------------------------------------- |
|
The performance counters unit is described in `section pcu'. This |
section may appear at most once. The following parameters may be |
specified. |
|
`enabled = 0|1' |
If 1 (true), the performance counters unit is enabled. If 0 (the |
default), it is disabled. |
|
|
|
File: or1ksim.info, Node: Peripheral Configuration, Prev: Core OpenRISC Configuration, Up: Configuration |
|
3.4 Configuring Memory Mapped Peripherals |
4145,6 → 4161,8
(line 6) |
* configuring the memory controller: Memory Controller Configuration. |
(line 6) |
* configuring the performance counters unit: Performance Counters Configuration. |
(line 6) |
* configuring the processor: CPU Configuration. (line 6) |
* configuring the PS2 interface: Keyboard Configuration. |
(line 6) |
4254,6 → 4272,8
(line 44) |
* enabled (MMU configuration): Memory Management Configuration. |
(line 12) |
* enabled (performance counters unit configuration): Performance Counters Configuration. |
(line 11) |
* enabled (power management configuration): Power Management Configuration. |
(line 35) |
* enabled (UART configuration): UART Configuration. (line 18) |
4507,6 → 4527,8
(line 82) |
* pc (Interactive CLI): Interactive Command Line. |
(line 51) |
* performance counters unit configuration: Performance Counters Configuration. |
(line 6) |
* persistent TAP device creation: Setting Up a Persistent TAP device. |
(line 6) |
* phy_addr: Ethernet Configuration. |
4671,6 → 4693,8
(line 6) |
* section memory: Memory Configuration. |
(line 6) |
* section pcu: Performance Counters Configuration. |
(line 6) |
* section pic: Interrupt Configuration. |
(line 6) |
* section pmu: Power Management Configuration. |
4865,36 → 4889,37
Node: Verification API Configuration47843 |
Node: CUC Configuration49783 |
Node: Core OpenRISC Configuration51775 |
Node: CPU Configuration52277 |
Node: Memory Configuration56396 |
Node: Memory Management Configuration63118 |
Node: Cache Configuration65495 |
Node: Interrupt Configuration67881 |
Node: Power Management Configuration69714 |
Node: Branch Prediction Configuration70991 |
Node: Debug Interface Configuration72351 |
Node: Peripheral Configuration74694 |
Node: Memory Controller Configuration75320 |
Node: UART Configuration79100 |
Node: DMA Configuration82619 |
Node: Ethernet Configuration84486 |
Node: GPIO Configuration89765 |
Node: Display Interface Configuration91398 |
Node: Frame Buffer Configuration93707 |
Node: Keyboard Configuration95571 |
Node: Disc Interface Configuration97809 |
Node: Generic Peripheral Configuration102913 |
Node: Interactive Command Line105208 |
Node: Verification API112182 |
Node: Code Internals116612 |
Node: Coding Conventions117195 |
Node: Global Data Structures121622 |
Node: Concepts124279 |
Ref: Output Redirection124424 |
Ref: Interrupts Internal124962 |
Node: Internal Debugging126115 |
Node: Regression Testing126639 |
Node: GNU Free Documentation License130428 |
Node: Index152835 |
Node: CPU Configuration52316 |
Node: Memory Configuration56435 |
Node: Memory Management Configuration63157 |
Node: Cache Configuration65534 |
Node: Interrupt Configuration67920 |
Node: Power Management Configuration69753 |
Node: Branch Prediction Configuration71030 |
Node: Debug Interface Configuration72390 |
Node: Performance Counters Configuration74776 |
Node: Peripheral Configuration75261 |
Node: Memory Controller Configuration75887 |
Node: UART Configuration79667 |
Node: DMA Configuration83186 |
Node: Ethernet Configuration85053 |
Node: GPIO Configuration90332 |
Node: Display Interface Configuration91965 |
Node: Frame Buffer Configuration94274 |
Node: Keyboard Configuration96138 |
Node: Disc Interface Configuration98376 |
Node: Generic Peripheral Configuration103480 |
Node: Interactive Command Line105775 |
Node: Verification API112749 |
Node: Code Internals117179 |
Node: Coding Conventions117762 |
Node: Global Data Structures122189 |
Node: Concepts124846 |
Ref: Output Redirection124991 |
Ref: Interrupts Internal125529 |
Node: Internal Debugging126682 |
Node: Regression Testing127206 |
Node: GNU Free Documentation License130995 |
Node: Index153402 |
|
End Tag Table |
/openrisc/trunk/or1ksim/doc/or1ksim.texi
1756,6 → 1756,7
* Power Management Configuration:: |
* Branch Prediction Configuration:: |
* Debug Interface Configuration:: |
* Performance Counters Configuration:: |
@end menu |
|
@node CPU Configuration |
1793,7 → 1794,7
@item |
Instruction cache present (0x00000004) |
@item |
Data MMY present (0x00000008) |
Data MMU present (0x00000008) |
@item |
Instruction MMU present (0x00000010) |
@item |
2467,6 → 2468,25
|
@end table |
|
|
|
@node Performance Counters Configuration |
@subsection Performance Counters Configuration |
@cindex configuring the performance counters unit |
@cindex performance counters unit configuration |
@cindex @code{section pcu} |
The performance counters unit is described in |
@code{@w{section pcu}}. This section may appear at most once. The |
following parameters may be specified. |
|
@table @code |
|
@item enabled = 0|1 |
@cindex @code{enabled} (performance counters unit configuration) |
If 1 (true), the performance counters unit is enabled. If 0 (the default), it is disabled. |
|
@end table |
|
@node Peripheral Configuration |
@section Configuring Memory Mapped Peripherals |
|
/openrisc/trunk/or1ksim/doc/version.texi
1,4 → 1,4
@set UPDATED 5 June 2011 |
@set UPDATED 6 June 2011 |
@set UPDATED-MONTH June 2011 |
@set EDITION 2011-04-28 |
@set VERSION 2011-04-28 |
/openrisc/trunk/or1ksim/ChangeLog
1,3 → 1,41
2011-06-06 Julius Baxter <julius@opencores.org> |
|
* Makefile.in: Regenerated. |
* cpu/or32/insnset.c: (mfspr): Made move-from-SPR in user mode work when |
SR[SUMRA] bit set. |
* cpu/common/abstract.c: Added PCU header to includes. |
(eval_mem32): Added call to PCU event count function. |
Moved debug breakpoint check to after exception triggers. |
(eval_mem16): Ditto. |
(eval_mem8): Ditto. |
(set_mem32): Ditto. |
(set_mem16): Ditto. |
(set_mem8): Ditto. |
(eval_insn): Added call to PCU event count function. |
* configure.ac: Added newly added pcu/ path to appropriate places. |
* cache/dcache-model.c: Added PCU header to includes. |
(dc_simulate_read): Added call to PCU event count function. |
* cache/icache-model.c: Added PCU header to includes. |
(ic_simulate_read): Added call to PCU event count function. |
* pcu/Makefile.in: Generated and added. |
* pcu/pcu.c: Added. |
* pcu/Makefile.am: Added. |
* pcu/pcu.h: Added. |
* mmu/dmmu.c: Added PCU header to includes. |
(dmmu_translate): Added call to PCU event count function on miss. |
Cleared away unused code surrounded by "#if 0". |
* mmu/immu.c: Added PCU header to includes. |
(immu_translate): Added call to PCU event count function on miss. |
Cleared away unused code surrounded by "#if 0". |
* configure: Regenerated. |
* Makefile.am: <SUBDIRS>: Added pcu. |
<libor1ksys_la_LIBADD>: Added pcu/libpcu.la. |
* sim-config.c: Added PCU header to includes. |
(init_defconfig): Initialise pcu config struct. |
(reg_config_secs): Add call to pcu section setup function. |
* sim-config.h: <struct config>: Added pcu config struct. |
* doc/or1ksim.texi: Added information on pcu configuration. |
|
2011-06-04 Julius Baxter <julius@opencores.org> |
|
* cpu/or32/rec-i386.h: Removed. |
/openrisc/trunk/or1ksim/pcu/Makefile.in
0,0 → 1,509
# Makefile.in generated by automake 1.11 from Makefile.am. |
# @configure_input@ |
|
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, |
# Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
@SET_MAKE@ |
|
# Makefile -- Makefile for performance counter unit |
# |
# Copyright (C) 2011 Julius Baxter, julius@opencores.org |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
# |
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
# |
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http://www.gnu.org/licenses/>. |
|
VPATH = @srcdir@ |
pkgdatadir = $(datadir)/@PACKAGE@ |
pkgincludedir = $(includedir)/@PACKAGE@ |
pkglibdir = $(libdir)/@PACKAGE@ |
pkglibexecdir = $(libexecdir)/@PACKAGE@ |
am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd |
install_sh_DATA = $(install_sh) -c -m 644 |
install_sh_PROGRAM = $(install_sh) -c |
install_sh_SCRIPT = $(install_sh) -c |
INSTALL_HEADER = $(INSTALL_DATA) |
transform = $(program_transform_name) |
NORMAL_INSTALL = : |
PRE_INSTALL = : |
POST_INSTALL = : |
NORMAL_UNINSTALL = : |
PRE_UNINSTALL = : |
POST_UNINSTALL = : |
build_triplet = @build@ |
host_triplet = @host@ |
target_triplet = @target@ |
subdir = pcu |
DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in |
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 |
am__aclocal_m4_deps = $(top_srcdir)/m4/libtool.m4 \ |
$(top_srcdir)/m4/ltoptions.m4 $(top_srcdir)/m4/ltsugar.m4 \ |
$(top_srcdir)/m4/ltversion.m4 $(top_srcdir)/m4/lt~obsolete.m4 \ |
$(top_srcdir)/configure.ac |
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ |
$(ACLOCAL_M4) |
mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs |
CONFIG_HEADER = $(top_builddir)/config.h |
CONFIG_CLEAN_FILES = |
CONFIG_CLEAN_VPATH_FILES = |
LTLIBRARIES = $(noinst_LTLIBRARIES) |
libpcu_la_LIBADD = |
am_libpcu_la_OBJECTS = pcu.lo |
libpcu_la_OBJECTS = $(am_libpcu_la_OBJECTS) |
DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) |
depcomp = $(SHELL) $(top_srcdir)/depcomp |
am__depfiles_maybe = depfiles |
am__mv = mv -f |
COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ |
$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) |
LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ |
--mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ |
$(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) |
CCLD = $(CC) |
LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ |
--mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ |
$(LDFLAGS) -o $@ |
SOURCES = $(libpcu_la_SOURCES) |
DIST_SOURCES = $(libpcu_la_SOURCES) |
ETAGS = etags |
CTAGS = ctags |
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) |
ACLOCAL = @ACLOCAL@ |
AMTAR = @AMTAR@ |
AR = @AR@ |
ARFLAGS = @ARFLAGS@ |
AUTOCONF = @AUTOCONF@ |
AUTOHEADER = @AUTOHEADER@ |
AUTOMAKE = @AUTOMAKE@ |
AWK = @AWK@ |
BUILD_DIR = @BUILD_DIR@ |
CC = @CC@ |
CCAS = @CCAS@ |
CCASDEPMODE = @CCASDEPMODE@ |
CCASFLAGS = @CCASFLAGS@ |
CCDEPMODE = @CCDEPMODE@ |
CFLAGS = @CFLAGS@ |
CPP = @CPP@ |
CPPFLAGS = @CPPFLAGS@ |
CPU_ARCH = @CPU_ARCH@ |
CYGPATH_W = @CYGPATH_W@ |
DEBUGFLAGS = @DEBUGFLAGS@ |
DEFS = @DEFS@ |
DEJAGNU = @DEJAGNU@ |
DEPDIR = @DEPDIR@ |
DSYMUTIL = @DSYMUTIL@ |
DUMPBIN = @DUMPBIN@ |
ECHO_C = @ECHO_C@ |
ECHO_N = @ECHO_N@ |
ECHO_T = @ECHO_T@ |
EGREP = @EGREP@ |
EXEEXT = @EXEEXT@ |
FGREP = @FGREP@ |
GREP = @GREP@ |
INCLUDES = @INCLUDES@ |
INSTALL = @INSTALL@ |
INSTALL_DATA = @INSTALL_DATA@ |
INSTALL_PROGRAM = @INSTALL_PROGRAM@ |
INSTALL_SCRIPT = @INSTALL_SCRIPT@ |
INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ |
LD = @LD@ |
LDFLAGS = @LDFLAGS@ |
LIBOBJS = @LIBOBJS@ |
LIBS = @LIBS@ |
LIBTOOL = @LIBTOOL@ |
LIPO = @LIPO@ |
LN_S = @LN_S@ |
LOCAL_CFLAGS = @LOCAL_CFLAGS@ |
LOCAL_DEFS = @LOCAL_DEFS@ |
LOCAL_LDFLAGS = @LOCAL_LDFLAGS@ |
LTLIBOBJS = @LTLIBOBJS@ |
MAKEINFO = @MAKEINFO@ |
MKDIR_P = @MKDIR_P@ |
NM = @NM@ |
NMEDIT = @NMEDIT@ |
OBJDUMP = @OBJDUMP@ |
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# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
.NOEXPORT: |
/openrisc/trunk/or1ksim/pcu/pcu.c
0,0 → 1,114
/* pcu.c -- Simulation of OR1k performance counters |
|
Copyright (C) 2011 Julius Baxter, julius@opencores.org |
|
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
|
/* This program is commented throughout in a fashion suitable for processing |
with Doxygen. */ |
|
#include "config.h" |
#include "sim-config.h" |
#include "execute.h" |
|
#include "pcu.h" |
|
/*---------------------------------------------------------------------------*/ |
/*!Increment a PCCR depending on the event |
|
Check the event, see if any PCMRs are set to increment, and permissions and |
increment the corresponding PCCR. |
|
The performance counters unit relies on a call to pcu_count_event() |
being placed a the appropriate place elsewhere in the simulator code. |
At present only instruction fetch, LSU accesses, MMU and cache misses are |
logged. Counts for other things such as stalls for LSU or fetch can |
probably be done but haven't been, yet. |
The function expects to receive the bit of the PCMR to check against for |
incrementing. See the existing use of the function in the |
cpu/common/abstract.c file which is where LSU accesses and instruction |
fetches are logged. |
|
@param[in] event The event that has occurred (PCMR bit) */ |
/*---------------------------------------------------------------------------*/ |
void |
pcu_count_event(unsigned event) |
{ |
|
int i; |
|
// Look through each PCMR, check if this event should be logged |
for(i=0;i<8;i++) |
if ((event & cpu_state.sprs[SPR_PCMR(i)]) && |
// Count in SM, and SR[SM] set |
(((cpu_state.sprs[SPR_PCMR(i)] & SPR_PCMR_CISM) && |
(cpu_state.sprs[SPR_SR] & SPR_SR_SM)) || |
// Count in UM and SR[SM] cleared |
((cpu_state.sprs[SPR_PCMR(i)] & SPR_PCMR_CIUM) && |
!(cpu_state.sprs[SPR_SR] & SPR_SR_SM)))) |
{ |
cpu_state.sprs[SPR_PCCR(i)]++; |
} |
|
} |
|
|
/*---------------------------------------------------------------------------*/ |
/*!Enable or disable the performance counters unit |
|
Set the corresponding field in the UPR, set present bit in all PCMRs |
|
@param[in] val The value to use |
@param[in] dat The config data structure (not used here) */ |
/*---------------------------------------------------------------------------*/ |
static void |
pcu_enabled (union param_val val, void *dat) |
{ |
if (val.int_val) |
{ |
cpu_state.sprs[SPR_UPR] |= SPR_UPR_PCUP; |
cpu_state.sprs[SPR_PCMR(0)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(1)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(2)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(3)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(4)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(5)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(6)] = SPR_PCMR_CP; |
cpu_state.sprs[SPR_PCMR(7)] = SPR_PCMR_CP; |
} |
else |
{ |
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_PCUP; |
} |
|
|
|
config.pcu.enabled = val.int_val; |
|
} /* pcu_enabled() */ |
|
|
/*---------------------------------------------------------------------------*/ |
/*!Register the configuration functions for the performance counters unit */ |
/*---------------------------------------------------------------------------*/ |
void |
reg_pcu_sec () |
{ |
struct config_section *sec = reg_config_sec ("pcu", NULL, NULL); |
|
reg_config_param (sec, "enabled", PARAMT_INT, pcu_enabled); |
|
} /* reg_pcu_sec () */ |
/openrisc/trunk/or1ksim/pcu/Makefile.am
0,0 → 1,23
# Makefile -- Makefile for performance counter unit |
# |
# Copyright (C) 2011 Julius Baxter, julius@opencores.org |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
# |
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
# |
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http://www.gnu.org/licenses/>. |
|
|
noinst_LTLIBRARIES = libpcu.la |
libpcu_la_SOURCES = pcu.c \ |
pcu.h |
/openrisc/trunk/or1ksim/pcu/pcu.h
0,0 → 1,31
/* pcu.h -- Simulation of OR1k performance counters |
|
Copyright (C) 2011 Julius Baxter, julius@opencores.org |
|
This file is part of Or1ksim, the OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
|
/* This program is commented throughout in a fashion suitable for processing |
with Doxygen. */ |
|
|
#ifndef PCU__H |
#define PCU__H |
|
/* Function prototypes for external use */ |
extern void pcu_count_event(unsigned); |
extern void reg_pcu_sec (); |
|
#endif |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure
11183,7 → 11183,7
$as_echo "#define SIZEOF_LONG 4" >>confdefs.h |
|
|
ac_config_files="$ac_config_files Makefile acv-gpio/Makefile acv-uart/Makefile basic/Makefile cache/Makefile cbasic/Makefile cfg/Makefile dhry/Makefile dmatest/Makefile eth/Makefile except/Makefile except-test/Makefile exit/Makefile ext/Makefile fbtest/Makefile fp/Makefile testfloat/Makefile functest/Makefile flag/Makefile int-test/Makefile int-logger/Makefile inst-set-test/Makefile kbdtest/Makefile local-global/Makefile loop/Makefile mc-async/Makefile mc-dram/Makefile mc-ssram/Makefile mc-sync/Makefile mc-common/Makefile mem-test/Makefile mmu/Makefile mul/Makefile mycompress/Makefile support/Makefile tick/Makefile uos/Makefile upcalls/Makefile" |
ac_config_files="$ac_config_files Makefile acv-gpio/Makefile acv-uart/Makefile basic/Makefile cache/Makefile cbasic/Makefile cfg/Makefile dhry/Makefile dmatest/Makefile eth/Makefile except/Makefile except-test/Makefile exit/Makefile ext/Makefile fbtest/Makefile fp/Makefile testfloat/Makefile functest/Makefile flag/Makefile int-test/Makefile int-logger/Makefile inst-set-test/Makefile kbdtest/Makefile local-global/Makefile loop/Makefile mc-async/Makefile mc-dram/Makefile mc-ssram/Makefile mc-sync/Makefile mc-common/Makefile mem-test/Makefile mmu/Makefile mul/Makefile mycompress/Makefile support/Makefile tick/Makefile uos/Makefile upcalls/Makefile pcu/Makefile" |
|
|
cat >confcache <<\_ACEOF |
12196,6 → 12196,7
"tick/Makefile") CONFIG_FILES="$CONFIG_FILES tick/Makefile" ;; |
"uos/Makefile") CONFIG_FILES="$CONFIG_FILES uos/Makefile" ;; |
"upcalls/Makefile") CONFIG_FILES="$CONFIG_FILES upcalls/Makefile" ;; |
"pcu/Makefile") CONFIG_FILES="$CONFIG_FILES pcu/Makefile" ;; |
|
*) as_fn_error "invalid argument: \`$ac_config_target'" "$LINENO" 5;; |
esac |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.in
296,7 → 296,8
mycompress \ |
tick \ |
uos \ |
upcalls |
upcalls \ |
pcu |
|
all: config.h |
$(MAKE) $(AM_MAKEFLAGS) all-recursive |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/configure.ac
163,6 → 163,7
support/Makefile \ |
tick/Makefile \ |
uos/Makefile \ |
upcalls/Makefile]) |
upcalls/Makefile \ |
pcu/Makefile]) |
|
AC_OUTPUT |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/pcu/Makefile.in
0,0 → 1,503
# Makefile.in generated by automake 1.11 from Makefile.am. |
# @configure_input@ |
|
# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, |
# 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, |
# Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
@SET_MAKE@ |
|
# Makefile.am for or1ksim testsuite CPU test program: pcu |
|
# Contributor Julius Baxter <julius@opencores.org> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
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pcu_SOURCES = pcu.S |
pcu_LDFLAGS = -T$(srcdir)/../default.ld |
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|
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|
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|
# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
.NOEXPORT: |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/pcu/pcu.S
0,0 → 1,511
/* pcu.S -- Tests the performance counters unit |
|
Contributor Julius Baxter <julius@opencores.org> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http: www.gnu.org/licenses/>. */ |
|
/* Currently only checks instruction fetch, TLB miss and cache miss counters. */ |
|
#include "spr-defs.h" |
|
.section .except,"ax" |
|
.org 0x100 |
l.j start_test |
l.nop |
.org 0x200 |
l.jal unhandled_except |
l.nop |
.org 0x300 |
l.jal unhandled_except |
l.nop |
.org 0x400 |
l.jal unhandled_except |
l.nop |
.org 0x500 |
l.jal unhandled_except |
l.nop |
.org 0x600 |
l.jal unhandled_except |
l.nop |
.org 0x700 |
l.jal unhandled_except |
l.nop |
.org 0x800 |
l.jal unhandled_except |
l.nop |
|
/* DTLB miss - just disable DMMU and return */ |
/* clobber r13 */ |
.org 0x900 |
l.mfspr r13,r0,SPR_ESR_BASE |
l.xori r13,r13,SPR_SR_DME |
l.mtspr r0,r13,SPR_ESR_BASE |
l.rfe |
|
/* ITLB miss - just disable IMMU and return */ |
/* clobber r13 */ |
.org 0xa00 |
l.mfspr r13,r0,SPR_ESR_BASE |
l.xori r13,r13,SPR_SR_IME |
l.mtspr r0,r13,SPR_ESR_BASE |
l.rfe |
|
.org 0xb00 |
l.jal unhandled_except |
l.nop |
|
/* System call - switches user/supervisor mode */ |
/* Clobbers r13 */ |
.org 0xc00 |
l.mfspr r13,r0,SPR_ESR_BASE |
l.xori r13,r13,SPR_SR_SM /* Toggle SM bit */ |
l.mtspr r0,r13,SPR_ESR_BASE |
l.rfe |
|
.org 0xd00 |
l.jal unhandled_except |
l.nop |
.org 0xe00 |
l.jal unhandled_except |
l.nop |
.org 0xf00 |
l.jal unhandled_except |
l.nop |
|
|
.section .text |
start_test: |
/* Check PCU is present */ |
l.movhi r0,0 |
l.mfspr r2,r0,SPR_UPR |
l.andi r2,r2,SPR_UPR_PCUP |
l.sfnei r2,SPR_UPR_PCUP |
/* Fail if not present */ |
l.bf fail |
l.nop |
|
/* Assumption that we are already in SM */ |
|
/* Set SUMRA bit in SR */ |
l.movhi r2,hi(SPR_SR_SUMRA) |
l.mfspr r3,r0,SPR_SR |
l.or r3,r3,r2 |
l.mtspr r0,r3,SPR_SR |
|
/* Check instruction fetch counter - supervisor mode */ |
/* r1 - counter of which counter (0-7) we're using */ |
l.movhi r1,0 |
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_IF | SPR_PCMR_UMRA) |
/* report pcmr value */ |
l.or r3,r5,r5 |
l.nop NOP_REPORT |
pcr_if_sm: |
/* report which counter we're using */ |
l.or r3,r1,r1 |
l.nop NOP_REPORT |
/* clear (0) pccr */ |
l.mtspr r1,r0,SPR_PCCR(0) |
/* Load pcmr with appropriate mode */ |
l.mtspr r1,r5,SPR_PCMR(0) |
/* This next instruction should be counted */ |
l.nop |
/* Pull PCCR out and check it's != 0 */ |
l.mfspr r3,r1,SPR_PCCR(0) |
//l.nop NOP_REPORT |
l.sfnei r3,0 |
l.bnf fail |
|
/* Now change to usermode, ensure the counter doesn't increment */ |
l.sys 0 |
/* SM = 0 */ |
l.mfspr r6,r1,SPR_PCCR(0) |
l.nop |
l.nop |
l.nop |
l.mfspr r7,r1,SPR_PCCR(0) |
/* r6 and r7 should be equal */ |
l.sfne r6,r7 |
l.bf fail |
l.sys 0 |
/* SM = 1 */ |
|
/* End of loop */ |
l.sfeqi r1,7 /* Finished checking all 8 regs? */ |
l.bnf pcr_if_sm /* check next set */ |
l.addi r1,r1,1 /* increment set counter */ |
|
|
/* Check instruction fetch counter - user mode */ |
/* r1 - counter of which counter (0-7) we're using */ |
l.movhi r1,0 |
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CIUM | SPR_PCMR_IF | SPR_PCMR_UMRA) |
/* report pcmr value */ |
l.or r3,r5,r5 |
l.nop NOP_REPORT |
pcr_if_um: |
/* report which counter we're using */ |
l.or r3,r1,r1 |
l.nop NOP_REPORT |
/* clear (0) pccr */ |
l.mtspr r1,r0,SPR_PCCR(0) |
/* Load pcmr with appropriate mode */ |
l.mtspr r1,r5,SPR_PCMR(0) |
/* Switch to user mode */ |
l.sys 0 |
/* SM = 0 */ |
/* This next instruction should be counted */ |
l.nop |
l.mfspr r6,r1,SPR_PCCR(0) |
l.nop |
l.nop |
l.mfspr r7,r1,SPR_PCCR(0) |
/* r6 should be smaller than r7 */ |
l.sfgeu r6,r7 |
l.bf fail |
|
/* Now change to supervisor, ensure the counter doesn't increment */ |
l.sys 0 |
/* SM = 1 */ |
l.mfspr r6,r1,SPR_PCCR(0) |
l.nop |
l.nop |
l.nop |
l.mfspr r7,r1,SPR_PCCR(0) |
/* r6 and r7 should be equal */ |
l.sfeq r6,r7 |
l.bnf fail |
|
/* End of loop */ |
l.sfeqi r1,7 /* Finished checking all 8 regs? */ |
l.bnf pcr_if_um /* check next set */ |
l.addi r1,r1,1 /* increment set counter */ |
|
|
/* Check for MMU miss */ |
/* immu */ |
|
/* Clear MMU match registers, will cause a miss as soon as we turn on |
the MMU */ |
l.movhi r1,0 /* Set counter */ |
l.movhi r2,0 /* Way counter */ |
immu_clear_ways: |
l.slli r3,r2,8 /* way * 0x100 */ |
immu_clear_sets: |
l.add r4,r1,r3 /* set + way */ |
/* clear immu entry */ |
l.mtspr r4,r0,SPR_ITLBMR_BASE(0) |
l.mtspr r4,r0,SPR_ITLBTR_BASE(0) |
/* End of immu sets? */ |
l.sfnei r1,127 |
l.bf immu_clear_sets |
l.addi r1,r1,1 |
|
/* Reset set counter */ |
l.movhi r1,0 |
|
/* end of immu ways? */ |
l.sfnei r2,3 |
l.bf immu_clear_ways |
l.addi r2,r2,1 |
|
/* Check itlb miss counter */ |
/* r1 - counter of which counter (0-7) we're using */ |
l.movhi r1,0 |
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_ITLBM | SPR_PCMR_UMRA) |
/* report pcmr value */ |
l.or r3,r5,r5 |
l.nop NOP_REPORT |
pcr_itlbm: |
/* report which counter we're using */ |
l.or r3,r1,r1 |
l.nop NOP_REPORT |
/* clear (0) pccr */ |
l.mtspr r1,r0,SPR_PCCR(0) |
/* Load pcmr with appropriate mode */ |
l.mtspr r1,r5,SPR_PCMR(0) |
|
/* Switch on IMMU - cause tlb miss*/ |
l.mfspr r4,r0,SPR_SR |
l.ori r4,r4,SPR_SR_IME |
l.mtspr r0,r4,SPR_SR |
/* Miss should occur here */ |
|
/* Check PCCR incremented */ |
l.mfspr r6,r1,SPR_PCCR(0) |
l.sfeq r6,r0 |
l.bf fail |
|
/* End of loop */ |
l.sfeqi r1,7 /* Finished checking all 8 regs? */ |
l.bnf pcr_itlbm /* check next set */ |
l.addi r1,r1,1 /* increment set counter */ |
|
/* Check for MMU miss */ |
/* dmmu */ |
|
/* Clear MMU match registers, will cause a miss as soon as we turn on |
the MMU */ |
l.movhi r1,0 /* Set counter */ |
l.movhi r2,0 /* Way counter */ |
dmmu_clear_ways: |
l.slli r3,r2,8 /* way * 0x100 */ |
dmmu_clear_sets: |
l.add r4,r1,r3 /* set + way */ |
/* clear dmmu entry */ |
l.mtspr r4,r0,SPR_DTLBMR_BASE(0) |
l.mtspr r4,r0,SPR_DTLBTR_BASE(0) |
/* End of dmmu sets? */ |
l.sfnei r1,127 |
l.bf dmmu_clear_sets |
l.addi r1,r1,1 |
|
/* Reset set counter */ |
l.movhi r1,0 |
|
/* end of dmmu ways? */ |
l.sfnei r2,3 |
l.bf dmmu_clear_ways |
l.addi r2,r2,1 |
|
/* Check dtlb miss counter */ |
/* r1 - counter of which counter (0-7) we're using */ |
l.movhi r1,0 |
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_DTLBM | SPR_PCMR_UMRA) |
/* report pcmr value */ |
l.or r3,r5,r5 |
l.nop NOP_REPORT |
pcr_dtlbm: |
/* report which counter we're using */ |
l.or r3,r1,r1 |
l.nop NOP_REPORT |
/* clear (0) pccr */ |
l.mtspr r1,r0,SPR_PCCR(0) |
/* Load pcmr with appropriate mode */ |
l.mtspr r1,r5,SPR_PCMR(0) |
|
/* Switch on DMMU - cause tlb miss*/ |
l.mfspr r4,r0,SPR_SR |
l.ori r4,r4,SPR_SR_DME |
l.mtspr r0,r4,SPR_SR |
|
l.sw 0(r0),r6 |
/* Miss should occur here */ |
|
/* Check PCCR incremented */ |
l.mfspr r6,r1,SPR_PCCR(0) |
l.sfeq r6,r0 |
l.bf fail |
|
/* End of loop */ |
l.sfeqi r1,7 /* Finished checking all 8 regs? */ |
l.bnf pcr_dtlbm /* check next set */ |
l.addi r1,r1,1 /* increment set counter */ |
|
|
/* Check instruction cache miss counter */ |
icache_miss_test: |
/* Check if IC present and skip enabling otherwise */ |
l.mfspr r3,r0,SPR_UPR |
l.andi r4,r3,SPR_UPR_ICP |
l.sfeq r4,r0 |
l.bf dcache_miss_test |
l.nop |
|
/* r1 - counter of which counter (0-7) we're using */ |
l.movhi r1,0 |
|
|
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_ICM | SPR_PCMR_UMRA) |
/* report pcmr value */ |
l.or r3,r5,r5 |
l.nop NOP_REPORT |
|
pcr_icmiss: |
/* report which counter we're using */ |
l.or r3,r1,r1 |
l.nop NOP_REPORT |
/* clear (0) pccr */ |
l.mtspr r1,r0,SPR_PCCR(0) |
/* Load pcmr with appropriate mode */ |
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_ICM | SPR_PCMR_UMRA) |
l.mtspr r1,r5,SPR_PCMR(0) |
|
/* Disable IC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_ICE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
|
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r3,r0,SPR_ICCFGR |
l.andi r4,r3,SPR_ICCFGR_CBS |
l.srli r5,r4,7 |
l.ori r6,r0,16 |
l.sll r14,r6,r5 |
|
/* Establish number of cache sets |
r7 contains number of cache sets |
r5 contains log(# of cache sets) |
*/ |
l.andi r4,r3,SPR_ICCFGR_NCS |
l.srli r5,r4,3 |
l.ori r6,r0,1 |
l.sll r7,r6,r5 |
|
/* Invalidate IC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r5 |
|
.L7: |
l.mtspr r0,r6,SPR_ICBIR |
l.sfne r6,r5 |
l.bf .L7 |
l.add r6,r6,r14 |
|
/* Enable IC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_ICE |
l.mtspr r0,r6,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
|
/* Should have had at least 1 miss, check this */ |
l.mfspr r6,r1,SPR_PCCR(0) |
l.sfeq r6,r0 |
l.bf fail |
l.nop |
|
/* End of loop */ |
l.sfeqi r1,7 /* Finished checking all 8 regs? */ |
l.bnf pcr_icmiss /* check next set */ |
l.addi r1,r1,1 /* increment set counter */ |
|
|
|
dcache_miss_test: |
|
/* Check if DC present and skip enabling otherwise */ |
l.mfspr r3,r0,SPR_UPR |
l.andi r4,r3,SPR_UPR_DCP |
l.sfeq r4,r0 |
l.bf dcache_miss_test_done |
l.nop |
|
/* r1 - counter of which counter (0-7) we're using */ |
l.movhi r1,0 |
|
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_DCM | SPR_PCMR_UMRA) |
/* report pcmr value */ |
l.or r3,r5,r5 |
l.nop NOP_REPORT |
|
pcr_dcmiss: |
/* report which counter we're using */ |
l.or r3,r1,r1 |
l.nop NOP_REPORT |
/* clear (0) pccr */ |
l.mtspr r1,r0,SPR_PCCR(0) |
/* Load pcmr with appropriate mode */ |
/* use r5 to hold pcmr value */ |
l.ori r5,r0,(SPR_PCMR_CISM | SPR_PCMR_DCM | SPR_PCMR_UMRA) |
l.mtspr r1,r5,SPR_PCMR(0) |
|
/* Disable DC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r3,r0,SPR_DCCFGR |
l.andi r4,r3,SPR_DCCFGR_CBS |
l.srli r5,r4,7 |
l.ori r6,r0,16 |
l.sll r14,r6,r5 |
/* Establish number of cache sets |
r7 contains number of cache sets |
r5 contains log(# of cache sets) |
*/ |
l.andi r4,r3,SPR_DCCFGR_NCS |
l.srli r5,r4,3 |
l.ori r6,r0,1 |
l.sll r7,r6,r5 |
/* Invalidate DC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r5 |
.L9: |
l.mtspr r0,r6,SPR_DCBIR |
l.sfne r6,r5 |
l.bf .L9 |
l.add r6,r6,r14 |
/* Enable DC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_DCE |
l.mtspr r0,r6,SPR_SR |
|
/* Should trigger a dcache miss */ |
l.sw 0(r0),r6 |
/* Should trigger another dcache miss */ |
l.lwz r6,0x1000(r0) |
|
/* Should have had 2 misses */ |
l.mfspr r6,r1,SPR_PCCR(0) |
l.sfnei r6,2 |
l.bf fail |
l.nop |
|
/* End of loop */ |
l.sfeqi r1,7 /* Finished checking all 8 regs? */ |
l.bnf pcr_dcmiss /* check next set */ |
l.addi r1,r1,1 /* increment set counter */ |
|
dcache_miss_test_done: |
|
finish_ok: |
l.movhi r3,0xdead |
l.ori r3,r3,0xdead |
l.nop NOP_REPORT |
l.ori r3,r0,0 |
l.nop NOP_EXIT |
|
fail: |
l.ori r3,r0,0x1234 |
l.nop NOP_EXIT |
|
unhandled_except: |
l.addi r3,r9,-8 |
l.nop NOP_REPORT |
l.nop NOP_EXIT |
|
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/pcu/Makefile.am
0,0 → 1,30
# Makefile.am for or1ksim testsuite CPU test program: pcu |
|
# Contributor Julius Baxter <julius@opencores.org> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# A test program for the performance counters unit |
check_PROGRAMS = pcu |
|
pcu_SOURCES = pcu.S |
|
pcu_LDFLAGS = -T$(srcdir)/../default.ld |
/openrisc/trunk/or1ksim/testsuite/test-code-or1k/Makefile.am
73,4 → 73,6
mycompress \ |
tick \ |
uos \ |
upcalls |
upcalls \ |
pcu |
|
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.in
245,7 → 245,8
mul.exp \ |
mycompress.exp \ |
testfloat.exp \ |
tick.exp |
tick.exp \ |
pcu.exp |
|
all: all-am |
|
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/pcu.cfg
0,0 → 1,128
/* pcu.cfg -- Or1ksim configuration script file when using perf. counters unit |
|
Copyright (C) 2001, Marko Mlinar <markom@opencores.org> |
Copyright (C) 2010 Embecosm Limited |
|
Contributor Marko Mlinar <markom@opencores.org> |
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
Contributor Julius Baxter <julius@opencores.org> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http: www.gnu.org/licenses/>. */ |
|
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
|
name = "RAM" |
ce = 1 |
mc = 0 |
baseaddr = 0x00000000 |
size = 0x00200000 |
delayr = 1 |
delayw = 1 |
end |
|
section immu |
enabled = 1 |
nsets = 64 |
nways = 1 |
ustates = 2 |
pagesize = 8192 |
end |
|
section dmmu |
enabled = 1 |
nsets = 64 |
nways = 1 |
ustates = 2 |
pagesize = 8192 |
end |
|
section ic |
enabled = 1 |
nsets = 256 |
nways = 1 |
ustates = 2 |
blocksize = 16 |
end |
|
section dc |
enabled = 1 |
nsets = 256 |
nways = 1 |
ustates = 2 |
blocksize = 16 |
end |
|
section cpu |
ver = 0x12 |
rev = 0x0001 |
/* upr = */ |
superscalar = 0 |
hazards = 0 |
dependstats = 0 |
hardfloat = 1 |
end |
|
section pcu |
enabled = 1 |
end |
|
section debug |
/* enabled = 1 |
rsp_enabled = 1 |
rsp_port = 51000 */ |
end |
|
section sim |
debug = 0 |
profile = 0 |
prof_fn = "sim.profile" |
|
exe_log = 0 |
exe_log_type = software |
exe_log_fn = "executed.log" |
end |
|
section dma |
baseaddr = 0xB8000000 |
irq = 4 |
end |
|
section ethernet |
enabled = 0 |
baseaddr = 0x92000000 |
irq = 4 |
rtx_type = "file" |
end |
|
section VAPI |
enabled = 0 |
server_port = 9998 |
end |
|
section fb |
enabled = 1 |
baseaddr = 0x97000000 |
refresh_rate = 10000 |
filename = "primary" |
end |
|
section kbd |
enabled = 0 |
end |
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/pcu.exp
0,0 → 1,83
# pcu.exp - performance counters unit |
|
# Contributor Julius Baxter <julius@opencores.org> |
|
# This file is part of OpenRISC 1000 Architectural Simulator. |
|
# This program is free software; you can redistribute it and/or modify it |
# under the terms of the GNU General Public License as published by the Free |
# Software Foundation; either version 3 of the License, or (at your option) |
# any later version. |
|
# This program is distributed in the hope that it will be useful, but WITHOUT |
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
# more details. |
|
# You should have received a copy of the GNU General Public License along |
# with this program. If not, see <http:#www.gnu.org/licenses/>. */ |
|
# ----------------------------------------------------------------------------- |
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
|
# Run the l.ext test |
run_or1ksim "pcu" \ |
[list "report(0x00000046);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x0000004a);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00002006);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00001006);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00000106);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"report(0x00000086);" \ |
"report(0x00000000);" \ |
"report(0x00000001);" \ |
"report(0x00000002);" \ |
"report(0x00000003);" \ |
"report(0x00000004);" \ |
"report(0x00000005);" \ |
"report(0x00000006);" \ |
"report(0x00000007);" \ |
"!report(0xdeaddead);" \ |
"!exit(0)"] \ |
"pcu.cfg" "pcu/pcu" |
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/mmu.exp
23,7 → 23,11
# This code is commented throughout for use with Doxygen. |
# ----------------------------------------------------------------------------- |
|
# Allow up to 30 seconds to run this |
set old_timeout $timeout |
set timeout 30 |
|
|
# Run the MMU test |
run_or1ksim "mmu" \ |
[list "DTLB translation tests OK" \ |
/openrisc/trunk/or1ksim/testsuite/or1ksim.tests/Makefile.am
61,4 → 61,5
mul.exp \ |
mycompress.exp \ |
testfloat.exp \ |
tick.exp |
tick.exp \ |
pcu.exp |
/openrisc/trunk/or1ksim/testsuite/ChangeLog
1,3 → 1,16
2011-06-06 Julius Baxter <julius@opencores.rg> |
* test-code-or1k/Makefile.am: Added pcu to SUBDIRS |
* test-code-or1k/Makefile.in: Regenerated |
* test-code-or1k/configure.ac: Added pcu/Makefile |
* test-code-or1k/pcu/pcu.S: Added. |
* test-code-or1k/pcu/Makefile.am: Added. |
* or1ksim.tests/Makefile.am: Added pcu.exp to EXTRA_DIST |
* or1ksim.tests/pcu.cfg: Added, has section enabling PCU |
* or1ksim.tests/pcu.exp: Added. |
* or1ksim.tests/mmu.exp: Set timeout to 30 seconds. |
* or1ksim.tests/Makefile.in: Regenerated. |
* README: Updated with details of PCU test. |
|
2011-01-04 Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
* README: Updated with details of new tests. |
/openrisc/trunk/or1ksim/testsuite/README
86,6 → 86,7
mycompress: 1 test using a compression program. |
testfloat 40 tests of detailed floating point behavior |
tick: 19 tests of the OR1K tick timer. |
pcu: 27 tests of the OR1K performance counters unit. |
|
Tests of the libsim library: |
|
133,4 → 134,5
|
|
Updated by Jeremy Bennett (jeremy@jeremybennett.com) |
13 June 2010 |
Updated by Julius Baxter (julius@opencores.org) |
6 June 2011 |
/openrisc/trunk/or1ksim/mmu/dmmu.c
44,8 → 44,8
#include "sprs.h" |
#include "misc.h" |
#include "sim-cmd.h" |
#include "pcu.h" |
|
|
struct dmmu *dmmu_state; |
|
/* Data MMU */ |
140,37 → 140,16
|
/* No, we didn't. */ |
dmmu_stats.loads_tlbmiss++; |
#if 0 |
for (i = 0; i < dmmu->nways; i++) |
if (((cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] & SPR_DTLBMR_LRU) >> 6) < |
minlru) |
minway = i; |
|
cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] &= ~SPR_DTLBMR_VPN; |
cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= vpn << 12; |
for (i = 0; i < dmmu->nways; i++) |
{ |
uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE (i) + set]; |
if (lru & SPR_DTLBMR_LRU) |
{ |
lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40); |
cpu_state.sprs[SPR_DTLBMR_BASE (i) + set] = lru; |
} |
} |
cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] &= ~SPR_DTLBMR_LRU; |
cpu_state.sprs[SPR_DTLBMR_BASE (way) + set] |= (dmmu->nsets - 1) << 6; |
|
/* 1 to 1 mapping */ |
cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] &= ~SPR_DTLBTR_PPN; |
cpu_state.sprs[SPR_DTLBTR_BASE (minway) + set] |= vpn << 12; |
|
cpu_state.sprs[SPR_DTLBMR_BASE (minway) + set] |= SPR_DTLBMR_V; |
#endif |
runtime.sim.mem_cycles += dmmu->missdelay; |
/* if tlb refill implemented in HW */ |
/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * dmmu->pagesize + (virtaddr % dmmu->pagesize); */ |
|
except_handle (EXCEPT_DTLBMISS, virtaddr); |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_DTLBM); |
|
return 0; |
} |
|
/openrisc/trunk/or1ksim/mmu/immu.c
39,6 → 39,7
#include "spr-dump.h" |
#include "misc.h" |
#include "sim-cmd.h" |
#include "pcu.h" |
|
|
struct immu *immu_state; |
132,38 → 133,16
|
/* No, we didn't. */ |
immu_stats.fetch_tlbmiss++; |
#if 0 |
for (i = 0; i < immu->nways; i++) |
if (((cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] & SPR_ITLBMR_LRU) >> 6) < |
minlru) |
minway = i; |
|
cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] &= ~SPR_ITLBMR_VPN; |
cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] |= vpn << 12; |
for (i = 0; i < immu->nways; i++) |
{ |
uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE (i) + set]; |
if (lru & SPR_ITLBMR_LRU) |
{ |
lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40); |
cpu_state.sprs[SPR_ITLBMR_BASE (i) + set] = lru; |
} |
} |
cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] &= ~SPR_ITLBMR_LRU; |
cpu_state.sprs[SPR_ITLBMR_BASE (way) + set] |= (immu->nsets - 1) << 6; |
|
/* 1 to 1 mapping */ |
cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] &= ~SPR_ITLBTR_PPN; |
cpu_state.sprs[SPR_ITLBTR_BASE (minway) + set] |= vpn << 12; |
|
cpu_state.sprs[SPR_ITLBMR_BASE (minway) + set] |= SPR_ITLBMR_V; |
#endif |
|
/* if tlb refill implemented in HW */ |
/* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * immu->pagesize + (virtaddr % immu->pagesize); */ |
runtime.sim.mem_cycles += immu->missdelay; |
|
except_handle (EXCEPT_ITLBMISS, virtaddr); |
|
if (config.pcu.enabled) |
pcu_count_event(SPR_PCMR_ITLBM); |
|
return 0; |
} |
|
/openrisc/trunk/or1ksim/configure
1,5 → 1,5
#! /bin/sh |
# From configure.ac Id: configure.ac 538 2011-05-09 14:42:56Z julius using automake version AC_ACVERSION. |
# From configure.ac Id: configure.ac 552 2011-06-05 10:49:58Z julius using automake version AC_ACVERSION. |
# Guess values for system-dependent variables and create Makefiles. |
# Generated by GNU Autoconf 2.64 for or1ksim 2011-04-28. |
# |
13123,10 → 13123,10
-I\${top_srcdir}/peripheral/channels -I\${top_srcdir}/pm -I\${top_srcdir}/pic \ |
-I\${top_srcdir}/debug -I\${top_srcdir}/vapi -I\${top_srcdir}/support \ |
-I\${top_srcdir}/cuc -I\${top_srcdir}/port -I\${top_srcdir}/argtable2 \ |
-I\${top_srcdir}/softfloat" |
-I\${top_srcdir}/softfloat -I\${top_srcdir}/pcu" |
|
|
ac_config_files="$ac_config_files Makefile argtable2/Makefile bpb/Makefile cache/Makefile cpu/Makefile cpu/common/Makefile cpu/or1k/Makefile cuc/Makefile softfloat/Makefile debug/Makefile doc/Makefile mmu/Makefile peripheral/Makefile peripheral/channels/Makefile pm/Makefile pic/Makefile port/Makefile support/Makefile testsuite/Makefile testsuite/config/Makefile testsuite/lib/Makefile testsuite/libsim.tests/Makefile testsuite/or1ksim.tests/Makefile testsuite/test-code/Makefile testsuite/test-code/lib-iftest/Makefile testsuite/test-code/lib-inttest/Makefile testsuite/test-code/lib-jtag/Makefile testsuite/test-code/lib-upcalls/Makefile tick/Makefile vapi/Makefile" |
ac_config_files="$ac_config_files Makefile argtable2/Makefile bpb/Makefile cache/Makefile cpu/Makefile cpu/common/Makefile cpu/or1k/Makefile cuc/Makefile softfloat/Makefile debug/Makefile doc/Makefile mmu/Makefile peripheral/Makefile peripheral/channels/Makefile pm/Makefile pic/Makefile pcu/Makefile port/Makefile support/Makefile testsuite/Makefile testsuite/config/Makefile testsuite/lib/Makefile testsuite/libsim.tests/Makefile testsuite/or1ksim.tests/Makefile testsuite/test-code/Makefile testsuite/test-code/lib-iftest/Makefile testsuite/test-code/lib-inttest/Makefile testsuite/test-code/lib-jtag/Makefile testsuite/test-code/lib-upcalls/Makefile tick/Makefile vapi/Makefile" |
|
|
# yuck. I don't know why I cannot just substitute $CPU_ARCH in the above |
14139,6 → 14139,7
"peripheral/channels/Makefile") CONFIG_FILES="$CONFIG_FILES peripheral/channels/Makefile" ;; |
"pm/Makefile") CONFIG_FILES="$CONFIG_FILES pm/Makefile" ;; |
"pic/Makefile") CONFIG_FILES="$CONFIG_FILES pic/Makefile" ;; |
"pcu/Makefile") CONFIG_FILES="$CONFIG_FILES pcu/Makefile" ;; |
"port/Makefile") CONFIG_FILES="$CONFIG_FILES port/Makefile" ;; |
"support/Makefile") CONFIG_FILES="$CONFIG_FILES support/Makefile" ;; |
"testsuite/Makefile") CONFIG_FILES="$CONFIG_FILES testsuite/Makefile" ;; |
/openrisc/trunk/or1ksim/autom4te.cache/output.1
13123,10 → 13123,10
-I\${top_srcdir}/peripheral/channels -I\${top_srcdir}/pm -I\${top_srcdir}/pic \ |
-I\${top_srcdir}/debug -I\${top_srcdir}/vapi -I\${top_srcdir}/support \ |
-I\${top_srcdir}/cuc -I\${top_srcdir}/port -I\${top_srcdir}/argtable2 \ |
-I\${top_srcdir}/softfloat" |
-I\${top_srcdir}/softfloat -I\${top_srcdir}/pcu" |
|
|
ac_config_files="$ac_config_files Makefile argtable2/Makefile bpb/Makefile cache/Makefile cpu/Makefile cpu/common/Makefile cpu/or1k/Makefile cuc/Makefile softfloat/Makefile debug/Makefile doc/Makefile mmu/Makefile peripheral/Makefile peripheral/channels/Makefile pm/Makefile pic/Makefile port/Makefile support/Makefile testsuite/Makefile testsuite/config/Makefile testsuite/lib/Makefile testsuite/libsim.tests/Makefile testsuite/or1ksim.tests/Makefile testsuite/test-code/Makefile testsuite/test-code/lib-iftest/Makefile testsuite/test-code/lib-inttest/Makefile testsuite/test-code/lib-jtag/Makefile testsuite/test-code/lib-upcalls/Makefile tick/Makefile vapi/Makefile" |
ac_config_files="$ac_config_files Makefile argtable2/Makefile bpb/Makefile cache/Makefile cpu/Makefile cpu/common/Makefile cpu/or1k/Makefile cuc/Makefile softfloat/Makefile debug/Makefile doc/Makefile mmu/Makefile peripheral/Makefile peripheral/channels/Makefile pm/Makefile pic/Makefile pcu/Makefile port/Makefile support/Makefile testsuite/Makefile testsuite/config/Makefile testsuite/lib/Makefile testsuite/libsim.tests/Makefile testsuite/or1ksim.tests/Makefile testsuite/test-code/Makefile testsuite/test-code/lib-iftest/Makefile testsuite/test-code/lib-inttest/Makefile testsuite/test-code/lib-jtag/Makefile testsuite/test-code/lib-upcalls/Makefile tick/Makefile vapi/Makefile" |
|
|
# yuck. I don't know why I cannot just substitute $CPU_ARCH in the above |
14139,6 → 14139,7
"peripheral/channels/Makefile") CONFIG_FILES="$CONFIG_FILES peripheral/channels/Makefile" ;; |
"pm/Makefile") CONFIG_FILES="$CONFIG_FILES pm/Makefile" ;; |
"pic/Makefile") CONFIG_FILES="$CONFIG_FILES pic/Makefile" ;; |
"pcu/Makefile") CONFIG_FILES="$CONFIG_FILES pcu/Makefile" ;; |
"port/Makefile") CONFIG_FILES="$CONFIG_FILES port/Makefile" ;; |
"support/Makefile") CONFIG_FILES="$CONFIG_FILES support/Makefile" ;; |
"testsuite/Makefile") CONFIG_FILES="$CONFIG_FILES testsuite/Makefile" ;; |
/openrisc/trunk/or1ksim/autom4te.cache/traces.0
955,6 → 955,7
peripheral/channels/Makefile \ |
pm/Makefile \ |
pic/Makefile \ |
pcu/Makefile \ |
port/Makefile \ |
support/Makefile \ |
testsuite/Makefile \ |
969,31 → 970,31
testsuite/test-code/lib-upcalls/Makefile \ |
tick/Makefile \ |
vapi/Makefile]) |
m4trace:configure.ac:374: -1- AC_CONFIG_FILES([cpu/or32/Makefile]) |
m4trace:configure.ac:398: -1- AC_SUBST([LIB@&t@OBJS], [$ac_libobjs]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([LIB@&t@OBJS]) |
m4trace:configure.ac:398: -1- m4_pattern_allow([^LIB@&t@OBJS$]) |
m4trace:configure.ac:398: -1- AC_SUBST([LTLIBOBJS], [$ac_ltlibobjs]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([LTLIBOBJS]) |
m4trace:configure.ac:398: -1- m4_pattern_allow([^LTLIBOBJS$]) |
m4trace:configure.ac:398: -1- AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"]) |
m4trace:configure.ac:398: -1- AC_SUBST([am__EXEEXT_TRUE]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([am__EXEEXT_TRUE]) |
m4trace:configure.ac:398: -1- m4_pattern_allow([^am__EXEEXT_TRUE$]) |
m4trace:configure.ac:398: -1- AC_SUBST([am__EXEEXT_FALSE]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([am__EXEEXT_FALSE]) |
m4trace:configure.ac:398: -1- m4_pattern_allow([^am__EXEEXT_FALSE$]) |
m4trace:configure.ac:398: -1- _AM_SUBST_NOTMAKE([am__EXEEXT_TRUE]) |
m4trace:configure.ac:398: -1- _AM_SUBST_NOTMAKE([am__EXEEXT_FALSE]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([top_builddir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([top_build_prefix]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([srcdir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([abs_srcdir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([top_srcdir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([abs_top_srcdir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([builddir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([abs_builddir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([abs_top_builddir]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([INSTALL]) |
m4trace:configure.ac:398: -1- AC_SUBST_TRACE([MKDIR_P]) |
m4trace:configure.ac:398: -1- AC_REQUIRE_AUX_FILE([ltmain.sh]) |
m4trace:configure.ac:375: -1- AC_CONFIG_FILES([cpu/or32/Makefile]) |
m4trace:configure.ac:399: -1- AC_SUBST([LIB@&t@OBJS], [$ac_libobjs]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([LIB@&t@OBJS]) |
m4trace:configure.ac:399: -1- m4_pattern_allow([^LIB@&t@OBJS$]) |
m4trace:configure.ac:399: -1- AC_SUBST([LTLIBOBJS], [$ac_ltlibobjs]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([LTLIBOBJS]) |
m4trace:configure.ac:399: -1- m4_pattern_allow([^LTLIBOBJS$]) |
m4trace:configure.ac:399: -1- AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"]) |
m4trace:configure.ac:399: -1- AC_SUBST([am__EXEEXT_TRUE]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([am__EXEEXT_TRUE]) |
m4trace:configure.ac:399: -1- m4_pattern_allow([^am__EXEEXT_TRUE$]) |
m4trace:configure.ac:399: -1- AC_SUBST([am__EXEEXT_FALSE]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([am__EXEEXT_FALSE]) |
m4trace:configure.ac:399: -1- m4_pattern_allow([^am__EXEEXT_FALSE$]) |
m4trace:configure.ac:399: -1- _AM_SUBST_NOTMAKE([am__EXEEXT_TRUE]) |
m4trace:configure.ac:399: -1- _AM_SUBST_NOTMAKE([am__EXEEXT_FALSE]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([top_builddir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([top_build_prefix]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([srcdir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([abs_srcdir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([top_srcdir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([abs_top_srcdir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([builddir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([abs_builddir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([abs_top_builddir]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([INSTALL]) |
m4trace:configure.ac:399: -1- AC_SUBST_TRACE([MKDIR_P]) |
m4trace:configure.ac:399: -1- AC_REQUIRE_AUX_FILE([ltmain.sh]) |
/openrisc/trunk/or1ksim/autom4te.cache/output.0
1,5 → 1,5
@%:@! /bin/sh |
@%:@ From configure.ac Id: configure.ac 538 2011-05-09 14:42:56Z julius using automake version AC_ACVERSION. |
@%:@ From configure.ac Id: configure.ac 552 2011-06-05 10:49:58Z julius using automake version AC_ACVERSION. |
@%:@ Guess values for system-dependent variables and create Makefiles. |
@%:@ Generated by GNU Autoconf 2.64 for or1ksim 2011-04-28. |
@%:@ |
13123,10 → 13123,10
-I\${top_srcdir}/peripheral/channels -I\${top_srcdir}/pm -I\${top_srcdir}/pic \ |
-I\${top_srcdir}/debug -I\${top_srcdir}/vapi -I\${top_srcdir}/support \ |
-I\${top_srcdir}/cuc -I\${top_srcdir}/port -I\${top_srcdir}/argtable2 \ |
-I\${top_srcdir}/softfloat" |
-I\${top_srcdir}/softfloat -I\${top_srcdir}/pcu" |
|
|
ac_config_files="$ac_config_files Makefile argtable2/Makefile bpb/Makefile cache/Makefile cpu/Makefile cpu/common/Makefile cpu/or1k/Makefile cuc/Makefile softfloat/Makefile debug/Makefile doc/Makefile mmu/Makefile peripheral/Makefile peripheral/channels/Makefile pm/Makefile pic/Makefile port/Makefile support/Makefile testsuite/Makefile testsuite/config/Makefile testsuite/lib/Makefile testsuite/libsim.tests/Makefile testsuite/or1ksim.tests/Makefile testsuite/test-code/Makefile testsuite/test-code/lib-iftest/Makefile testsuite/test-code/lib-inttest/Makefile testsuite/test-code/lib-jtag/Makefile testsuite/test-code/lib-upcalls/Makefile tick/Makefile vapi/Makefile" |
ac_config_files="$ac_config_files Makefile argtable2/Makefile bpb/Makefile cache/Makefile cpu/Makefile cpu/common/Makefile cpu/or1k/Makefile cuc/Makefile softfloat/Makefile debug/Makefile doc/Makefile mmu/Makefile peripheral/Makefile peripheral/channels/Makefile pm/Makefile pic/Makefile pcu/Makefile port/Makefile support/Makefile testsuite/Makefile testsuite/config/Makefile testsuite/lib/Makefile testsuite/libsim.tests/Makefile testsuite/or1ksim.tests/Makefile testsuite/test-code/Makefile testsuite/test-code/lib-iftest/Makefile testsuite/test-code/lib-inttest/Makefile testsuite/test-code/lib-jtag/Makefile testsuite/test-code/lib-upcalls/Makefile tick/Makefile vapi/Makefile" |
|
|
# yuck. I don't know why I cannot just substitute $CPU_ARCH in the above |
14139,6 → 14139,7
"peripheral/channels/Makefile") CONFIG_FILES="$CONFIG_FILES peripheral/channels/Makefile" ;; |
"pm/Makefile") CONFIG_FILES="$CONFIG_FILES pm/Makefile" ;; |
"pic/Makefile") CONFIG_FILES="$CONFIG_FILES pic/Makefile" ;; |
"pcu/Makefile") CONFIG_FILES="$CONFIG_FILES pcu/Makefile" ;; |
"port/Makefile") CONFIG_FILES="$CONFIG_FILES port/Makefile" ;; |
"support/Makefile") CONFIG_FILES="$CONFIG_FILES support/Makefile" ;; |
"testsuite/Makefile") CONFIG_FILES="$CONFIG_FILES testsuite/Makefile" ;; |
/openrisc/trunk/or1ksim/Makefile.am
40,6 → 40,7
pm \ |
pic \ |
debug \ |
pcu \ |
vapi \ |
cuc \ |
port \ |
82,6 → 83,7
pm/libpm.la \ |
pic/libpic.la \ |
debug/libdebug.la \ |
pcu/libpcu.la \ |
vapi/libvapi.la \ |
cuc/libcuc.la \ |
softfloat/libsoftfloat.la \ |
/openrisc/trunk/or1ksim/sim-config.c
46,6 → 46,7
#include "icache-model.h" |
#include "pic.h" |
#include "pm.h" |
#include "pcu.h" |
#include "branch-predict.h" |
#include "debug-unit.h" |
#include "mc.h" |
375,6 → 376,9
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_PICP; |
} |
|
/* Performance Counters Unit */ |
config.pcu.enabled = 0; |
|
/* Branch Prediction */ |
config.bpb.enabled = 0; |
config.bpb.btic = 0; |
1605,6 → 1609,7
reg_gpio_sec (); |
reg_bpb_sec (); |
reg_pm_sec (); |
reg_pcu_sec (); |
reg_vga_sec (); |
reg_fb_sec (); |
reg_kbd_sec (); |