URL
https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
Subversion Repositories or1k_old
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 555 to Rev 556
- ↔ Reverse comparison
Rev 555 → Rev 556
/trunk/or1ksim/sim-config.h
158,6 → 158,7
struct { |
unsigned long upr; /* Unit present register */ |
unsigned long ver, rev; /* Version register */ |
int sr; /* Supervision register */ |
int superscalar; /* superscalara analysis */ |
int hazards; /* dependency hazards analysis */ |
int dependstats; /* dependency statistics */ |
/trunk/or1ksim/sim.cfg
384,6 → 384,9
|
upr = <value> |
changes the upr register |
|
sr = <value> |
sets the initial Supervision Register value |
|
superscalar = 0/1 |
whether CPU is scalar or superscalar |
405,6 → 408,7
ver = 0x1200 |
rev = 0x0001 |
/* upr = */ |
sr = 0x00008003 |
superscalar = 0 |
hazards = 0 |
dependstats = 0 |
/trunk/or1ksim/cpu/or32/execute.c
386,7 → 386,8
mtspr(SPR_UPR, config.cpu.upr); |
setsprbits(SPR_VR, SPR_VR_VER, config.cpu.ver); |
setsprbits(SPR_VR, SPR_VR_REV, config.cpu.rev); |
|
mtspr(SPR_SR, config.cpu.sr); |
|
pcnext = 0x0; /* MM1409: All programs should start at reset vector entry! */ |
printf ("Starting at 0x%08x\n", pcnext); |
pc = pcnext; |
/trunk/or1ksim/cpu/common/stats.c
175,7 → 175,7
printf("BTIC: hit %d(%d%%), miss %d\n", mstats.btic.hit, (mstats.btic.hit * 100) / SD(mstats.btic.hit + mstats.btic.miss), mstats.btic.miss); |
} else |
printf("BTIC simulation disabled. Enabled it to see BTIC analysis\n"); |
|
|
if (testsprbits(SPR_UPR, SPR_UPR_ICP)) { |
printf("IC read: hit %d(%d%%), miss %d\n", ic_stats.readhit, (ic_stats.readhit * 100) / SD(ic_stats.readhit + ic_stats.readmiss), ic_stats.readmiss); |
} else |
/trunk/or1ksim/cpu/or1k/except.c
92,9 → 92,9
} |
#endif |
|
pc_saved = pc & ~0x3; |
pc_saved = pc & ~0x3; |
if (except == EXCEPT_ILLEGAL) |
mtspr(SPR_EPCR_BASE, pending.saved); |
mtspr(SPR_EPCR_BASE, pending.saved); |
else if (except == EXCEPT_ALIGN) |
mtspr(SPR_EPCR_BASE, pending.saved); |
else if (except == EXCEPT_DTLBMISS) |
123,9 → 123,9
mtspr(SPR_SR, mfspr(SPR_SR) & ~SPR_SR_EIR); /* Disable interrupts. */ |
|
clear_pending_exception (); |
|
pc = (unsigned long)except; |
|
pc = (unsigned long)except + (testsprbits (SPR_SR, SPR_SR_EP) ? 0xf0000000 : 0x00000000); |
|
/* This has been removed. All exceptions (not just SYSCALL) suffer |
from the same problem. The solution is to continue just like |
the pipeline would, and issue the exception on the next |
147,5 → 147,5
pc_phy = pc; /* An exception always turns off the MMU, so |
pc is always pc_phy */ |
|
#endif |
#endif /* !ONLY_VIRUAL_MACHINE */ |
} |
/trunk/or1ksim/sim-config.c
106,6 → 106,7
config.cpu.upr = SPR_UPR_UP | SPR_UPR_DCP | SPR_UPR_ICP | SPR_UPR_DMP |
| SPR_UPR_IMP | SPR_UPR_OB32P | SPR_UPR_DUP | SPR_UPR_PICP |
| SPR_UPR_PMP | SPR_UPR_TTP; |
config.cpu.sr = 0x00008003; |
|
/* Debug */ |
config.debug.enabled = 0; |