URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 557 to Rev 558
- ↔ Reverse comparison
Rev 557 → Rev 558
/openrisc/trunk/orpsocv2/scripts/make/Makefile-board-benchsrc.inc
37,7 → 37,7
|
ifeq ($(VPI), 1) |
# Manually add the VPI bench verilog path |
COMMON_BENCH_VERILOG_SUBDIRS += $(VPI_SRC_VERILOG_DIR) |
COMMON_BENCH_VERILOG_SUBDIRS += vpi/verilog |
endif |
|
print-board-bench-subdirs: |
/openrisc/trunk/orpsocv2/scripts/make/Makefile-board-modelsim.inc
20,7 → 20,6
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# VPI debugging interface set up |
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c |
VPI_SRC_VERILOG_DIR=vpi/verilog |
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch]) |
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# Modelsim VPI compile variables |
97,11 → 96,15
work: modelsim_dut.scr |
$(Q)if [ ! -e $@ ]; then vlib $@; fi |
$(Q)echo; echo "\t### Compiling Verilog design library ###"; echo |
$(Q)vlog $(QUIET) -f $< $(DUT_TOP) |
$(Q)vlog $(QUIET) -f $< $(DUT_TOP_FILE) |
$(Q)if [ "$(RTL_VHDL_SRC)" != "" ]; then \ |
echo; echo "\t### Compiling VHDL design library ###"; \ |
echo; \ |
vcom -93 $(QUIET) $(RTL_VHDL_SRC); \ |
fi |
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|
# |
# Run rule |
# Run rule, one for each vendor |
# |
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.PHONY : $(MODELSIM) |
108,9 → 111,9
ifeq ($(FPGA_VENDOR), actel) |
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work |
$(Q)echo; echo "\t### Compiling testbench ###"; echo |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $< |
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -L $(BACKEND_LIB) \ |
-o tb |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $< |
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \ |
-L $(BACKEND_LIB) -o tb |
$(Q)echo; echo "\t### Launching simulation ###"; echo |
$(Q)vsim $(VSIM_ARGS) tb |
endif |
118,9 → 121,18
ifeq ($(FPGA_VENDOR), xilinx) |
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work |
$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP) -f $< |
$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP) $(VOPT_ARGS) -o tb |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $< |
$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb |
$(Q)echo; echo "\t### Launching simulation ###"; echo |
$(Q)vsim $(VSIM_ARGS) tb |
endif |
|
ifeq ($(FPGA_VENDOR), altera) |
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(BACKEND_LIB) $(VPI_LIBS) work |
$(Q)echo; echo "\t### Compiling testbench ###"; echo |
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $< |
$(Q)vopt $(QUIET) $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) \ |
-L $(BACKEND_LIB) -o tb |
$(Q)echo; echo "\t### Launching simulation ###"; echo |
$(Q)vsim $(VSIM_ARGS) tb |
endif |
/openrisc/trunk/orpsocv2/scripts/make/Makefile-board-rtlmodules.inc
47,3 → 47,33
print-verilog-src: |
@echo echo; echo "\t### Verilog source ###"; echo |
@echo $(RTL_VERILOG_SRC) |
|
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ifeq ($(HAVE_VHDL), 1) |
# We have some VHDL we should include. |
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# Currently only supported for board builds - no common VHDL included at present |
BOARD_RTL_VHDL_DIR=$(BOARD_RTL_DIR)/vhdl |
BOARD_RTL_VHDL_MODULES=$(shell ls $(BOARD_RTL_VHDL_DIR)) |
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# |
# VHDL DUT source variables |
# |
VHDL_FILE_EXT=vhd |
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RTL_VHDL_SRC=$(shell for module in $(BOARD_RTL_VHDL_MODULES); do if [ -d $(BOARD_RTL_VHDL_DIR)/$$module ]; then ls $(BOARD_RTL_VHDL_DIR)/$$module/*.$(VHDL_FILE_EXT); fi; done) |
|
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# Rule for debugging this script |
print-vhdl-modules: |
@echo echo; echo "\t### Board VHDL modules ###"; echo |
@echo $(BOARD_RTL_VHDL_MODULES) |
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print-vhdl-src: |
@echo echo; echo "\t### VHDL modules and source ###"; echo |
@echo "modules: "; echo $(BOARD_RTL_VHDL_MODULES); echo |
@echo "file extension: "$(VHDL_FILE_EXT) |
@echo "source: "$(RTL_VHDL_SRC) |
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endif |
/openrisc/trunk/orpsocv2/scripts/make/Makefile-board-tops.inc
1,8 → 1,8
# Variables holding the names and paths to top-level files |
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# Name of testbench top |
RTL_TESTBENCH_TOP=$(DESIGN_NAME)_testbench |
RTL_TESTBENCH_TOP_NAME=$(DESIGN_NAME)_testbench |
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# Paths to top-level files |
DUT_TOP=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v |
BENCH_TOP=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v |
DUT_TOP_FILE=$(BOARD_RTL_VERILOG_DIR)/$(DESIGN_NAME)_top/$(DESIGN_NAME)_top.v |
BENCH_TOP_FILE=$(BOARD_BENCH_VERILOG_DIR)/$(DESIGN_NAME)_testbench.v |