OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 560 to Rev 561
    Reverse comparison

Rev 560 → Rev 561

/trunk/or1ksim/cpu/or1k/sprs.c
64,11 → 64,9
cont_run = 0;
return;
case SPR_TTMR:
/* CZ -- 04/09/01 Clear the interrupt in the PIC also... */
/* If it's cleared now and it was set, then we need to fix it */
if(~value & SPR_TTMR_IP & sprs[SPR_TTMR])
setsprbit(SPR_PICSR, 3, 0);
if (value & SPR_TTMR_M == 2) break;
setsprbit(SPR_PICSR, config.tick.irq, 0);
break;
case SPR_TTCR:
tt_stopped = 0;
break;
79,13 → 77,6
flag = 0;
sprs[SPR_SR] = value | SPR_SR_EXR; /* Exceptions are allways enabled */
break;
case SPR_EPCR_BASE:
if((value & 0xffffff00) == 0x00020600)
{
printf("SIMON: EPCR = ext_int\n");
cont_run = 0;
}
break;
case SPR_NPC:
{
extern unsigned long pc;
/trunk/or1ksim/tick/tick.c
25,6 → 25,7
#include <stdio.h>
#include <string.h>
 
#include "except.h"
#include "tick.h"
#include "../cpu/or1k/spr_defs.h"
#include "pic.h"
/trunk/or1ksim/pic/pic.c
55,6 → 55,9
it should. Someone needs to correct this if there is something
I am missing... */
 
/* From Sections 16.3 & 16.4, bits 0 & 1 are reserved */
picsr = mfspr(SPR_PICSR);
picpr = mfspr(SPR_PICPR) | 0x00000003;
sr = mfspr(SPR_SR);
 
/* Don't do anything if interrupts not currently enabled */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.