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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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Rev 561 → Rev 562

/trunk/mp3/rtl/verilog/xfpga_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/11/04 19:00:08 lampret
// First import.
//
 
`define EXCLUDE_DBG
// `define EXCLUDE_VGA
56,7 → 59,7
 
// Global connections
clk,
// clk2,
clk2,
rstn,
 
// Flash RAM
157,7 → 160,7
// Global connections
 
input clk;
//input clk2;
input clk2;
input rstn;
 
// Flash RAM
572,6 → 575,48
 
//////////////////////////////////////////////////////
// Development i/f
//`define DBG_IF_MODEL
`ifdef DBG_IF_MODEL
dbg_if_model dbg1 (
.tms_pad_i(jtag_tms),
.tck_pad_i(jtag_tck),
.trst_pad_i(jtag_trst),
.tdi_pad_i(jtag_tdi),
.tdo_pad_o(jtag_tdo),
 
.capture_dr_o(),
.shift_dr_o(),
.update_dr_o(),
.extest_selected_o(),
.bs_chain_i(1'b0),
.wb_rst_i(~resetn),
.risc_clk_i(wb_clk_i),
.risc_data_i(dbg_dat_risc),
.wp_i(dbg_wp),
.bp_i(dbg_bp),
.lsstatus_i(dbg_lss),
.istatus_i(dbg_is),
 
.risc_data_o(dbg_dat_dbg),
.risc_addr_o(dbg_adr),
.opselect_o(dbg_op),
.risc_stall_o(dbg_stall),
.reset_o(),
 
.wb_clk_i(wb_clk_i),
.wb_adr_o( wb_dm_adr_o ),
.wb_dat_i( wb_dm_dat_i ),
.wb_dat_o( wb_dm_dat_o ),
.wb_sel_o( wb_dm_sel_o ),
.wb_we_o( wb_dm_we_o ),
.wb_stb_o( wb_dm_stb_o ),
.wb_cyc_o( wb_dm_cyc_o ),
.wb_cab_o( wb_dm_cab_o ),
.wb_ack_i( wb_dm_ack_i ),
.wb_err_i( wb_dm_err_i )
);
`else
dbg_top dbg1 (
/*
.tms_pad_i(1'b0),
618,6 → 663,7
.wb_ack_i( wb_dm_ack_i ),
.wb_err_i( wb_dm_err_i )
);
`endif
 
/////////////////////////////////////////////////////////////////////////////////////
// The CPU block
624,7 → 670,7
`ifdef EXCLUDE_RISC
or1200_dummy risc (
`else
or1200 risc (
or1200_top risc (
`endif
.iwb_clk_i( wb_clk_i ),
.iwb_rst_i( ~resetn ),
638,6 → 684,7
.iwb_rty_i( wb_ri_rty_i ),
.iwb_we_o( wb_ri_we_o ),
.iwb_stb_o( wb_ri_stb_o ),
.iwb_cab_o( ),
 
.dwb_clk_i( wb_clk_i ),
.dwb_rst_i( ~resetn ),
652,10 → 699,17
.dwb_we_o( wb_rd_we_o ),
.dwb_stb_o( wb_rd_stb_o ),
 
.rst( ~resetn ),
.clk( wb_clk_i ),
.clkdiv_by_2( 1'b1 ),
 
.rst_i( ~resetn ),
.clk_i( clk2 ),
`ifdef OR1200_CLMODE_1TO2
.clmode_i( 2'b01 ),
`else
`ifdef OR1200_CLMODE_1TO4
.clmode_i( 2'b11 ),
`else
.clmode_i( 2'b00 ),
`endif
`endif
.dbg_stall_i(dbg_stall),
.dbg_dat_i(dbg_dat_dbg),
.dbg_adr_i(dbg_adr),
668,18 → 722,18
.dbg_bp_o(dbg_bp),
.dbg_dat_o(dbg_dat_risc),
 
.pm_clksd( ),
.pm_cpustall( 1'b0 ),
.pm_dc_gate( ),
.pm_ic_gate( ),
.pm_dmmu_gate( ),
.pm_immu_gate( ),
.pm_tt_gate( ),
.pm_cpu_gate( ),
.pm_wakeup( ),
.pm_lvolt( ),
// .pic_ints( { 19'b0, audio_dreq } )
.pic_ints( { my_int, 19'b0} )
.pm_clksd_o( ),
.pm_cpustall_i( 1'b0 ),
.pm_dc_gate_o( ),
.pm_ic_gate_o( ),
.pm_dmmu_gate_o( ),
.pm_immu_gate_o( ),
.pm_tt_gate_o( ),
.pm_cpu_gate_o( ),
.pm_wakeup_o( ),
.pm_lvolt_o( ),
// .pic_ints_i( { 19'b0, audio_dreq } )
.pic_ints_i( { my_int, 19'b0} )
);
 
/////////////////////////////////////////////////////////////////////////////////////
/trunk/mp3/rtl/verilog/mem_if/flash_top.v
44,12 → 44,18
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/11/04 19:00:09 lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "bench_define.v"
 
`ifdef FLASH_GENERIC
 
module flash_top (
clk, rstn,
 
81,6 → 87,98
output [20:0] a;
output a_oe;
 
reg [7:0] mem [65535:0];
wire [31:0] adr;
`ifdef FLASH_GENERIC_REGISTERED
reg wb_ack_o;
reg [31:0] wb_dat_o;
`endif
 
assign flash_rstn = 1'b1;
assign oen = 1'b1;
assign cen = 1'b1;
assign wen = 1'b1;
assign a = 21'b0;
assign a_oe = 1'b1;
 
initial $readmemh("../src/flash.in", mem, 0);
assign adr = {wb_adr_i[31:2], 2'b00};
`ifdef FLASH_GENERIC_REGISTERED
always @(negedge rstn or posedge clk)
if (!rstn)
wb_dat_o <= #1 32'h0000_0000;
else begin
wb_dat_o[7:0] <= #1 wb_adr_i < 65535 ? mem[adr+3] : 8'h00;
wb_dat_o[15:8] <= #1 wb_adr_i < 65535 ? mem[adr+2] : 8'h00;
wb_dat_o[23:16] <= #1 wb_adr_i < 65535 ? mem[adr+1] : 8'h00;
wb_dat_o[31:24] <= #1 wb_adr_i < 65535 ? mem[adr+0] : 8'h00;
end
`else
assign wb_dat_o[7:0] = wb_adr_i < 65535 ? mem[adr+3] : 8'h00;
assign wb_dat_o[15:8] = wb_adr_i < 65535 ? mem[adr+2] : 8'h00;
assign wb_dat_o[23:16] = wb_adr_i < 65535 ? mem[adr+1] : 8'h00;
assign wb_dat_o[31:24] = wb_adr_i < 65535 ? mem[adr+0] : 8'h00;
`endif
 
`ifdef FLASH_GENERIC_REGISTERED
always @(posedge clk or negedge rstn)
if (!rstn)
wb_ack_o <= #1 1'b0;
else
wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;
`else
assign wb_ack_o = wb_cyc_i & wb_stb_i;
`endif
 
assign wb_err_o = 1'b0;
 
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
always @(posedge clk)
if (wb_cyc_i)
if (wb_stb_i & wb_we_i) begin
$fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);
#100 $finish;
end else if (wb_ack_o)
$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
 
endmodule
 
`else
 
module flash_top (
clk, rstn,
 
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o,
 
flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
 
input clk;
input rstn;
 
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
 
output flash_rstn;
output oen;
output cen;
output wen;
input rdy;
inout [7:0] d;
output [20:0] a;
output a_oe;
 
reg [4:0] counter;
reg [31:0] data_sr;
reg f_ack;
89,7 → 187,7
always @(posedge clk or negedge rstn)
begin
if(!rstn)
counter <= 5'h0;
counter <= #1 5'h0;
else
if(!wb_cyc_i | (counter == 5'h10) | (|middle_tphqv))
counter <= #1 5'h0;
101,7 → 199,7
always @(posedge clk or negedge rstn)
begin
if(!rstn)
f_ack <= 1'h0;
f_ack <= #1 1'h0;
else
if(counter == 5'h0f && !(|middle_tphqv))
f_ack <= #1 1'h1;
145,7 → 243,7
 
always @(posedge clk or negedge rstn)
begin
if (!rstn) data_sr <= 32'b0;
if (!rstn) data_sr <= #1 32'b0;
else
if (counter[1:0] == 2'h3)
begin
154,9 → 252,11
2'h1 : data_sr[23:16] <= #1 d;
2'h2 : data_sr[15:8] <= #1 d;
2'h3 : data_sr[7:0] <= #1 d;
default : data_sr <= 32'bx;
default : data_sr <= #1 32'bx;
endcase
end
end
endmodule
 
`endif
/trunk/mp3/rtl/verilog/mem_if/sram_top.v
46,7 → 46,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2001/11/04 19:00:09 lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
225,7 → 228,7
if(wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
l0_wen <= #1 1'b0;
else
l0_wen <= 1'b1;
l0_wen <= #1 1'b1;
end
 
 
238,7 → 241,7
if(wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
r0_wen <= #1 1'b0;
else
r0_wen <= 1'b1;
r0_wen <= #1 1'b1;
end
 
 
/trunk/or1200/rtl/verilog/or1200_du.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/30 18:58:00 simons
// Trap insn couses break after exits ex_insn.
//
285,7 → 288,7
`endif
;
else
dbg_bp_r <= #1 1'b0;
dbg_bp_r <= #1 |except_stop;
 
//
// Write to DMR1
/trunk/or1200/rtl/verilog/or1200_ic_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
190,7 → 193,7
assign icbiu_sel_o = (ic_en & icfsm_biu_read) ? 4'b1111 : icpu_sel_i;
assign icbiu_cab_o = (ic_en) ? icfsm_burst : 1'b0;
assign icpu_rty_o = ~icpu_ack_o;
assign icimmu_tag_o = icpu_tag_i;
assign icimmu_tag_o = icimmu_err_o ? `OR1200_ITAG_BE : icpu_tag_i;
 
//
// CPU normal and error termination
232,8 → 235,7
.ic_en(ic_en),
.icimmu_cyc_i(icimmu_cyc_i),
.icimmu_stb_i(icimmu_stb_i),
// .icimmu_ci_i(icimmu_ci_i),
.icimmu_ci_i(1'b0),
.icimmu_ci_i(icimmu_ci_i),
.icpu_sel_i(icpu_sel_i),
.tagcomp_miss(tagcomp_miss),
.biudata_valid(icbiu_ack_i),
/trunk/or1200/rtl/verilog/or1200_freeze.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/13 10:02:21 lampret
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
//
89,7 → 92,7
multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
lsu_unstall, du_stall, mac_stall,
force_dslot_fetch,
if_freeze, id_freeze, ex_freeze, wb_freeze
genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze
);
 
//
106,6 → 109,7
input force_dslot_fetch;
input du_stall;
input mac_stall;
output genpc_freeze;
output if_freeze;
output id_freeze;
output ex_freeze;
130,6 → 134,7
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
// This way NOP is asserted from stage ID into EX stage.
//
assign genpc_freeze = du_stall | flushpipe;
assign if_freeze = id_freeze | extend_flush;
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
/trunk/or1200/rtl/verilog/or1200_alu.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/12 01:45:40 lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
219,10 → 222,11
//
always @(shrot_op or a or b) begin
case (shrot_op) // synopsys parallel_case
`OR1200_SHROTOP_SLL :
`OR1200_SHROTOP_SLL :
shifted_rotated = (a << b[4:0]);
`OR1200_SHROTOP_SRL :
shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
`OR1200_SHROTOP_ROR :
shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
237,7 → 241,7
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
case(comp_op[2:0]) // synopsys parallel_case full_case
`OR1200_COP_SFEQ:
flagforw = a_eq_b;
`OR1200_COP_SFNE:
263,7 → 267,7
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
case(comp_op[2:0]) // synopsys parallel_case
case(comp_op[2:0]) // synopsys parallel_case full_case
`OR1200_COP_SFEQ:
flagforw = (comp_a == comp_b);
`OR1200_COP_SFNE:
/trunk/or1200/rtl/verilog/or1200_cfgr.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
93,7 → 96,7
`ifdef OR1200_SYS_FULL_DECODE
if (!spr_addr[31:4])
`endif
case(spr_addr[3:0])
case(spr_addr[3:0]) // synopsys parallel_case
`OR1200_SPRGRP_SYS_VR: begin
spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
178,7 → 181,7
end
default: spr_dat_o = 32'h0000_0000;
endcase
`ifdef SYS_FULL_DECODE
`ifdef OR1200_SYS_FULL_DECODE
else
spr_dat_o = 32'h0000_0000;
`endif
/trunk/or1200/rtl/verilog/or1200_cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.19 2001/11/30 18:59:47 simons
// *** empty log message ***
//
238,6 → 241,7
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op;
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
wire [`OR1200_LSUOP_WIDTH-1:0] lsu_op;
wire genpc_freeze;
wire if_freeze;
wire id_freeze;
wire ex_freeze;
368,7 → 372,9
.epcr(epcr),
.spr_dat_i(spr_dataout),
.spr_pc_we(pc_we),
.genpc_refetch(genpc_refetch)
.genpc_refetch(genpc_refetch),
.genpc_freeze(genpc_freeze),
.flushpipe(flushpipe)
);
 
//
640,6 → 646,7
.force_dslot_fetch(force_dslot_fetch),
.du_stall(du_stall),
.mac_stall(mac_stall),
.genpc_freeze(genpc_freeze),
.if_freeze(if_freeze),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
680,6 → 687,10
.except_stop(except_stop),
.wb_pc(spr_dat_ppc),
.ex_pc(spr_dat_npc),
.id_pc(),
// .wb_pc(),
// .ex_pc(spr_dat_ppc),
// .id_pc(spr_dat_npc),
 
.datain(operand_b),
.du_dsr(du_dsr),
/trunk/or1200/rtl/verilog/or1200_immu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
241,7 → 244,7
//
// Cache Inhibit
//
assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : !icimmu_adr_o[30];
assign icimmu_ci_o = immu_en ? itlb_done & itlb_ci : 1'b0;
 
//
// Physical address is either translated virtual address or
/trunk/or1200/rtl/verilog/or1200_dc_fsm.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
191,6 → 194,11
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
else if (biudata_error) begin // load terminated with an error
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
else if (dcdmmu_ci_i & biudata_valid) begin // load from cache inhibit page
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
225,6 → 233,11
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
end
else if (biudata_error) begin // store terminated with an error
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
store <= #1 1'b0;
end
else if (dcdmmu_ci_i & biudata_valid) begin // store to cache inhibit page
state <= #1 `OR1200_DCFSM_IDLE;
hitmiss_eval <= #1 1'b0;
/trunk/or1200/rtl/verilog/or1200_dc_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
189,10 → 192,10
assign dcbiu_cyc_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_cyc_i;
assign dcbiu_stb_o = (dc_en) ? dcfsm_biu_read | dcfsm_biu_write : dcdmmu_stb_i;
assign dcbiu_we_o = (dc_en) ? dcfsm_biu_write : dcpu_we_i;
assign dcbiu_sel_o = (dc_en & dcfsm_biu_read) ? 4'b1111 : dcpu_sel_i;
assign dcbiu_sel_o = (dc_en & dcfsm_biu_read & !dcfsm_biu_write) ? 4'b1111 : dcpu_sel_i;
assign dcbiu_cab_o = (dc_en) ? dcfsm_burst : 1'b0;
assign dcpu_rty_o = ~dcpu_ack_o;
assign dcdmmu_tag_o = dcpu_tag_i;
assign dcdmmu_tag_o = dcdmmu_err_o ? `OR1200_DTAG_BE : dcpu_tag_i;
 
//
// DC/LSU normal and error termination
234,8 → 237,7
.dc_en(dc_en),
.dcdmmu_cyc_i(dcdmmu_cyc_i),
.dcdmmu_stb_i(dcdmmu_stb_i),
// .dcdmmu_ci_i(dcdmmu_ci_i),
.dcdmmu_ci_i(1'b0),
.dcdmmu_ci_i(dcdmmu_ci_i),
.dcpu_we_i(dcpu_we_i),
.dcpu_sel_i(dcpu_sel_i),
.tagcomp_miss(tagcomp_miss),
/trunk/or1200/rtl/verilog/or1200_dmmu_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.6 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
229,7 → 232,7
//
// Cache Inhibit
//
assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : !dcdmmu_adr_o[30];
assign dcdmmu_ci_o = dmmu_en ? dtlb_done & dtlb_ci : 1'b0;
 
//
// Physical address is either translated virtual address or
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.15 2001/11/27 23:13:11 lampret
// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
//
109,7 → 112,7
branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
except_started, except_stop,
wb_pc, ex_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
esr, sr, lsu_addr
);
 
157,6 → 160,7
output [12:0] except_stop;
output [31:0] wb_pc;
output [31:0] ex_pc;
output [31:0] id_pc;
 
//
// Internal regs and wires
188,8 → 192,9
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
assign except_start = (except_type != `OR1200_EXCEPT_NONE);
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
 
//
207,7 → 212,7
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
};
assign except_stop = {
222,7 → 227,7
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
sig_trap & du_dsr[`OR1200_DU_DSR_TE],
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_range & du_dsr[`OR1200_DU_DSR_RE]
};
 
234,12 → 239,11
id_pc <= #1 32'd0;
id_exceptflags <= #1 4'b0000;
end
else if (flushpipe) begin
id_pc <= #1 32'h0000_0000;
id_exceptflags <= #1 4'b0000;
end
else if (!id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display("%t: id_pc <= %h", $time, if_pc);
// synopsys translate_on
`endif
id_pc <= #1 if_pc;
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
end
272,6 → 276,13
delayed1_ex_dslot <= #1 1'b0;
delayed2_ex_dslot <= #1 1'b0;
end
else if (flushpipe) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 32'h0000_0000;
ex_exceptflags <= #1 4'b0000;
delayed1_ex_dslot <= #1 1'b0;
delayed2_ex_dslot <= #1 1'b0;
end
else if (!ex_freeze & id_freeze) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 id_pc;
308,7 → 319,7
//
// Flush pipeline
//
assign flushpipe = except_flushpipe | pc_we | extend_flush | extend_flush_last;
assign flushpipe = except_flushpipe | pc_we | extend_flush;
 
//
// We have started execution of exception handler:
315,7 → 326,7
// 1. Asserted for 3 clock cycles
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig;
assign except_flushpipe = |except_trig & !state;
 
//
// Exception FSM that sequences execution of exception handler
411,7 → 422,7
13'b0_0000_0001_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_BUSERR;
eear <= #1 lsu_addr;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
13'b0_0000_0000_1xxx: begin
except_type <= #1 `OR1200_EXCEPT_LPINT;
446,7 → 457,7
esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
end
`OR1200_EXCEPTFSM_FLU1:
if (!if_stall & !id_freeze)
// if (!if_stall & !id_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU2;
`OR1200_EXCEPTFSM_FLU2:
if (except_type == `OR1200_EXCEPT_TRAP) begin
455,10 → 466,11
extend_flush_last <= #1 1'b0;
except_type <= #1 `OR1200_EXCEPT_NONE;
end
else if (!if_stall & !id_freeze)
else
// if (!if_stall & !id_freeze)
state <= #1 `OR1200_EXCEPTFSM_FLU3;
`OR1200_EXCEPTFSM_FLU3:
if (!if_stall && !id_freeze)
// if (!if_stall && !id_freeze)
begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
469,11 → 481,12
state <= #1 `OR1200_EXCEPTFSM_FLU4;
end
`OR1200_EXCEPTFSM_FLU4: begin
state <= #1 `OR1200_EXCEPTFSM_FLU5;
extend_flush <= #1 1'b0;
extend_flush_last <= #1 1'b1;
end
state <= #1 `OR1200_EXCEPTFSM_FLU5;
extend_flush <= #1 1'b0;
extend_flush_last <= #1 1'b0; // damjan
end
`OR1200_EXCEPTFSM_FLU5: begin
if (!if_stall && !id_freeze) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: Just finished flushing pipeline.");
483,6 → 496,7
except_type <= #1 `OR1200_EXCEPT_NONE;
extend_flush_last <= #1 1'b0;
end
end
endcase
end
end
/trunk/or1200/rtl/verilog/or1200_genpc.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10 2001/11/20 18:46:15 simons
// Break point bug fixed
//
84,7 → 87,8
// Internal i/f
branch_op, except_type,
branch_addrofs, lr_restor, flag, taken, except_start,
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
genpc_freeze, flushpipe
);
 
//
125,6 → 129,8
input [31:0] spr_dat_i;
input spr_pc_we;
input genpc_refetch;
input genpc_freeze;
input flushpipe;
 
//
// Internal wires and regs
138,13 → 144,13
//
// Address of insn to be fecthed
//
assign icpu_adr_o = icpu_rty_i | genpc_refetch ? icpu_adr_i : pc;
assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
assign icpu_cyc_o = 1'b1;
assign icpu_stb_o = 1'b1;
assign icpu_cyc_o = !genpc_freeze;
assign icpu_stb_o = icpu_cyc_o;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
261,7 → 267,7
pcreg <= #1 30'd63;
else if (spr_pc_we)
pcreg <= #1 spr_dat_i[31:2];
else if (!icpu_rty_i & !genpc_refetch)
else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
pcreg <= #1 pc[31:2];
 
//
/trunk/or1200/rtl/verilog/or1200_mem2reg.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
87,10 → 90,15
//
`ifdef OR1200_MEM2REG_FAST
 
`define OR1200_SEL_00 2'b00
`define OR1200_SEL_01 2'b01
`define OR1200_SEL_10 2'b10
`define OR1200_SEL_11 2'b11
`define OR1200_M2R_BYTE0 4'b0000
`define OR1200_M2R_BYTE1 4'b0001
`define OR1200_M2R_BYTE2 4'b0010
`define OR1200_M2R_BYTE3 4'b0011
`define OR1200_M2R_EXTB0 4'b0100
`define OR1200_M2R_EXTB1 4'b0101
`define OR1200_M2R_EXTB2 4'b0110
`define OR1200_M2R_EXTB3 4'b0111
`define OR1200_M2R_ZERO 4'b0000
 
reg [7:0] regdata_hh;
reg [7:0] regdata_hl;
97,7 → 105,7
reg [7:0] regdata_lh;
reg [7:0] regdata_ll;
reg [width-1:0] aligned;
reg [1:0] sel_byte0, sel_byte1,
reg [3:0] sel_byte0, sel_byte1,
sel_byte2, sel_byte3;
 
assign regdata = {regdata_hh, regdata_hl, regdata_lh, regdata_ll};
106,21 → 114,16
// Byte select 0
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr})
{3'b01x, 2'b00}:
sel_byte0 = `OR1200_SEL_11;
{3'b01x, 2'b01}:
sel_byte0 = `OR1200_SEL_10;
{3'b01x, 2'b10}:
sel_byte0 = `OR1200_SEL_01;
{3'b01x, 2'b11}:
sel_byte0 = `OR1200_SEL_00;
{3'b10x, 2'b00}:
sel_byte0 = `OR1200_SEL_10;
{3'b10x, 2'b10}:
sel_byte0 = `OR1200_SEL_00;
default:
sel_byte0 = `OR1200_SEL_00;
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b01x, 2'b00}: // lbz/lbs 0
sel_byte0 = `OR1200_M2R_BYTE3; // take byte 3
{3'b01x, 2'b01}, // lbz/lbs 1
{3'b10x, 2'b00}: // lhz/lhs 0
sel_byte0 = `OR1200_M2R_BYTE2; // take byte 2
{3'b01x, 2'b10}: // lbz/lbs 2
sel_byte0 = `OR1200_M2R_BYTE1; // take byte 1
default: // all other cases
sel_byte0 = `OR1200_M2R_BYTE0; // take byte 0
endcase
end
 
128,15 → 131,21
// Byte select 1
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr})
{3'b010, 2'bxx}:
sel_byte1 = `OR1200_SEL_00; // zero extend
{3'b011, 2'bxx}:
sel_byte1 = `OR1200_SEL_10; // sign extend byte
{3'b10x, 2'b00}:
sel_byte1 = `OR1200_SEL_11;
default:
sel_byte1 = `OR1200_SEL_01;
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}: // lbz
sel_byte1 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}: // lbs 0
sel_byte1 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte1 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}: // lbs 2
sel_byte1 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte1 = `OR1200_M2R_EXTB0; // sign extend from byte 0
{3'b10x, 2'b00}: // lhz/lhs 0
sel_byte1 = `OR1200_M2R_BYTE3; // take byte 3
default: // all other cases
sel_byte1 = `OR1200_M2R_BYTE1; // take byte 1
endcase
end
 
144,16 → 153,22
// Byte select 2
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr})
{3'b010, 2'bxx},
{3'b100, 2'bxx}:
sel_byte2 = `OR1200_SEL_00; // zero extend
{3'b011, 2'bxx}:
sel_byte2 = `OR1200_SEL_01; // sign extend byte
{3'b101, 2'bxx}:
sel_byte2 = `OR1200_SEL_11; // sign extend halfword
default:
sel_byte2 = `OR1200_SEL_10;
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}, // lbz
{3'b100, 2'bxx}: // lhz
sel_byte2 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}, // lbs 0
{3'b101, 2'b00}: // lhs 0
sel_byte2 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte2 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}, // lbs 2
{3'b101, 2'b10}: // lhs 0
sel_byte2 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte2 = `OR1200_M2R_EXTB0; // sign extend from byte 0
default: // all other cases
sel_byte2 = `OR1200_M2R_BYTE2; // take byte 2
endcase
end
 
161,16 → 176,22
// Byte select 3
//
always @(addr or lsu_op) begin
casex({lsu_op[2:0], addr})
{3'b010, 2'bxx},
{3'b100, 2'bxx}:
sel_byte3 = `OR1200_SEL_00; // zero extend
{3'b011, 2'bxx}:
sel_byte3 = `OR1200_SEL_01; // sign extend byte
{3'b101, 2'bxx}:
sel_byte3 = `OR1200_SEL_10; // sign extend halfword
default:
sel_byte3 = `OR1200_SEL_11;
casex({lsu_op[2:0], addr}) // synopsys parallel_case
{3'b010, 2'bxx}, // lbz
{3'b100, 2'bxx}: // lhz
sel_byte3 = `OR1200_M2R_ZERO; // zero extend
{3'b011, 2'b00}, // lbs 0
{3'b101, 2'b00}: // lhs 0
sel_byte3 = `OR1200_M2R_EXTB3; // sign extend from byte 3
{3'b011, 2'b01}: // lbs 1
sel_byte3 = `OR1200_M2R_EXTB2; // sign extend from byte 2
{3'b011, 2'b10}, // lbs 2
{3'b101, 2'b10}: // lhs 0
sel_byte3 = `OR1200_M2R_EXTB1; // sign extend from byte 1
{3'b011, 2'b11}: // lbs 3
sel_byte3 = `OR1200_M2R_EXTB0; // sign extend from byte 0
default: // all other cases
sel_byte3 = `OR1200_M2R_BYTE3; // take byte 3
endcase
end
 
179,16 → 200,16
//
always @(sel_byte0 or memdata) begin
case(sel_byte0) // synopsys full_case parallel_case infer_mux
`OR1200_SEL_00: begin
`OR1200_M2R_BYTE0: begin
regdata_ll = memdata[7:0];
end
`OR1200_SEL_01: begin
`OR1200_M2R_BYTE1: begin
regdata_ll = memdata[15:8];
end
`OR1200_SEL_10: begin
`OR1200_M2R_BYTE2: begin
regdata_ll = memdata[23:16];
end
`OR1200_SEL_11: begin
`OR1200_M2R_BYTE3: begin
regdata_ll = memdata[31:24];
end
endcase
199,18 → 220,27
//
always @(sel_byte1 or memdata) begin
case(sel_byte1) // synopsys full_case parallel_case infer_mux
`OR1200_SEL_00: begin
regdata_lh = 8'b0;
`OR1200_M2R_ZERO: begin
regdata_lh = 8'h00;
end
`OR1200_SEL_01: begin
`OR1200_M2R_BYTE1: begin
regdata_lh = memdata[15:8];
end
`OR1200_SEL_10: begin
`OR1200_M2R_BYTE3: begin
regdata_lh = memdata[31:24];
end
`OR1200_M2R_EXTB0: begin
regdata_lh = {8{memdata[7]}};
end
`OR1200_SEL_11: begin
regdata_lh = memdata[31:24];
`OR1200_M2R_EXTB1: begin
regdata_lh = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_lh = {8{memdata[23]}};
end
`OR1200_M2R_EXTB3: begin
regdata_lh = {8{memdata[31]}};
end
endcase
end
 
219,18 → 249,24
//
always @(sel_byte2 or memdata) begin
case(sel_byte2) // synopsys full_case parallel_case infer_mux
`OR1200_SEL_00: begin
regdata_hl = 8'b0;
`OR1200_M2R_ZERO: begin
regdata_hl = 8'h00;
end
`OR1200_SEL_01: begin
`OR1200_M2R_BYTE2: begin
regdata_hl = memdata[23:16];
end
`OR1200_M2R_EXTB0: begin
regdata_hl = {8{memdata[7]}};
end
`OR1200_SEL_10: begin
regdata_hl = memdata[23:16];
end
`OR1200_SEL_11: begin
`OR1200_M2R_EXTB1: begin
regdata_hl = {8{memdata[15]}};
end
`OR1200_M2R_EXTB2: begin
regdata_hl = {8{memdata[23]}};
end
`OR1200_M2R_EXTB3: begin
regdata_hl = {8{memdata[31]}};
end
endcase
end
 
239,18 → 275,24
//
always @(sel_byte3 or memdata) begin
case(sel_byte3) // synopsys full_case parallel_case infer_mux
`OR1200_SEL_00: begin
regdata_hh = 8'b0;
`OR1200_M2R_ZERO: begin
regdata_hh = 8'h00;
end
`OR1200_SEL_01: begin
`OR1200_M2R_BYTE3: begin
regdata_hh = memdata[31:24];
end
`OR1200_M2R_EXTB0: begin
regdata_hh = {8{memdata[7]}};
end
`OR1200_SEL_10: begin
`OR1200_M2R_EXTB1: begin
regdata_hh = {8{memdata[15]}};
end
`OR1200_SEL_11: begin
regdata_hh = memdata[31:24];
`OR1200_M2R_EXTB2: begin
regdata_hh = {8{memdata[23]}};
end
`OR1200_M2R_EXTB3: begin
regdata_hh = {8{memdata[31]}};
end
endcase
end
 
/trunk/or1200/rtl/verilog/or1200_ic_fsm.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
192,6 → 195,11
hitmiss_eval <= #1 1'b1;
load <= #1 1'b1;
end
else if (!icimmu_cyc_i | !icimmu_stb_i) begin // load aborted (usually caused by exception)
state <= #1 `OR1200_ICFSM_IDLE;
hitmiss_eval <= #1 1'b0;
load <= #1 1'b0;
end
else // load in-progress
hitmiss_eval <= #1 1'b0;
`OR1200_ICFSM_LREFILL3 : begin
/trunk/or1200/rtl/verilog/or1200_ctrl.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.14 2001/11/30 18:59:17 simons
// force_dslot_fetch does not work - allways zero.
//
430,6 → 433,8
always @(posedge clk or posedge rst) begin
if (rst)
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F};
else if (flushpipe)
wb_insn <= #1 {`OR1200_OR32_NOP, 26'h000_444F}; // wb_insn[0] must be 1
else if (!wb_freeze) begin
wb_insn <= #1 ex_insn;
end

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