URL
https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
Subversion Repositories or1k_old
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- This comparison shows the changes necessary to convert path
/
- from Rev 564 to Rev 565
- ↔ Reverse comparison
Rev 564 → Rev 565
/trunk/mp3/sim/run/run_regression
4,18 → 4,18
set failed = 0; |
set all_tests = 0; |
# List all test cases |
set simpletests=(immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \ |
immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc) |
set complextests=(immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \ |
immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \ |
set simpletests=(buserr-nocache immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \ |
buserr-icdc immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc) |
set complextests=(buserr-ic immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \ |
buserr-dc immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \ |
mul-nocache-O0 cbasic-nocache-O0 \ |
mul-icdc-O0 cbasic-icdc-O0 \ |
mul-ic-O0 cbasic-ic-O0 \ |
mul-dc-O0 cbasic-dc-O0) |
set simpletimes=(10 10 40 40 40 40 40 60 \ |
10 10 40 40 40 40 40 40) |
set complextimes=(10 10 40 40 40 40 40 40 \ |
10 10 40 40 40 40 40 60 \ |
set simpletimes=(10 10 10 40 40 40 40 40 60 \ |
10 10 10 40 40 40 40 40 40) |
set complextimes=(10 10 10 40 40 40 40 40 40 \ |
10 10 10 40 40 40 40 40 100 \ |
40 40 \ |
40 40 \ |
40 40 \ |
141,8 → 141,8
cat ncsim.out |
exit |
else |
set magic=`tail -1 sprs.log | cut -d'-' -f2 | cut -c2-9` |
set magictime=`tail -1 sprs.log | cut -d'n' -f1` |
set magic=`tail -1 nop.log | cut -d'(' -f2 | cut -d')' -f1` |
set magictime=`tail -1 nop.log | cut -d'n' -f1` |
if ($magic == "deaddead") then |
echo "\t### Passed (@time $magictime)" |
@ all_tests += 1; |
155,6 → 155,7
mv executed.log ../log/i${iter}-${test}-executed.log |
mv sram.log ../log/i${iter}-${test}-sram.log |
mv sprs.log ../log/i${iter}-${test}-sprs.log |
mv nop.log ../log/i${iter}-${test}-nop.log |
endif |
end |
|
/trunk/mp3/sim/bin/nc.scr
23,6 → 23,8
../../bench/models/codec_model.v |
+incdir+../../bench/models/28f016s3 |
../../bench/models/28f016s3/bwsvff.v |
../../bench/verilog/dbg_if_model.v |
../../bench/verilog/wb_master.v |
|
// |
// RTL files (top) |