URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 569 to Rev 570
- ↔ Reverse comparison
Rev 569 → Rev 570
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_spram_256x32.v
3,7 → 3,7
//// eth_spram_256x32.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_shiftreg.v
3,7 → 3,7
//// eth_shiftreg.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxethmac.v
3,7 → 3,7
//// eth_rxethmac.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxcounters.v
3,7 → 3,7
//// eth_rxcounters.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txethmac.v
1,9 → 1,9
////////////////////////////////////////////////////////////////////// |
//// //// |
//// eth_txethmac.v //// |
/// //// |
/// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_wishbone.v
3,7 → 3,7
//// eth_wishbone.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txcounters.v
3,7 → 3,7
//// eth_txcounters.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_random.v
3,7 → 3,7
//// eth_random.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_receivecontrol.v
3,7 → 3,7
//// eth_receivecontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_register.v
3,7 → 3,7
//// eth_register.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_clockgen.v
3,7 → 3,7
//// eth_clockgen.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_miim.v
3,7 → 3,7
//// eth_miim.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_outputcontrol.v
3,7 → 3,7
//// eth_outputcontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_maccontrol.v
3,7 → 3,7
//// eth_maccontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_transmitcontrol.v
3,7 → 3,7
//// eth_transmitcontrol.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_macstatus.v
3,7 → 3,7
//// eth_macstatus.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_rxstatem.v
3,7 → 3,7
//// eth_rxstatem.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_registers.v
3,7 → 3,7
//// eth_registers.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_crc.v
3,7 → 3,7
//// eth_crc.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
/openrisc/trunk/orpsocv2/rtl/verilog/ethmac/eth_txstatem.v
3,7 → 3,7
//// eth_txstatem.v //// |
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/project,ethmac //// |
//// http://www.opencores.org/project,ethmac //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |