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  • This comparison shows the changes necessary to convert path
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    from Rev 569 to Rev 570
    Reverse comparison

Rev 569 → Rev 570

/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
211,9 → 214,9
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_range & ~du_dsr[`OR1200_DU_DSR_RE]
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
assign except_stop = {
inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
226,9 → 229,9
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
sig_range & du_dsr[`OR1200_DU_DSR_RE],
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_range & du_dsr[`OR1200_DU_DSR_RE]
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
 
//

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