OpenCores
URL https://opencores.org/ocsvn/can/can/trunk

Subversion Repositories can

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /
    from Rev 57 to Rev 58
    Reverse comparison

Rev 57 → Rev 58

/trunk/rtl/verilog/can_register_syn.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
59,7 → 63,9
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
module can_register_syn
/trunk/rtl/verilog/can_register_asyn.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
59,7 → 63,9
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
module can_register_asyn
/trunk/rtl/verilog/can_register.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
59,7 → 63,9
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
module can_register
/trunk/rtl/verilog/can_register_asyn_syn.v
50,6 → 50,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3 2003/02/09 02:24:33 mohor
// Bosch license warning added. Error counters finished. Overload frames
// still need to be fixed.
//
// Revision 1.2 2002/12/27 00:12:52 mohor
// Header changed, testbench improved to send a frame (crc still missing).
//
59,7 → 63,9
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
module can_register_asyn_syn

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.