URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 571 to Rev 572
- ↔ Reverse comparison
Rev 571 → Rev 572
/trunk/or1ksim/cpu/common/abstract.c
65,7 → 65,7
inline unsigned long translate_vrt_to_phy_add(unsigned long virtaddr, int write_access) |
{ |
if (config.ic.tagtype == CT_NONE) |
return virtaddr; |
return immu_translate(virtaddr, write_access); |
else |
if (config.ic.tagtype == CT_VIRTUAL) { |
return immu_translate(virtaddr, write_access); |
109,7 → 109,7
unsigned long simulate_dc_mmu_load(unsigned long virtaddr) |
{ |
if (config.dc.tagtype == CT_NONE) |
return virtaddr; |
return dmmu_translate(virtaddr, 0); |
else |
if (config.dc.tagtype == CT_VIRTUAL) { |
dc_simulate_read(virtaddr); |
135,7 → 135,7
unsigned long simulate_dc_mmu_store(unsigned long virtaddr) |
{ |
if (config.dc.tagtype == CT_NONE) |
return virtaddr; |
return dmmu_translate(virtaddr, 0); |
else |
if (config.dc.tagtype == CT_VIRTUAL) { |
dc_simulate_write(virtaddr); |
/trunk/or1ksim/cpu/or1k/sprs.c
75,7 → 75,7
flag = 1; |
else |
flag = 0; |
sprs[SPR_SR] = value | SPR_SR_EXR; /* Exceptions are allways enabled */ |
value = value | SPR_SR_EXR; /* Exceptions are allways enabled */ |
break; |
case SPR_NPC: |
{ |
/trunk/or1ksim/cpu/or1k/except.c
107,6 → 107,10
mtspr(SPR_EPCR_BASE, pending.saved); |
else if (except == EXCEPT_RANGE) |
mtspr(SPR_EPCR_BASE, pending.saved); |
else if (except == EXCEPT_ITLBMISS) |
mtspr(SPR_EPCR_BASE, pending.saved); |
else if (except == EXCEPT_IPF) |
mtspr(SPR_EPCR_BASE, pending.saved); |
else |
mtspr(SPR_EPCR_BASE, pc_saved); |
|
/trunk/or1ksim/mmu/dmmu.c
37,8 → 37,8
unsigned long tagaddr; |
unsigned long vpn, ppn; |
extern int mem_cycles; |
|
if (!(mfspr(SPR_SR) & SPR_SR_DME) || (!testsprbits(SPR_SR, SPR_SR_DME))) |
|
if (!(mfspr(SPR_SR) & SPR_SR_DME) || !testsprbits(SPR_UPR, SPR_UPR_DMP)) |
return virtaddr; |
|
/* Which set to check out? */ |
/trunk/or1ksim/sim-config.c
851,10 → 851,12
|
void immu_enabled () { |
setsprbits (SPR_UPR, SPR_UPR_IMP, tempL & 1); |
config.immu.enabled = tempL; |
} |
|
void dmmu_enabled () { |
setsprbits (SPR_UPR, SPR_UPR_DMP, tempL & 1); |
config.dmmu.enabled = tempL; |
} |
|
void immu_nsets () { |