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URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 573 to Rev 574
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  •

Rev 573 → Rev 574

/trunk/or1ksim/cpu/or32/execute.c
309,9 → 309,6
{
debug (9, "%i %08X\n", op_no, op[op_no + MAX_OPERANDS]);
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
if (op[op_no] & 0x01) {
return 0;
}
return eval_mem16 (op[op_no], breakpoint);
}
else {
363,13 → 360,9
/* Mark this as destination operand. */
op[op_no + MAX_OPERANDS] |= OPTYPE_DST;
if (op[op_no + MAX_OPERANDS] & OPTYPE_DIS) {
if (op[op_no] & 0x01) {
except_handle (EXCEPT_ALIGN, op[op_no]);
return;
}
set_mem16(op[op_no], value, breakpoint);
}
else
else
{
fprintf (stderr, "Invalid operand type.\n");
exit (1);
401,10 → 394,11
debug(5, "fetch()\n");
 
/* Update the pc for pending exceptions, or get physical pc */
if (!pending.valid)
pc_phy = translate_vrt_to_phy_add(pc);
 
if(pending.valid)
except_handle_backend(pending.type, pending.address, pending.saved);
else
pc_phy = translate_vrt_to_phy_add(pc);
 
if (CHECK_BREAKPOINTS) {
/* MM: Check for breakpoint. This has to be done in fetch cycle,
/trunk/or1ksim/cpu/common/abstract.c
86,7 → 86,7
cache for virtually indexed insn cache or after simulating insn cache
for physically indexed insn cache. It returns physical address. */
 
unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr)
static inline unsigned long simulate_ic_mmu_fetch(unsigned long virtaddr)
{
 
unsigned long phyaddr;
106,7 → 106,7
cache for virtually indexed data cache or after simulating data cache
for physically indexed data cache. It returns physical address. */
 
unsigned long simulate_dc_mmu_load(unsigned long virtaddr)
static inline unsigned long simulate_dc_mmu_load(unsigned long virtaddr)
{
if (config.dc.tagtype == CT_NONE)
return dmmu_translate(virtaddr, 0);
132,7 → 132,7
cache for virtually indexed data cache or after simulating data cache
for physically indexed data cache. It returns physical address. */
 
unsigned long simulate_dc_mmu_store(unsigned long virtaddr)
static inline unsigned long simulate_dc_mmu_store(unsigned long virtaddr)
{
if (config.dc.tagtype == CT_NONE)
return dmmu_translate(virtaddr, 0);
370,17 → 370,16
if (config.sim.mprofile)
mprofile (memaddr, MPROF_32 | MPROF_READ);
 
cur_vadd = memaddr;
if (config.dmmu.enabled)
memaddr = simulate_dc_mmu_load(memaddr);
if (pending.valid)
return 0;
 
if (memaddr & 3) {
except_handle (EXCEPT_ALIGN, memaddr);
return 0;
}
 
cur_vadd = memaddr;
memaddr = simulate_dc_mmu_load(memaddr);
if (pending.valid)
return 0;
 
if (config.debug.enabled)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
temp = evalsim_mem32(memaddr);
417,17 → 416,16
if (config.sim.mprofile)
mprofile (memaddr, MPROF_16 | MPROF_READ);
 
cur_vadd = memaddr;
if (config.dmmu.enabled)
memaddr = simulate_dc_mmu_load(memaddr);
if (pending.valid)
return 0;
if (memaddr & 1) {
except_handle (EXCEPT_ALIGN, memaddr);
return 0;
}
 
cur_vadd = memaddr;
memaddr = simulate_dc_mmu_load(memaddr);
if (pending.valid)
return 0;
if (config.debug.enabled)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
447,10 → 445,10
mprofile (memaddr, MPROF_8 | MPROF_READ);
 
cur_vadd = memaddr;
if (config.dmmu.enabled)
memaddr = simulate_dc_mmu_load(memaddr);
memaddr = simulate_dc_mmu_load(memaddr);
if (pending.valid)
return 0;
if (config.debug.enabled)
*breakpoint += CheckDebugUnit(DebugLoadAddress,memaddr); /* 28/05/01 CZ */
 
466,20 → 464,18
{
if (config.sim.mprofile)
mprofile (memaddr, MPROF_32 | MPROF_WRITE);
cur_vadd = memaddr;
if (config.dmmu.enabled)
memaddr = simulate_dc_mmu_store(memaddr);
 
/* If we produced exception don't set anything */
if (pending.valid)
return;
 
if (memaddr & 3) {
except_handle (EXCEPT_ALIGN, memaddr);
return;
}
 
cur_vadd = memaddr;
memaddr = simulate_dc_mmu_store(memaddr);
/* If we produced exception don't set anything */
if (pending.valid)
return;
 
if (config.debug.enabled) {
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
*breakpoint += CheckDebugUnit(DebugStoreData,value);
526,18 → 522,16
if (config.sim.mprofile)
mprofile (memaddr, MPROF_16 | MPROF_WRITE);
if (memaddr & 1) {
except_handle (EXCEPT_ALIGN, memaddr);
return;
}
cur_vadd = memaddr;
if (config.dmmu.enabled)
memaddr = simulate_dc_mmu_store(memaddr);
 
memaddr = simulate_dc_mmu_store(memaddr);
/* If we produced exception don't set anything */
if (pending.valid)
return;
if (memaddr & 1) {
except_handle (EXCEPT_ALIGN, memaddr);
return;
}
 
if (config.debug.enabled) {
*breakpoint += CheckDebugUnit(DebugStoreAddress,memaddr); /* 28/05/01 CZ */
584,9 → 578,7
mprofile (memaddr, MPROF_8 | MPROF_WRITE);
cur_vadd = memaddr;
if (config.dmmu.enabled)
memaddr = simulate_dc_mmu_store(memaddr);
 
memaddr = simulate_dc_mmu_store(memaddr);
/* If we produced exception don't set anything */
if (pending.valid) return;
 
/trunk/or1ksim/testbench/Makefile.in
94,6 → 94,7
 
OR1K_TESTS = basic cache cfg dmatest eth mmu except_test pic
IND_TESTS = exit cbasic local_global mul mycompress dhry functest mem_test
# inst_set_test
ACV_TESTS = acv_uart acv_gpio
MC_TESTS = mc_dram mc_ssram mc_async mc_sync
# Subdirectory tests
123,6 → 124,8
functest_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
mem_test_SOURCES = $(OR1K_SUPPORT_S) support.h mem_test.c
mem_test_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
inst_set_test_SOURCES = $(OR1K_SUPPORT_S) support.h inst_set_test.c
inst_set_test_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
###############################################
 
######### MC Tests ############################
139,7 → 142,7
##### Platform Dependent Tests - not OR1K #####
@OR1K_EXCEPT_TRUE@basic_SOURCES = basic.S spr_defs.h
@OR1K_EXCEPT_FALSE@basic_SOURCES =
@OR1K_EXCEPT_TRUE@basic_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
@OR1K_EXCEPT_TRUE@basic_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
@OR1K_EXCEPT_TRUE@basic_LDADD =
@OR1K_EXCEPT_TRUE@cache_SOURCES = $(OR1K_SUPPORT_S) support.h cache.c
@OR1K_EXCEPT_FALSE@cache_SOURCES =
146,7 → 149,7
@OR1K_EXCEPT_TRUE@cache_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
@OR1K_EXCEPT_TRUE@cfg_SOURCES = cfg.S spr_defs.h
@OR1K_EXCEPT_FALSE@cfg_SOURCES =
@OR1K_EXCEPT_TRUE@cfg_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
@OR1K_EXCEPT_TRUE@cfg_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
@OR1K_EXCEPT_TRUE@cfg_LDADD =
@OR1K_EXCEPT_TRUE@pic_SOURCES = $(OR1K_SUPPORT_S) support.h pic.c
@OR1K_EXCEPT_FALSE@pic_SOURCES =
163,7 → 166,7
@OR1K_EXCEPT_TRUE@acv_gpio_SOURCES = $(OR1K_SUPPORT_S) support.h acv_gpio.c
@OR1K_EXCEPT_FALSE@acv_gpio_SOURCES =
@OR1K_EXCEPT_TRUE@acv_gpio_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
@OR1K_EXCEPT_TRUE@mmu_SOURCES = $(OR1K_SUPPORT_S) support.h mmu.c mmu_asm.S -DCOPY_SECTIONS
@OR1K_EXCEPT_TRUE@mmu_SOURCES = $(OR1K_SUPPORT_S) support.h mmu.c mmu_asm.S
@OR1K_EXCEPT_FALSE@mmu_SOURCES =
@OR1K_EXCEPT_TRUE@mmu_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
@OR1K_EXCEPT_TRUE@except_test_SOURCES = except_test_s.S except_test.c spr_defs.h
/trunk/or1ksim/testbench/functest.c
1,3 → 1,4
/* Simple test, that test function parameters */
#include "support.h"
 
int gk = 0;
/trunk/or1ksim/testbench/cache.c
266,8 → 266,8
This test can not be run on or1ksim. */
rc = ic_test();
report(rc);
exit(0);
 
return 0;
}
 
/* just for size calculation */
/trunk/or1ksim/testbench/cache.cfg
1,101 → 1,3
/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001, Marko Mlinar, markom@opencores.org
 
This file includes a lot of help about configurations and default one
 
This file is part of OpenRISC 1000 Architectural Simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
The or1ksim have various parameters, which can be set in configuration
files. Multiple configurations may be used and switched between at
or1ksim startup.
By default, or1ksim loads condfiguration file from './sim.cfg' and if not
found it checks '~/.or1k/sim.cfg'. If even this file is not found or
all parameters are not defined, default configuration is used.
Users should not rely on default configuration, but rather redefine all
critical settings, since default configuration may differ in newer
versions of the or1ksim.
If multiple configurations are used, user can switch between them by
supplying -f <filename.cfg> option when starting simulator.
 
This file may contain (standard C) only comments - no // support.
 
Like normal configuration file, this file is divided in sections,
where each section is described in detail also.
 
Some section also have subsections. One example of such subsection is
block:
 
device <index>
instance specific parameters...
enddevice
 
which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
This section specifies how is initial memory generated and which blocks
it consist of.
 
type = random/unknown/pattern
specifies the initial memory values. 'random' parameter generate
random memory using seed 'random_seed' parameter. 'pattern' parameter
fills memory with 'pattern' parameter and 'unknown' does not specify
how memory should be generated - the fastest option.
 
random_seed = <value>
random seed for randomizer, used if type = random
 
pattern = <value>
pattern to fill memory, used if type = pattern
 
nmemories = <value>
number of memory instances connected
 
instance specific:
baseaddr = <hex_value>
memory start address
 
size = <hex_value>
memory size
 
name = "<string>"
memory block name
 
ce = <value>
chip enable index of the memory instance
 
delayr = <value>
cycles, required for read access, -1 if instance does not support reading
 
delayw = <value>
cycles, required for write access, -1 if instance does not support writing
 
16550 = 0/1
0, if this device is uart 16450 and 1, if it is 16550
 
log = "<filename>"
filename, where to log memory accesses to, no log, if log command is not specified
*/
 
section memory
/*random_seed = 12345
type = random*/
122,31 → 24,6
enddevice
end
 
 
/* IMMU SECTION
 
This section configures Instruction Memory Menangement Unit
 
enabled = 0/1
whether IMMU is enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of ITLB sets; must be power of two
 
nways = <value>
number of ITLB ways
 
pagesize = <value>
instruction page size; must be power of two
 
entrysize = <value>
instruction entry size in bytes
 
ustates = <value>
number of ITLB usage states (2, 3, 4 etc., max is 4)
*/
 
section immu
enabled = 0
nsets = 32
154,31 → 31,6
pagesize = 8192
end
 
 
/* DMMU SECTION
 
This section configures Data Memory Menangement Unit
 
enabled = 0/1
whether DMMU is enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DTLB sets; must be power of two
 
nways = <value>
number of DTLB ways
 
pagesize = <value>
data page size; must be power of two
 
entrysize = <value>
data entry size in bytes
 
ustates = <value>
number of DTLB usage states (2, 3, 4 etc., max is 4)
*/
 
section dmmu
enabled = 0
nsets = 32
186,28 → 38,6
pagesize = 8192
end
 
 
/* IC SECTION
 
This section configures Instruction Cache
 
enabled = 0/1
whether IC is enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of IC sets; must be power of two
 
nways = <value>
number of IC ways
 
blocksize = <value>
IC block size in bytes; must be power of two
 
ustates = <value>
number of IC usage states (2, 3, 4 etc., max is 4)
*/
 
section ic
enabled = 1
nsets = 512
215,28 → 45,6
blocksize = 16
end
 
 
/* DC SECTION
 
This section configures Data Cache
 
enabled = 0/1
whether DC is enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DC sets; must be power of two
 
nways = <value>
number of DC ways
 
blocksize = <value>
DC block size in bytes; must be power of two
 
ustates = <value>
number of DC usage states (2, 3, 4 etc., max is 4)
*/
 
section dc
enabled = 1
nsets = 512
244,112 → 52,6
blocksize = 16
end
 
/* SIM SECTION
 
This section specifies how should sim behave.
 
verbose = 0/1
whether to print out extra messages
 
debug = 0-9
= 0 disabled debug messages
1-9 level of sim debug information, greater the number more verbose is
the output
 
profile = 0/1
whether to generate profiling file 'sim.profile'
 
prof_fn = "<filename>"
filename, where to generate profiling info, used
only if 'profile' is set
 
history = 0/1
whether instruction execution flow is tracked for
display by simulator hist command. Useful for
back-trace debugging.
 
exe_log = 0/1
whether execution log should be generated
 
exe_log_fn = "<filename>"
where to put execution log in, used only if 'exe_log'
is set
clkcycle = <value>[ps|ns|us|ms]
specifies time measurement for one cycle
*/
 
section sim
/* verbose = 1 */
debug = 0
profile = 0
prof_fn = "sim.profile"
 
history = 1
exe_log = 0
exe_log_fn = "executed.log"
clkcycle = 4ns
end
 
 
/* SECTION VAPI
 
This section configures Verification API, used for Advanced
Core Verification.
 
enabled = 0/1
whether to start VAPI server
 
server_port = <value>
TCP/IP port to start VAPI server on
 
log_enabled = 0/1
whether logging of VAPI requests is enabled
 
vapi_fn = <filename>
specifies filename where to log into, if log_enabled is selected
*/
 
section VAPI
enabled = 0
server_port = 9998
log_enabled = 0
vapi_log_fn = "vapi.log"
end
 
 
/* CPU SECTION
 
This section specifies various CPU parameters.
 
ver = <value>
rev = <value>
specifies version and revision of the CPU used
 
upr = <value>
changes the upr register
 
superscalar = 0/1
whether CPU is scalar or superscalar
(modify cpu/or32/execute.c to tune superscalar model)
 
hazards = 0/1
whether data hazards are tracked in superscalar CPU
and displayed by the simulator r command
 
dependstats = 0/1
whether inter-instruction dependencies are calculated
and displayed by simulator stats command.
 
btic = 0/1
enable branch target instruction cache model
 
bpb = 0/1
enable branch prediction buffer model
 
parameters for CPU analysis
*/
 
section cpu
ver = 0x1200
rev = 0x0001
358,195 → 60,3
hazards = 0
dependstats = 0
end
 
section bpb
enabled = 0
btic = 0
end
 
/* DEBUG SECTION
 
This sections specifies how debug unit should behave.
 
enabled = 0/1
whether debug unit is enabled
 
gdb_enabled = 0/1
whether to start gdb server at 'server_port' port
 
server_port = <value>
TCP/IP port to start gdb server on, used only if gdb_enabled
is set
 
section debug
enabled = 0
gdb_enabled = 0
server_port = 9999
end
 
 
/* MC SECTION
 
This section configures the memory controller
 
enabled = 0/1
whether memory controller is enabled
 
baseaddr = <hex_value>
address of first MC register
 
POC = <hex_value>
Power On Configuration register
*/
 
section mc
enabled = 0
baseaddr = 0xa0000000
POC = 0x00000008 /* Power on configuration register */
end
 
 
/* UART SECTION
 
This section configures UARTs
 
enabled = 0/1
whether uarts are enabled
 
nuarts = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
 
instance specific:
baseaddr = <hex_value>
address of first UART register for this device
 
rx_file = "<filename>"
filename, where to read data from
 
tx_file = "<filename>"
filename, where to write data to
 
irq = <value>
irq number for this device
 
16550 = 0/1
0, if this device is uart 16450 and 1, if it is 16550
 
jitter = <value>
in msecs... time to block, -1 to disable it
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section uart
enabled = 0
nuarts = 1
 
device 0
baseaddr = 0x80000000
irq = 2
rxfile = "/tmp/uart0.rx"
txfile = "/tmp/uart0.tx"
jitter = -1 /* async behaviour */
enddevice
end
 
 
/* DMA SECTION
 
This section configures DMAs
 
enabled = 0/1
whether DMAs are enabled
 
ndmas = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
 
instance specific:
baseaddr = <hex_value>
address of first DMA register for this device
 
irq = <value>
irq number for this device
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section dma
enabled = 0
ndmas = 1
 
device 0
baseaddr = 0x90000000
irq = 4
enddevice
end
 
 
/* ETHERNET SECTION
 
This section configures ethernets
 
enabled = 0/1
whether ethernets are enabled
 
nethernets = <value>
make specified number of instances, configure each
instance within device - enddevice construct.
 
instance specific:
baseaddr = <hex_value>
address of first ethernet register for this device
 
dma = <value>
which controller is this ethernet "connected" to
 
rx_channel = <value>
DMA channel used for RX
 
tx_channel = <value>
DMA channel used for TX
 
rx_file = "<filename>"
filename, where to read data from
 
tx_file = "<filename>"
filename, where to write data to
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section ethernet
enabled = 0
nethernets = 1
 
device 0
baseaddr = 0x88000000
dma = 0
tx_channel = 0
rx_channel = 1
rxfile = "/tmp/eth0.rx"
txfile = "/tmp/eth0.tx"
enddevice
end
 
/* TICK TIMER SECTION
 
This section configures tick timer
 
enabled = 0/1
whether tick timer is enabled
 
irq = <value>
irq number
*/
 
section tick
enabled = 0
irq = 3
end
/trunk/or1ksim/testbench/Makefile.am
23,6 → 23,7
# tests in this directory
OR1K_TESTS = basic cache cfg dmatest eth mmu except_test pic
IND_TESTS = exit cbasic local_global mul mycompress dhry functest mem_test
# inst_set_test
ACV_TESTS = acv_uart acv_gpio
MC_TESTS = mc_dram mc_ssram mc_async mc_sync
# Subdirectory tests
52,6 → 53,8
functest_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
mem_test_SOURCES = $(OR1K_SUPPORT_S) support.h mem_test.c
mem_test_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
inst_set_test_SOURCES = $(OR1K_SUPPORT_S) support.h inst_set_test.c
inst_set_test_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
###############################################
 
######### MC Tests ############################
69,12 → 72,12
 
####### Platform Dependent Tests - OR1K ########
basic_SOURCES = basic.S spr_defs.h
basic_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
basic_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
basic_LDADD =
cache_SOURCES = $(OR1K_SUPPORT_S) support.h cache.c
cache_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
cfg_SOURCES = cfg.S spr_defs.h
cfg_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
cfg_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
cfg_LDADD =
pic_SOURCES = $(OR1K_SUPPORT_S) support.h pic.c
pic_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
86,7 → 89,7
acv_uart_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
acv_gpio_SOURCES = $(OR1K_SUPPORT_S) support.h acv_gpio.c
acv_gpio_LDFLAGS = -T$(OR1K_SRCDIR)/default.ld
mmu_SOURCES = $(OR1K_SUPPORT_S) support.h mmu.c mmu_asm.S -DCOPY_SECTIONS
mmu_SOURCES = $(OR1K_SUPPORT_S) support.h mmu.c mmu_asm.S
mmu_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
except_test_SOURCES = except_test_s.S except_test.c spr_defs.h
except_test_LDFLAGS = -T$(OR1K_SRCDIR)/xess.ld
/trunk/or1ksim/sim-config.c
930,6 → 930,7
}
 
void ic_enabled () {
config.ic.enabled = tempL;
setsprbits (SPR_UPR, SPR_UPR_ICP, tempL & 1);
}
 
979,6 → 980,7
}
 
void dc_enabled () {
config.dc.enabled = tempL;
setsprbits (SPR_UPR, SPR_UPR_DCP, tempL & 1);
}
 

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