OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

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    from Rev 58 to Rev 59
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Rev 58 → Rev 59

/light8080/trunk/vhdl/test/light8080_tb0.vhdl
60,7 → 60,7
 
--------------------------------------------------------------------------------
 
-- Component Declaration for the Unit Under Test (UUT)
-- Component Declaration for the Unit Under Test (UUT)
component light8080
port (
addr_out : out std_logic_vector(15 downto 0);
372,24 → 372,24
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
 
 
-- clock: run clock until test is done
396,9 → 396,9
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
 
 
406,25 → 406,25
main_test:
process
begin
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
 
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
 
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
assert (done = '1')
report "Test timed out."
severity failure;
wait;
report "Test timed out."
severity failure;
wait;
end process main_test;
 
 
/light8080/trunk/vhdl/test/light8080_tb1.vhdl
381,24 → 381,24
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
 
 
-- clock: run clock until test is done
405,9 → 405,9
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
 
 
415,25 → 415,25
main_test:
process
begin
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
 
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
 
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
assert (done = '1')
report "Test timed out."
severity failure;
wait;
report "Test timed out."
severity failure;
wait;
end process main_test;
 
 
/light8080/trunk/vhdl/test/tb_template.vhdl
124,24 → 124,24
 
begin
 
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
-- Instantiate the Unit Under Test (UUT)
uut: light8080 PORT MAP(
clk => clk,
reset => reset,
vma => vma_o,
rd => rd_o,
wr => wr_o,
io => io_o,
fetch => fetch_o,
addr_out => addr_o,
data_in => data_i,
data_out => data_o,
intr => intr_i,
inte => inte_o,
inta => inta_o,
halt => halt_o
);
 
 
-- clock: run clock until test is done
148,9 → 148,9
clock:
process(done, clk)
begin
if done = '0' then
clk <= not clk after T/2;
end if;
if done = '0' then
clk <= not clk after T/2;
end if;
end process clock;
 
 
158,25 → 158,25
main_test:
process
begin
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
-- Assert reset for at least one full clk period
reset <= '1';
wait until clk = '1';
wait for T/2;
reset <= '0';
 
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
-- Remember to 'cut away' the preceding 3 clk semiperiods from
-- the wait statement...
wait for (MAX_SIM_LENGTH - T*1.5);
 
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
-- Maximum sim time elapsed, assume the program ran away and
-- stop the clk process asserting 'done' (which will stop the simulation)
done <= '1';
assert (done = '1')
report "Test timed out."
severity failure;
wait;
report "Test timed out."
severity failure;
wait;
end process main_test;
 
 

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