URL
https://opencores.org/ocsvn/openmsp430/openmsp430/trunk
Subversion Repositories openmsp430
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- This comparison shows the changes necessary to convert path
/
- from Rev 58 to Rev 59
- ↔ Reverse comparison
Rev 58 → Rev 59
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
133,7 → 133,7
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always @ (posedge mclk or posedge por) |
if (por) brk_ctl <= 5'h00; |
else if (brk_ctl_wr) brk_ctl <= dbg_din[4:0]; |
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]}; |
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl}; |
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146,7 → 146,8
reg [5:0] brk_stat; |
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wire brk_stat_wr = brk_reg_wr[BRK_STAT]; |
wire [5:0] brk_stat_set = {range_wr_set, range_rd_set, |
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE, |
range_rd_set & `HWBRK_RANGE, |
addr1_wr_set, addr1_rd_set, |
addr0_wr_set, addr0_rd_set}; |
wire [5:0] brk_stat_clr = ~dbg_din[5:0]; |
208,7 → 209,8
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wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE]; |
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE]; |
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & brk_ctl[`BRK_RANGE]; |
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & |
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; |
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reg fe_mb_en_buf; |
always @ (posedge mclk or posedge por) |
217,7 → 219,8
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & brk_ctl[`BRK_RANGE]; |
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & |
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; |
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// Detect accesses |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_defines.v
280,6 → 280,9
`define DBG_DCO_FREQ 20000000 |
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) |
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// Enable/Disable the hardware breakpoint RANGE mode |
`define HWBRK_RANGE 1'b0 |
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// Check configuration |
`ifdef DBG_EN |
`ifdef DBG_UART |
/openmsp430/trunk/fpga/xilinx_diligent_s3board/rtl/verilog/openmsp430/openMSP430_undefines.v
491,3 → 491,8
`ifdef DBG_UART_CNT |
`undef DBG_UART_CNT |
`endif |
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// Enable/Disable the hardware breakpoint RANGE mode |
`ifdef HWBRK_RANGE |
`undef HWBRK_RANGE |
`endif |
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/omsp_dbg_hwbrk.v
133,7 → 133,7
|
always @ (posedge mclk or posedge por) |
if (por) brk_ctl <= 5'h00; |
else if (brk_ctl_wr) brk_ctl <= dbg_din[4:0]; |
else if (brk_ctl_wr) brk_ctl <= {`HWBRK_RANGE & dbg_din[4], dbg_din[3:0]}; |
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wire [7:0] brk_ctl_full = {3'b000, brk_ctl}; |
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146,7 → 146,8
reg [5:0] brk_stat; |
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wire brk_stat_wr = brk_reg_wr[BRK_STAT]; |
wire [5:0] brk_stat_set = {range_wr_set, range_rd_set, |
wire [5:0] brk_stat_set = {range_wr_set & `HWBRK_RANGE, |
range_rd_set & `HWBRK_RANGE, |
addr1_wr_set, addr1_rd_set, |
addr0_wr_set, addr0_rd_set}; |
wire [5:0] brk_stat_clr = ~dbg_din[5:0]; |
208,7 → 209,8
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wire equ_d_addr0 = eu_mb_en & (eu_mab==brk_addr0) & ~brk_ctl[`BRK_RANGE]; |
wire equ_d_addr1 = eu_mb_en & (eu_mab==brk_addr1) & ~brk_ctl[`BRK_RANGE]; |
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & brk_ctl[`BRK_RANGE]; |
wire equ_d_range = eu_mb_en & ((eu_mab>=brk_addr0) & (eu_mab<=brk_addr1)) & |
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; |
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reg fe_mb_en_buf; |
always @ (posedge mclk or posedge por) |
217,7 → 219,8
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wire equ_i_addr0 = fe_mb_en_buf & (pc==brk_addr0) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_addr1 = fe_mb_en_buf & (pc==brk_addr1) & ~brk_ctl[`BRK_RANGE]; |
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & brk_ctl[`BRK_RANGE]; |
wire equ_i_range = fe_mb_en_buf & ((pc>=brk_addr0) & (pc<=brk_addr1)) & |
brk_ctl[`BRK_RANGE] & `HWBRK_RANGE; |
|
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// Detect accesses |
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_defines.v
280,6 → 280,9
`define DBG_DCO_FREQ 20000000 |
`define DBG_UART_CNT ((`DBG_DCO_FREQ/`DBG_UART_BAUD)-1) |
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// Enable/Disable the hardware breakpoint RANGE mode |
`define HWBRK_RANGE 1'b0 |
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// Check configuration |
`ifdef DBG_EN |
`ifdef DBG_UART |
/openmsp430/trunk/fpga/altera_de1_board/rtl/verilog/openmsp430/openMSP430_undefines.v
491,3 → 491,8
`ifdef DBG_UART_CNT |
`undef DBG_UART_CNT |
`endif |
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// Enable/Disable the hardware breakpoint RANGE mode |
`ifdef HWBRK_RANGE |
`undef HWBRK_RANGE |
`endif |