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Rev 58 → Rev 59

/trunk/rtl/verilog/fifo_control.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.4 2002/03/05 11:53:47 mihad
// Added some testcases, removed un-needed fifo signals
//
135,14 → 138,14
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
 
// FFs for registered empty and full flags
reg empty ;
reg full ;
wire empty ;
wire full ;
 
// almost_empty tag
reg almost_empty ;
wire almost_empty ;
 
// write allow wire - writes are allowed when fifo is not full
wire wallow = wenable_in && ~full ;
wire wallow = wenable_in && !full ;
 
// write allow output assignment
assign wallow_out = wallow ;
165,26 → 168,32
wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
end
 
reg stretched_empty ;
always@(posedge rclock_in or posedge clear)
begin
if(clear)
stretched_empty <= #`FF_DELAY 1'b1 ;
else
stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
end
wire stretched_empty ;
 
wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
 
meta_flop #(1) i_meta_flop_stretched_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (stretched_empty_flop_i),
.meta_q_o (stretched_empty)
) ;
 
// empty output is actual empty + 1 read clock cycle ( stretched empty )
assign empty_out = empty || stretched_empty ;
 
//rallow generation
assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
 
// rallow output assignment
assign rallow_out = rallow ;
 
// almost empty output assignment
assign almost_empty_out = almost_empty && ~empty && ~stretched_empty ;
assign almost_empty_out = almost_empty && !empty && !stretched_empty ;
 
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
333,13 → 342,16
//combinatorial input to Registered full FlipFlop
wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
 
always@(posedge wclock_in or posedge clear)
begin
if (clear)
full <= #`FF_DELAY 1'b0 ;
else
full <= #`FF_DELAY reg_full ;
end
meta_flop #(0) i_meta_flop_full
(
.rst_i (clear),
.clk_i (wclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_full),
.meta_q_o (full)
) ;
 
/*------------------------------------------------------------------------------------------------------------------------------
Registered empty control:
357,26 → 369,30
// combinatorial input for registered emty FlipFlop
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
 
always@(posedge rclock_in or posedge clear)
begin
if (clear)
empty <= #`FF_DELAY 1'b1 ;
else if (flush_in)
empty <= #`FF_DELAY 1'b1 ;
else
empty <= #`FF_DELAY reg_empty ;
end
// meta flop for empty signal instantiation - reset value 1, load value (flush) 1 etc..
meta_flop #(1) i_meta_flop_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (flush_in),
.ld_val_i (1'b1),
.en_i (1'b1),
.d_i (reg_empty),
.meta_q_o (empty)
) ;
 
// input for almost empty flip flop
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
always@(posedge clear or posedge rclock_in)
begin
if (clear)
almost_empty <= #`FF_DELAY 1'b0 ;
else if (flush_in)
almost_empty <= #`FF_DELAY 1'b0 ;
else
almost_empty <= #`FF_DELAY reg_almost_empty ;
end
 
meta_flop #(0) i_meta_flop_almost_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (flush_in),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_almost_empty),
.meta_q_o (almost_empty)
) ;
 
endmodule
/trunk/rtl/verilog/wbr_fifo_control.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.3 2002/02/01 15:25:13 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
122,7 → 125,7
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
 
// FF for registered empty flag
reg empty ;
wire empty ;
 
// write allow wire
wire wallow = wenable_in ;
146,20 → 149,26
end
 
// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
reg stretched_empty ;
always@(posedge rclock_in or posedge clear)
begin
if(clear)
stretched_empty <= #`FF_DELAY 1'b1 ;
else
stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
end
wire stretched_empty ;
 
wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
 
meta_flop #(1) i_meta_flop_stretched_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (stretched_empty_flop_i),
.meta_q_o (stretched_empty)
) ;
 
// empty output is actual empty + 1 read clock cycle ( stretched empty )
assign empty_out = empty || stretched_empty ;
 
//rallow generation
assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
 
// rallow output assignment
assign rallow_out = renable_in ;
278,14 → 287,15
// combinatorial input for registered emty FlipFlop
wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
 
always@(posedge rclock_in or posedge clear)
begin
if (clear)
empty <= #`FF_DELAY 1'b1 ;
else if (flush_in)
empty <= #1 1'b1 ; // when flushed, set empty to active
else
empty <= #`FF_DELAY reg_empty ;
end
meta_flop #(1) i_meta_flop_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (flush_in),
.ld_val_i (1'b1),
.en_i (1'b1),
.d_i (reg_empty),
.meta_q_o (empty)
) ;
 
endmodule
/trunk/rtl/verilog/wbw_wbr_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.3 2002/02/01 15:25:14 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
499,17 → 502,18
// synchronize transaction ready output to reading clock
// transaction ready is set when incoming transaction count is not equal to outgoing transaction count (what goes in must come out logic)
// transaction ready is cleared when whole transaction is pulled out of fifo (otherwise it could stay set for additional cycle and result in wrong op.)
reg wbw_transaction_ready_out ;
always@(posedge pci_clock_in or posedge wbw_clear)
begin
if (wbw_clear)
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
else
if ( out_count_en )
wbw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
else
wbw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
end
wire wbw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
 
meta_flop #(0) i_meta_flop_wbw_transaction_ready
(
.rst_i (wbw_clear),
.clk_i (pci_clock_in),
.ld_i (out_count_en),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (wbw_transaction_ready_flop_i),
.meta_q_o (wbw_transaction_ready_out)
) ;
 
endmodule
 
/trunk/rtl/verilog/pciw_pcir_fifos.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.4 2002/03/05 11:53:47 mihad
// Added some testcases, removed un-needed fifo signals
//
527,18 → 530,19
// transaction is ready when incoming transaction count is not equal to outgoing transaction count ( what comes in must come out )
// anytime last entry of transaction is pulled out of fifo, transaction ready flag is cleared for at least one clock to prevent wrong operation
// ( otherwise transaction ready would stay set for one additional clock even though next transaction was not ready )
reg pciw_transaction_ready_out ;
always@(posedge wb_clock_in or posedge pciw_clear)
begin
if (pciw_clear)
pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
else
if ( out_count_en )
pciw_transaction_ready_out <= #`FF_DELAY 1'b0 ;
else
pciw_transaction_ready_out <= #`FF_DELAY inGreyCount != outGreyCount ;
end
 
wire pciw_transaction_ready_flop_i = inGreyCount != outGreyCount ;
meta_flop #(0) i_meta_flop_transaction_ready
(
.rst_i (pciw_clear),
.clk_i (wb_clock_in),
.ld_i (out_count_en),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (pciw_transaction_ready_flop_i),
.meta_q_o (pciw_transaction_ready_out)
) ;
 
assign pcir_transaction_ready_out = 1'b0 ;
 
endmodule
/trunk/rtl/verilog/pciw_fifo_control.v
127,15 → 127,15
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
 
// FFs for registered empty and full flags
reg empty ;
reg full ;
wire empty ;
wire full ;
 
// registered almost_empty and almost_full flags
reg almost_empty ;
reg almost_full ;
wire almost_empty ;
wire almost_full ;
 
// write allow wire - writes are allowed when fifo is not full
wire wallow = wenable_in && ~full ;
wire wallow = wenable_in && !full ;
 
// write allow output assignment
assign wallow_out = wallow ;
147,7 → 147,7
assign full_out = full ;
 
// almost full output assignment
assign almost_full_out = almost_full && ~full ;
assign almost_full_out = almost_full && !full ;
 
// clear generation for FFs and registers
wire clear = reset_in /*|| flush_in*/ ; // flush not used for write fifo
161,26 → 161,32
wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
end
 
reg stretched_empty ;
always@(posedge rclock_in or posedge clear)
begin
if(clear)
stretched_empty <= #`FF_DELAY 1'b1 ;
else
stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
end
wire stretched_empty ;
 
wire stretched_empty_flop_i = empty && ~wclock_nempty_detect ;
 
meta_flop #(1) i_meta_flop_stretched_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (stretched_empty_flop_i),
.meta_q_o (stretched_empty)
) ;
 
// empty output is actual empty + 1 read clock cycle ( stretched empty )
assign empty_out = empty || stretched_empty ;
 
//rallow generation
assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
 
// rallow output assignment
assign rallow_out = rallow ;
 
// almost empty output assignment
assign almost_empty_out = almost_empty && ~empty && ~stretched_empty ;
assign almost_empty_out = almost_empty && !empty && !stretched_empty ;
 
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
// when FIFO is empty, this register provides actual read address, so first location can be read
355,7 → 361,6
registered two left is set on rising edge of write clock when three locations are left in fifo and another is written to it.
it's kept high until something is read/written from/to fifo.
--------------------------------------------------------------------------------------------------------------------------------*/
reg two_left_out ;
wire comb_full = wgrey_next == rgrey_addr ;
wire comb_almost_full = wgrey_addr == rgrey_minus2 ;
wire comb_two_left = wgrey_next == rgrey_minus2 ;
364,34 → 369,43
//combinatorial input to Registered full FlipFlop
wire reg_full = (wallow && comb_almost_full) || (comb_full) ;
 
always@(posedge wclock_in or posedge clear)
begin
if (clear)
full <= #`FF_DELAY 1'b0 ;
else
full <= #`FF_DELAY reg_full ;
end
meta_flop #(0) i_meta_flop_full
(
.rst_i (clear),
.clk_i (wclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_full),
.meta_q_o (full)
) ;
 
// input for almost full flip flop
wire reg_almost_full_in = wallow && comb_two_left || comb_almost_full ;
 
always@(posedge clear or posedge wclock_in)
begin
if (clear)
almost_full <= #`FF_DELAY 1'b0 ;
else
almost_full <= #`FF_DELAY reg_almost_full_in ;
end
meta_flop #(0) i_meta_flop_almost_full
(
.rst_i (clear),
.clk_i (wclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_almost_full_in),
.meta_q_o (almost_full)
) ;
 
wire reg_two_left_in = wallow && comb_three_left || comb_two_left ;
 
always@(posedge clear or posedge wclock_in)
begin
if (clear)
two_left_out <= #`FF_DELAY 1'b0 ;
else
two_left_out <= #`FF_DELAY reg_two_left_in ;
end
meta_flop #(0) i_meta_flop_two_left
(
.rst_i (clear),
.clk_i (wclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_two_left_in),
.meta_q_o (two_left_out)
) ;
 
/*------------------------------------------------------------------------------------------------------------------------------
Registered empty control:
410,22 → 424,29
// combinatorial input for registered emty FlipFlop
wire reg_empty = (rallow && comb_almost_empty) || comb_empty ;
 
always@(posedge rclock_in or posedge clear)
begin
if (clear)
empty <= #`FF_DELAY 1'b1 ;
else
empty <= #`FF_DELAY reg_empty ;
end
meta_flop #(1) i_meta_flop_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_empty),
.meta_q_o (empty)
) ;
 
// input for almost empty flip flop
wire reg_almost_empty = rallow && comb_two_used || comb_almost_empty ;
always@(posedge clear or posedge rclock_in)
begin
if (clear)
almost_empty <= #`FF_DELAY 1'b0 ;
else
almost_empty <= #`FF_DELAY reg_almost_empty ;
end
 
meta_flop #(0) i_meta_flop_almost_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_almost_empty),
.meta_q_o (almost_empty)
) ;
 
endmodule
/trunk/rtl/verilog/wbw_fifo_control.v
42,6 → 42,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/09/25 15:53:52 mihad
// Removed all logic from asynchronous reset network
//
// Revision 1.3 2002/02/01 15:25:14 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
129,17 → 132,17
wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
 
// FFs for registered empty and full flags
reg empty ;
reg full ;
wire empty ;
wire full ;
 
// almost_full tag
reg almost_full ;
wire almost_full ;
 
// write allow wire - writes are allowed when fifo is not full
wire wallow = wenable_in && ~full ;
wire wallow = wenable_in && !full ;
 
// write allow output assignment
assign wallow_out = wallow && ~full ;
assign wallow_out = wallow && !full ;
 
// read allow wire
wire rallow ;
148,7 → 151,7
assign full_out = full ;
 
// almost full output assignment
assign almost_full_out = almost_full && ~full ;
assign almost_full_out = almost_full && !full ;
 
// clear generation for FFs and registers
wire clear = reset_in /*|| flush_in*/ ; // flush not used
163,20 → 166,26
end
 
// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
reg stretched_empty ;
always@(posedge rclock_in or posedge clear)
begin
if(clear)
stretched_empty <= #`FF_DELAY 1'b1 ;
else
stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
end
wire stretched_empty ;
 
wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
 
meta_flop #(1) i_meta_flop_stretched_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (stretched_empty_flop_i),
.meta_q_o (stretched_empty)
) ;
 
// empty output is actual empty + 1 read clock cycle ( stretched empty )
assign empty_out = empty || stretched_empty ;
 
//rallow generation
assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
 
// rallow output assignment
assign rallow_out = rallow ;
326,24 → 335,30
//combinatorial input to Registered full FlipFlop
wire reg_full = wallow && (wgrey_next == rgrey_minus1) || (wgrey_next == rgrey_addr) ;
 
always@(posedge wclock_in or posedge clear)
begin
if (clear)
full <= #`FF_DELAY 1'b0 ;
else
full <= #`FF_DELAY reg_full ;
end
meta_flop #(0) i_meta_flop_full
(
.rst_i (clear),
.clk_i (wclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_full),
.meta_q_o (full)
) ;
 
// input for almost full latch
wire reg_almost_full_in = wallow && (wgrey_next == rgrey_minus2) || (wgrey_next == rgrey_minus1) ;
 
always@(posedge clear or posedge wclock_in)
begin
if (clear)
almost_full <= #`FF_DELAY 1'b0 ;
else
almost_full <= #`FF_DELAY reg_almost_full_in ;
end
meta_flop #(0) i_meta_flop_almost_full
(
.rst_i (clear),
.clk_i (wclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_almost_full_in),
.meta_q_o (almost_full)
) ;
 
/*------------------------------------------------------------------------------------------------------------------------------
Registered empty control:
359,12 → 374,15
wire comb_empty = (rgrey_addr == wgrey_addr) ;
wire reg_empty = renable_in && comb_almost_empty || comb_empty ;
 
always@(posedge rclock_in or posedge clear)
begin
if (clear)
empty <= #`FF_DELAY 1'b1 ;
else
empty <= #`FF_DELAY reg_empty ;
end
meta_flop #(1) i_meta_flop_empty
(
.rst_i (clear),
.clk_i (rclock_in),
.ld_i (1'b0),
.ld_val_i (1'b0),
.en_i (1'b1),
.d_i (reg_empty),
.meta_q_o (empty)
) ;
 
endmodule
/trunk/rtl/verilog/meta_flop.v
0,0 → 1,81
//////////////////////////////////////////////////////////////////////
//// ////
//// File name "meta_flop.v" ////
//// ////
//// This file is part of the "PCI bridge" project ////
//// http://www.opencores.org/cores/pci/ ////
//// ////
//// Author(s): ////
//// - Miha Dolenc (mihad@opencores.org) ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
// this module is just an ordinary flip-flop - used for identifying meta stable critical flip flops - similar to synchronizer flop
module meta_flop
(
rst_i,
clk_i,
ld_i,
ld_val_i,
en_i,
d_i,
meta_q_o
) ;
 
parameter p_reset_value = 0 ;
 
input rst_i,
clk_i,
ld_i,
ld_val_i,
en_i,
d_i ;
 
output meta_q_o ;
reg meta_q_o ;
 
always@(posedge rst_i or posedge clk_i)
begin
if (rst_i)
meta_q_o <= #1 p_reset_value ;
else if (ld_i)
meta_q_o <= #1 ld_val_i ;
else if (en_i)
meta_q_o <= #1 d_i ;
end
 
endmodule
/trunk/apps/crt/rtl/verilog/top.v
43,6 → 43,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/02/01 15:24:46 mihad
// Repaired a few bugs, updated specification, added test bench files and design document
//
// Revision 1.1.1.1 2001/10/02 15:33:33 mihad
// New project directory structure
//
54,8 → 57,6
module TOP
(
CLK,
AD,
CBE,
RST,
INTA,
REQ,
69,6 → 70,42
PAR,
PERR,
SERR,
AD0,
AD1,
AD2,
AD3,
AD4,
AD5,
AD6,
AD7,
AD8,
AD9,
AD10,
AD11,
AD12,
AD13,
AD14,
AD15,
AD16,
AD17,
AD18,
AD19,
AD20,
AD21,
AD22,
AD23,
AD24,
AD25,
AD26,
AD27,
AD28,
AD29,
AD30,
AD31,
CBE0,
CBE1,
CBE2,
CBE3,
 
/* CLK_I,
RST_I,
105,13 → 142,62
CRT_CLK,
HSYNC,
VSYNC,
RGB,
 
RGB4,
RGB5,
RGB6,
RGB7,
RGB8,
RGB9,
RGB10,
RGB11,
RGB12,
RGB13,
RGB14,
RGB15,
LED
);
 
input CLK ;
inout [31:0] AD ;
inout [3:0] CBE ;
inout AD0,
AD1,
AD2,
AD3,
AD4,
AD5,
AD6,
AD7,
AD8,
AD9,
AD10,
AD11,
AD12,
AD13,
AD14,
AD15,
AD16,
AD17,
AD18,
AD19,
AD20,
AD21,
AD22,
AD23,
AD24,
AD25,
AD26,
AD27,
AD28,
AD29,
AD30,
AD31 ;
 
inout CBE0,
CBE1,
CBE2,
CBE3 ;
 
inout RST ;
inout INTA ;
output REQ ;
130,7 → 216,18
// CRT outputs
output HSYNC ;
output VSYNC ;
output [15:4] RGB ;
output RGB4,
RGB5,
RGB6,
RGB7,
RGB8,
RGB9,
RGB10,
RGB11,
RGB12,
RGB13,
RGB14,
RGB15 ;
output LED ;
 
// WISHBONE system signals
170,9 → 267,50
wire [31:0] AD_en ;
 
 
wire [31:0] AD_in = AD ;
wire [31:0] AD_in =
{
AD31,
AD30,
AD29,
AD28,
AD27,
AD26,
AD25,
AD24,
AD23,
AD22,
AD21,
AD20,
AD19,
AD18,
AD17,
AD16,
AD15,
AD14,
AD13,
AD12,
AD11,
AD10,
AD9,
AD8,
AD7,
AD6,
AD5,
AD4,
AD3,
AD2,
AD1,
AD0
} ;
 
wire [3:0] CBE_in = CBE ;
wire [3:0] CBE_in =
{
CBE3,
CBE2,
CBE1,
CBE0
} ;
 
wire [3:0] CBE_out ;
wire [3:0] CBE_en ;
 
318,43 → 456,43
);
 
// PCI IO buffers instantiation
bufif0 AD_buf0 ( AD[0], AD_out[0], AD_en[0]) ;
bufif0 AD_buf1 ( AD[1], AD_out[1], AD_en[1]) ;
bufif0 AD_buf2 ( AD[2], AD_out[2], AD_en[2]) ;
bufif0 AD_buf3 ( AD[3], AD_out[3], AD_en[3]) ;
bufif0 AD_buf4 ( AD[4], AD_out[4], AD_en[4]) ;
bufif0 AD_buf5 ( AD[5], AD_out[5], AD_en[5]) ;
bufif0 AD_buf6 ( AD[6], AD_out[6], AD_en[6]) ;
bufif0 AD_buf7 ( AD[7], AD_out[7], AD_en[7]) ;
bufif0 AD_buf8 ( AD[8], AD_out[8], AD_en[8]) ;
bufif0 AD_buf9 ( AD[9], AD_out[9], AD_en[9]) ;
bufif0 AD_buf10 ( AD[10], AD_out[10],AD_en[10] ) ;
bufif0 AD_buf11 ( AD[11], AD_out[11],AD_en[11] ) ;
bufif0 AD_buf12 ( AD[12], AD_out[12],AD_en[12] ) ;
bufif0 AD_buf13 ( AD[13], AD_out[13],AD_en[13] ) ;
bufif0 AD_buf14 ( AD[14], AD_out[14],AD_en[14] ) ;
bufif0 AD_buf15 ( AD[15], AD_out[15],AD_en[15] ) ;
bufif0 AD_buf16 ( AD[16], AD_out[16],AD_en[16] ) ;
bufif0 AD_buf17 ( AD[17], AD_out[17],AD_en[17] ) ;
bufif0 AD_buf18 ( AD[18], AD_out[18],AD_en[18] ) ;
bufif0 AD_buf19 ( AD[19], AD_out[19],AD_en[19] ) ;
bufif0 AD_buf20 ( AD[20], AD_out[20],AD_en[20] ) ;
bufif0 AD_buf21 ( AD[21], AD_out[21],AD_en[21] ) ;
bufif0 AD_buf22 ( AD[22], AD_out[22],AD_en[22] ) ;
bufif0 AD_buf23 ( AD[23], AD_out[23],AD_en[23] ) ;
bufif0 AD_buf24 ( AD[24], AD_out[24],AD_en[24] ) ;
bufif0 AD_buf25 ( AD[25], AD_out[25],AD_en[25] ) ;
bufif0 AD_buf26 ( AD[26], AD_out[26],AD_en[26] ) ;
bufif0 AD_buf27 ( AD[27], AD_out[27],AD_en[27] ) ;
bufif0 AD_buf28 ( AD[28], AD_out[28],AD_en[28] ) ;
bufif0 AD_buf29 ( AD[29], AD_out[29],AD_en[29] ) ;
bufif0 AD_buf30 ( AD[30], AD_out[30],AD_en[30] ) ;
bufif0 AD_buf31 ( AD[31], AD_out[31],AD_en[31] ) ;
bufif0 AD_buf0 ( AD0, AD_out[0], AD_en[0]) ;
bufif0 AD_buf1 ( AD1, AD_out[1], AD_en[1]) ;
bufif0 AD_buf2 ( AD2, AD_out[2], AD_en[2]) ;
bufif0 AD_buf3 ( AD3, AD_out[3], AD_en[3]) ;
bufif0 AD_buf4 ( AD4, AD_out[4], AD_en[4]) ;
bufif0 AD_buf5 ( AD5, AD_out[5], AD_en[5]) ;
bufif0 AD_buf6 ( AD6, AD_out[6], AD_en[6]) ;
bufif0 AD_buf7 ( AD7, AD_out[7], AD_en[7]) ;
bufif0 AD_buf8 ( AD8, AD_out[8], AD_en[8]) ;
bufif0 AD_buf9 ( AD9, AD_out[9], AD_en[9]) ;
bufif0 AD_buf10 ( AD10, AD_out[10],AD_en[10] ) ;
bufif0 AD_buf11 ( AD11, AD_out[11],AD_en[11] ) ;
bufif0 AD_buf12 ( AD12, AD_out[12],AD_en[12] ) ;
bufif0 AD_buf13 ( AD13, AD_out[13],AD_en[13] ) ;
bufif0 AD_buf14 ( AD14, AD_out[14],AD_en[14] ) ;
bufif0 AD_buf15 ( AD15, AD_out[15],AD_en[15] ) ;
bufif0 AD_buf16 ( AD16, AD_out[16],AD_en[16] ) ;
bufif0 AD_buf17 ( AD17, AD_out[17],AD_en[17] ) ;
bufif0 AD_buf18 ( AD18, AD_out[18],AD_en[18] ) ;
bufif0 AD_buf19 ( AD19, AD_out[19],AD_en[19] ) ;
bufif0 AD_buf20 ( AD20, AD_out[20],AD_en[20] ) ;
bufif0 AD_buf21 ( AD21, AD_out[21],AD_en[21] ) ;
bufif0 AD_buf22 ( AD22, AD_out[22],AD_en[22] ) ;
bufif0 AD_buf23 ( AD23, AD_out[23],AD_en[23] ) ;
bufif0 AD_buf24 ( AD24, AD_out[24],AD_en[24] ) ;
bufif0 AD_buf25 ( AD25, AD_out[25],AD_en[25] ) ;
bufif0 AD_buf26 ( AD26, AD_out[26],AD_en[26] ) ;
bufif0 AD_buf27 ( AD27, AD_out[27],AD_en[27] ) ;
bufif0 AD_buf28 ( AD28, AD_out[28],AD_en[28] ) ;
bufif0 AD_buf29 ( AD29, AD_out[29],AD_en[29] ) ;
bufif0 AD_buf30 ( AD30, AD_out[30],AD_en[30] ) ;
bufif0 AD_buf31 ( AD31, AD_out[31],AD_en[31] ) ;
 
bufif0 CBE_buf0 ( CBE[0], CBE_out[0], CBE_en[0] ) ;
bufif0 CBE_buf1 ( CBE[1], CBE_out[1], CBE_en[1] ) ;
bufif0 CBE_buf2 ( CBE[2], CBE_out[2], CBE_en[2] ) ;
bufif0 CBE_buf3 ( CBE[3], CBE_out[3], CBE_en[3] ) ;
bufif0 CBE_buf0 ( CBE0, CBE_out[0], CBE_en[0] ) ;
bufif0 CBE_buf1 ( CBE1, CBE_out[1], CBE_en[1] ) ;
bufif0 CBE_buf2 ( CBE2, CBE_out[2], CBE_en[2] ) ;
bufif0 CBE_buf3 ( CBE3, CBE_out[3], CBE_en[3] ) ;
 
bufif0 FRAME_buf ( FRAME, FRAME_out, FRAME_en ) ;
bufif0 IRDY_buf ( IRDY, IRDY_out, IRDY_en ) ;
421,7 → 559,7
.rgb_in(rgb_int[15:4]),
.hsync_out(HSYNC),
.vsync_out(VSYNC),
.rgb_out(RGB)
.rgb_out({RGB15, RGB14, RGB13, RGB12, RGB11, RGB10, RGB9, RGB8, RGB7, RGB6, RGB5, RGB4})
) ;
 
endmodule
endmodule
/trunk/apps/crt/syn/ucf/pci_crt.ucf
299,92 → 299,94
# INST gbuf1 LOC=SSW
#
# #
 
NET "CLK" IOSTANDARD = PCI33_5 ;
NET "CLK" TNM_NET = "CLK";
NET "CRT_CLK" TNM_NET = "CRT_CLK";
 
TIMESPEC "TS_CLK" = PERIOD "CLK" 30 ns HIGH 50 %;
TIMESPEC "TS_CRT_CLK" = PERIOD "CRT_CLK" 44 ns HIGH 50 %;
TIMESPEC "TS_CLK_2_CRT_CLK" = FROM : "CLK" : TO : "CRT_CLK" : 30 ;
TIMESPEC "TS_CRT_CLK_2_CLK" = FROM : "CRT_CLK" : TO : "CLK" : 30 ;
TIMESPEC "TS_CLK_2_CRT_CLK" = FROM : "CLK" : TO : "CRT_CLK" : 5 ;
TIMESPEC "TS_CRT_CLK_2_CLK" = FROM : "CRT_CLK" : TO : "CLK" : 5 ;
 
INST "AD<0>.PAD" TNM = "PCI_AD";
INST "AD<1>.PAD" TNM = "PCI_AD";
INST "AD<2>.PAD" TNM = "PCI_AD";
INST "AD<3>.PAD" TNM = "PCI_AD";
INST "AD<4>.PAD" TNM = "PCI_AD";
INST "AD<5>.PAD" TNM = "PCI_AD";
INST "AD<6>.PAD" TNM = "PCI_AD";
INST "AD<7>.PAD" TNM = "PCI_AD";
INST "AD<8>.PAD" TNM = "PCI_AD";
INST "AD<9>.PAD" TNM = "PCI_AD";
INST "AD<10>.PAD" TNM = "PCI_AD";
INST "AD<11>.PAD" TNM = "PCI_AD";
INST "AD<12>.PAD" TNM = "PCI_AD";
INST "AD<13>.PAD" TNM = "PCI_AD";
INST "AD<14>.PAD" TNM = "PCI_AD";
INST "AD<15>.PAD" TNM = "PCI_AD";
INST "AD<16>.PAD" TNM = "PCI_AD";
INST "AD<17>.PAD" TNM = "PCI_AD";
INST "AD<18>.PAD" TNM = "PCI_AD";
INST "AD<19>.PAD" TNM = "PCI_AD";
INST "AD<20>.PAD" TNM = "PCI_AD";
INST "AD<21>.PAD" TNM = "PCI_AD";
INST "AD<22>.PAD" TNM = "PCI_AD";
INST "AD<23>.PAD" TNM = "PCI_AD";
INST "AD<24>.PAD" TNM = "PCI_AD";
INST "AD<25>.PAD" TNM = "PCI_AD";
INST "AD<26>.PAD" TNM = "PCI_AD";
INST "AD<27>.PAD" TNM = "PCI_AD";
INST "AD<28>.PAD" TNM = "PCI_AD";
INST "AD<29>.PAD" TNM = "PCI_AD";
INST "AD<30>.PAD" TNM = "PCI_AD";
INST "AD<31>.PAD" TNM = "PCI_AD";
INST "AD0.PAD" TNM = "PCI_AD";
INST "AD1.PAD" TNM = "PCI_AD";
INST "AD2.PAD" TNM = "PCI_AD";
INST "AD3.PAD" TNM = "PCI_AD";
INST "AD4.PAD" TNM = "PCI_AD";
INST "AD5.PAD" TNM = "PCI_AD";
INST "AD6.PAD" TNM = "PCI_AD";
INST "AD7.PAD" TNM = "PCI_AD";
INST "AD8.PAD" TNM = "PCI_AD";
INST "AD9.PAD" TNM = "PCI_AD";
INST "AD10.PAD" TNM = "PCI_AD";
INST "AD11.PAD" TNM = "PCI_AD";
INST "AD12.PAD" TNM = "PCI_AD";
INST "AD13.PAD" TNM = "PCI_AD";
INST "AD14.PAD" TNM = "PCI_AD";
INST "AD15.PAD" TNM = "PCI_AD";
INST "AD16.PAD" TNM = "PCI_AD";
INST "AD17.PAD" TNM = "PCI_AD";
INST "AD18.PAD" TNM = "PCI_AD";
INST "AD19.PAD" TNM = "PCI_AD";
INST "AD20.PAD" TNM = "PCI_AD";
INST "AD21.PAD" TNM = "PCI_AD";
INST "AD22.PAD" TNM = "PCI_AD";
INST "AD23.PAD" TNM = "PCI_AD";
INST "AD24.PAD" TNM = "PCI_AD";
INST "AD25.PAD" TNM = "PCI_AD";
INST "AD26.PAD" TNM = "PCI_AD";
INST "AD27.PAD" TNM = "PCI_AD";
INST "AD28.PAD" TNM = "PCI_AD";
INST "AD29.PAD" TNM = "PCI_AD";
INST "AD30.PAD" TNM = "PCI_AD";
INST "AD31.PAD" TNM = "PCI_AD";
TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK";
TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK";
NET "AD<0>" IOSTANDARD = PCI33_5;
NET "AD<1>" IOSTANDARD = PCI33_5;
NET "AD<2>" IOSTANDARD = PCI33_5;
NET "AD<3>" IOSTANDARD = PCI33_5;
NET "AD<4>" IOSTANDARD = PCI33_5;
NET "AD<5>" IOSTANDARD = PCI33_5;
NET "AD<6>" IOSTANDARD = PCI33_5;
NET "AD<7>" IOSTANDARD = PCI33_5;
NET "AD<8>" IOSTANDARD = PCI33_5;
NET "AD<9>" IOSTANDARD = PCI33_5;
NET "AD<10>" IOSTANDARD = PCI33_5;
NET "AD<11>" IOSTANDARD = PCI33_5;
NET "AD<12>" IOSTANDARD = PCI33_5;
NET "AD<13>" IOSTANDARD = PCI33_5;
NET "AD<14>" IOSTANDARD = PCI33_5;
NET "AD<15>" IOSTANDARD = PCI33_5;
NET "AD<16>" IOSTANDARD = PCI33_5;
NET "AD<17>" IOSTANDARD = PCI33_5;
NET "AD<18>" IOSTANDARD = PCI33_5;
NET "AD<19>" IOSTANDARD = PCI33_5;
NET "AD<20>" IOSTANDARD = PCI33_5;
NET "AD<21>" IOSTANDARD = PCI33_5;
NET "AD<22>" IOSTANDARD = PCI33_5;
NET "AD<23>" IOSTANDARD = PCI33_5;
NET "AD<24>" IOSTANDARD = PCI33_5;
NET "AD<25>" IOSTANDARD = PCI33_5;
NET "AD<26>" IOSTANDARD = PCI33_5;
NET "AD<27>" IOSTANDARD = PCI33_5;
NET "AD<28>" IOSTANDARD = PCI33_5;
NET "AD<29>" IOSTANDARD = PCI33_5;
NET "AD<30>" IOSTANDARD = PCI33_5;
NET "AD<31>" IOSTANDARD = PCI33_5;
INST "CBE<0>.PAD" TNM = "PCI_CBE";
INST "CBE<1>.PAD" TNM = "PCI_CBE";
INST "CBE<2>.PAD" TNM = "PCI_CBE";
INST "CBE<3>.PAD" TNM = "PCI_CBE";
NET "AD0" IOSTANDARD = PCI33_5;
NET "AD1" IOSTANDARD = PCI33_5;
NET "AD2" IOSTANDARD = PCI33_5;
NET "AD3" IOSTANDARD = PCI33_5;
NET "AD4" IOSTANDARD = PCI33_5;
NET "AD5" IOSTANDARD = PCI33_5;
NET "AD6" IOSTANDARD = PCI33_5;
NET "AD7" IOSTANDARD = PCI33_5;
NET "AD8" IOSTANDARD = PCI33_5;
NET "AD9" IOSTANDARD = PCI33_5;
NET "AD10" IOSTANDARD = PCI33_5;
NET "AD11" IOSTANDARD = PCI33_5;
NET "AD12" IOSTANDARD = PCI33_5;
NET "AD13" IOSTANDARD = PCI33_5;
NET "AD14" IOSTANDARD = PCI33_5;
NET "AD15" IOSTANDARD = PCI33_5;
NET "AD16" IOSTANDARD = PCI33_5;
NET "AD17" IOSTANDARD = PCI33_5;
NET "AD18" IOSTANDARD = PCI33_5;
NET "AD19" IOSTANDARD = PCI33_5;
NET "AD20" IOSTANDARD = PCI33_5;
NET "AD21" IOSTANDARD = PCI33_5;
NET "AD22" IOSTANDARD = PCI33_5;
NET "AD23" IOSTANDARD = PCI33_5;
NET "AD24" IOSTANDARD = PCI33_5;
NET "AD25" IOSTANDARD = PCI33_5;
NET "AD26" IOSTANDARD = PCI33_5;
NET "AD27" IOSTANDARD = PCI33_5;
NET "AD28" IOSTANDARD = PCI33_5;
NET "AD29" IOSTANDARD = PCI33_5;
NET "AD30" IOSTANDARD = PCI33_5;
NET "AD31" IOSTANDARD = PCI33_5;
INST "CBE0.PAD" TNM = "PCI_CBE";
INST "CBE1.PAD" TNM = "PCI_CBE";
INST "CBE2.PAD" TNM = "PCI_CBE";
INST "CBE3.PAD" TNM = "PCI_CBE";
 
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK";
TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK";
 
NET "CBE<0>" IOSTANDARD = PCI33_5;
NET "CBE<1>" IOSTANDARD = PCI33_5;
NET "CBE<2>" IOSTANDARD = PCI33_5;
NET "CBE<3>" IOSTANDARD = PCI33_5;
NET "CBE0" IOSTANDARD = PCI33_5;
NET "CBE1" IOSTANDARD = PCI33_5;
NET "CBE2" IOSTANDARD = PCI33_5;
NET "CBE3" IOSTANDARD = PCI33_5;
 
#INST "DEVSEL.PAD" TNM = "PCI_CTRL" ;
 
458,6 → 460,9
 
#INST "TRDY.PAD" TNM = "PCI_CTRL" ;
 
NET "IDSEL" OFFSET = IN 7ns BEFORE "CLK" ;
NET "IDSEL" IOSTANDARD = PCI33_5 ;
 
##################################################################################
# Pin locations
##################################################################################
466,25 → 471,25
NET "RST" LOC = "P199" ;
NET "GNT" LOC = "P200" ;
NET "REQ" LOC = "P201" ;
NET "AD<31>" LOC = "P203" ;
NET "AD<30>" LOC = "P204" ;
NET "AD<29>" LOC = "P205" ;
NET "AD<28>" LOC = "P206" ;
NET "AD<27>" LOC = "P3" ;
NET "AD<26>" LOC = "P4" ;
NET "AD<25>" LOC = "P5" ;
NET "AD<24>" LOC = "P6" ;
NET "CBE<3>" LOC = "P8" ;
NET "AD31" LOC = "P203" ;
NET "AD30" LOC = "P204" ;
NET "AD29" LOC = "P205" ;
NET "AD28" LOC = "P206" ;
NET "AD27" LOC = "P3" ;
NET "AD26" LOC = "P4" ;
NET "AD25" LOC = "P5" ;
NET "AD24" LOC = "P6" ;
NET "CBE3" LOC = "P8" ;
NET "IDSEL" LOC = "P9" ;
NET "AD<23>" LOC = "P10" ;
NET "AD<22>" LOC = "P14" ;
NET "AD<21>" LOC = "P15" ;
NET "AD<20>" LOC = "P16" ;
NET "AD<19>" LOC = "P17" ;
NET "AD<18>" LOC = "P18" ;
NET "AD<17>" LOC = "P20" ;
NET "AD<16>" LOC = "P21" ;
NET "CBE<2>" LOC = "P22" ;
NET "AD23" LOC = "P10" ;
NET "AD22" LOC = "P14" ;
NET "AD21" LOC = "P15" ;
NET "AD20" LOC = "P16" ;
NET "AD19" LOC = "P17" ;
NET "AD18" LOC = "P18" ;
NET "AD17" LOC = "P20" ;
NET "AD16" LOC = "P21" ;
NET "CBE2" LOC = "P22" ;
NET "FRAME" LOC = "P23" ;
NET "IRDY" LOC = "P24" ;
#
494,24 → 499,24
NET "PERR" LOC = "P31" ;
NET "SERR" LOC = "P33" ;
NET "PAR" LOC = "P34" ;
NET "CBE<1>" LOC = "P35" ;
NET "AD<15>" LOC = "P36" ;
NET "AD<14>" LOC = "P37" ;
NET "AD<13>" LOC = "P41" ;
NET "AD<12>" LOC = "P42" ;
NET "AD<11>" LOC = "P43" ;
NET "AD<10>" LOC = "P45" ;
NET "AD<9>" LOC = "P46" ;
NET "AD<8>" LOC = "P47" ;
NET "CBE<0>" LOC = "P48" ;
NET "AD<7>" LOC = "P49" ;
NET "AD<6>" LOC = "P57" ;
NET "AD<5>" LOC = "P58" ;
NET "AD<4>" LOC = "P59" ;
NET "AD<3>" LOC = "P61" ;
NET "AD<2>" LOC = "P62" ;
NET "AD<1>" LOC = "P63" ;
NET "AD<0>" LOC = "P67" ;
NET "CBE1" LOC = "P35" ;
NET "AD15" LOC = "P36" ;
NET "AD14" LOC = "P37" ;
NET "AD13" LOC = "P41" ;
NET "AD12" LOC = "P42" ;
NET "AD11" LOC = "P43" ;
NET "AD10" LOC = "P45" ;
NET "AD9" LOC = "P46" ;
NET "AD8" LOC = "P47" ;
NET "CBE0" LOC = "P48" ;
NET "AD7" LOC = "P49" ;
NET "AD6" LOC = "P57" ;
NET "AD5" LOC = "P58" ;
NET "AD4" LOC = "P59" ;
NET "AD3" LOC = "P61" ;
NET "AD2" LOC = "P62" ;
NET "AD1" LOC = "P63" ;
NET "AD0" LOC = "P67" ;
 
#
#NET "HSYNC" LOC = "P188" ;
524,18 → 529,18
NET "CRT_CLK" LOC = "P182" ;
NET "HSYNC" LOC = "P83" ;
NET "VSYNC" LOC = "P84" ;
NET "RGB<4>" LOC = "P166" ;
NET "RGB<5>" LOC = "P167" ;
NET "RGB<6>" LOC = "P168" ;
NET "RGB<7>" LOC = "P172" ;
NET "RGB<8>" LOC = "P173" ;
NET "RGB<9>" LOC = "P174" ;
NET "RGB<10>" LOC = "P175" ;
NET "RGB<11>" LOC = "P176" ;
NET "RGB<12>" LOC = "P178" ;
NET "RGB<13>" LOC = "P179" ;
NET "RGB<14>" LOC = "P180" ;
NET "RGB<15>" LOC = "P181" ;
NET "RGB4" LOC = "P166" ;
NET "RGB5" LOC = "P167" ;
NET "RGB6" LOC = "P168" ;
NET "RGB7" LOC = "P172" ;
NET "RGB8" LOC = "P173" ;
NET "RGB9" LOC = "P174" ;
NET "RGB10" LOC = "P175" ;
NET "RGB11" LOC = "P176" ;
NET "RGB12" LOC = "P178" ;
NET "RGB13" LOC = "P179" ;
NET "RGB14" LOC = "P180" ;
NET "RGB15" LOC = "P181" ;
NET "LED" LOC = "P202" ;
#
 
/trunk/apps/crt/syn/synplify/pci_crt.ucf
0,0 → 1,378
##############################################
# BASIC UCF SYNTAX EXAMPLES V2.1.6 #
##############################################
#
# The "#" symbol is a comment character. To use this sample file, find the
# specification necessary, remove the comment character (#) from the beginning
# of the line, and modify the line (if necessary) to fit your design.
#
# TIMING SPECIFICATIONS
#
# Timing specifications can be applied to the entire device (global) or to
# specific groups in your design (called "time groups'). The time groups are
# declared in two basic ways.
#
# Method 1: Based on a net name, where 'my_net' is a net that touches all the
# logic to be grouped in to 'logic_grp'. Example:
#NET my_net TNM_NET = logic_grp ;
#
# Method 2: Group using the key word 'TIMEGRP' and declare using the names of
# logic in your design. Example:
#TIMEGRP group_name = FFS ("U1/*");
# creates a group called 'group_name' for all flip-flops within
# the hierarchical block called U1. Wildcards are valid.
#
# Grouping is very important because it lets you tell the software which parts
# of a design run at which speeds. For the majority of the designs with only
# one clock, use simple global constraints.
#
# The type of grouping constraint you use can vary depending on the synthesis
# tools you are using. Foundation Express does better with Method 2.
#
#
############################################################
# Internal to the device clock speed specifications - Tsys #
############################################################
#
# data _________ /^^^^^\ _________ out
# ----------| D Q |-----{ LOGIC } -----| D Q |------
# | | \vvvvv/ | |
# ---|> CLK | ---|> CLK |
# clock | --------- | ---------
# ------------------------------------
#
# ---------------
# Single Clock
# ---------------
#
# ----------------
# PERIOD TIME-SPEC
# ----------------
# The PERIOD spec. covers all timing paths that start or end at a
# register, latch, or synchronous RAM which are clocked by the reference
# net (excluding pad destinations). Also covered is the setup
# requirement of the synchronous element relative to other elements
# (ex. flip flops, pads, etc...).
# NOTE: The default unit for time is nanoseconds.
#
#NET clock PERIOD = 50ns ;
#
# -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
# FROM:TO style timespecs can be used to constrain paths between time
# groups. NOTE: Keywords: RAMS, FFS, PADS, and LATCHES are predefined
# time groups used to specify all elements of each type in a design.
#TIMEGRP RFFS = RISING FFS ("*"); // creates a rising group called RFFS
#TIMEGRP FFFS = FALLING FFS ("*"); // creates a falling group called FFFS
#TIMESPEC TSF2F = FROM : FFS : TO : FFS : 50 ns; // Flip-flips with the same edge
#TIMESPEC TSR2F = FROM : RFFS : TO : FFFS : 25 ns; // rising edge to falling edge
#TIMESPEC TSF2R = FROM : FFFS : TO : RFFS : 25 ns; // falling edge to rising edge
#
# ---------------
# Multiple Clocks
# ---------------
# Requires a combination of the 'Period' and 'FROM:TO' type time specifications
#NET clock1 TNM_NET = clk1_grp ;
#NET clock2 TNM_NET = clk2_grp ;
#
#TIMESPEC TS_clk1 = PERIOD : clk1_grp : 50 ;
#TIMESPEC TS_clk2 = PERIOD : clk2_grp : 30 ;
#TIMESPEC TS_ck1_2_ck2 = FROM : clk1_grp : TO : clk2_grp : 50 ;
#TIMESPEC TS_ck2_2_ck1 = FROM : clk2_grp : TO : clk1_grp : 30 ;
#
#
############################################################
# CLOCK TO OUT specifications - Tco #
############################################################
#
# from _________ /^^^^^\ --------\
# ----------| D Q |-----{ LOGIC } -----| Pad >
# PLD | | \vvvvv/ --------/
# ---|> CLK |
# clock | ---------
# --------
#
# ----------------
# OFFSET TIME-SPEC
# ----------------
# To automatically include clock buffer/routing delay in your
# clock-to-out timing specifications, use OFFSET constraints .
# For an output where the maximum clock-to-out (Tco) is 25 ns:
#
#NET out_net_name OFFSET = OUT 25 AFTER clock_net_name ;
#
# -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSF2P = FROM : FFS : TO : PADS : 25 ns;
# Note that FROM: FFS : TO: PADS constraints start the delay analysis
# at the flip flop itself, and not the clock input pin. The recommended
# method to create a clock-to-out constraint is to use an OFFSET constraint.
#
#
############################################################
# Pad to Flip-Flop speed specifications - Tsu #
############################################################
#
# ------\ /^^^^^\ _________ into PLD
# |pad >-------{ LOGIC } -----| D Q |------
# ------/ \vvvvv/ | |
# ---|> CLK |
# clock | ---------
# ----------------------------
#
# ----------------
# OFFSET TIME-SPEC
# ----------------
# To automatically account for clock delay in your input setup timing
# specifications, use OFFSET constraints.
# For an input where the maximum setup time is 25 ns:
#NET in_net_name OFFSET = IN 25 BEFORE clock_net_name ;
#
# -OR-
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSP2F = FROM : PADS : TO : FFS : 25 ns;
# Note that FROM: PADS : TO: FFS constraints do not take into account any
# delay for the clock path. The recommended method to create an input
# setup time constraint is to use an OFFSET constraint.
#
#
############################################################
# Pad to Pad speed specifications - Tpd #
############################################################
#
# ------\ /^^^^^\ -------\
# |pad >-------{ LOGIC } -----| pad >
# ------/ \vvvvv/ -------/
#
# ------------------
# FROM:TO TIME-SPECs
# ------------------
#TIMESPEC TSP2P = FROM : PADS : TO : PADS : 125 ns;
#
#
############################################################
# Other timing specifications #
############################################################
#
# -------------
# TIMING IGNORE
# -------------
# If you can ignore timing of paths, use Timing Ignore (TIG). NOTE: The
# "*" character is a wild card, which can be used for bus names. A "?"
# character can be used to wild-card one character.
# Ignore timing of net reset_n:
#NET : reset_n : TIG ;
#
# Ignore data_reg(7:0) net in instance mux_mem:
#NET : mux_mem/data_reg* : TIG ;
#
# Ignore data_reg(7:0) net in instance mux_mem as related to a TIMESPEC
# named TS01 only:
#NET : mux_mem/data_reg* : TIG = TS01 ;
#
# Ignore data1_sig and data2_sig nets:
#NET : data?_sig : TIG ;
#
# ---------------
# PATH EXCEPTIONS
# ---------------
# If your design has outputs that can be slower than others, you can
# create specific timespecs similar to this example for output nets
# named out_data(7:0) and irq_n:
#TIMEGRP slow_outs = PADS(out_data* : irq_n) ;
#TIMEGRP fast_outs = PADS : EXCEPT : slow_outs ;
#TIMESPEC TS08 = FROM : FFS : TO : fast_outs : 22 ;
#TIMESPEC TS09 = FROM : FFS : TO : slow_outs : 75 ;
#
# If you have multi-cycle FF to FF paths, you can create a time group
# using either the TIMEGRP or TNM statements.
#
# WARNING: Many VHDL/Verilog synthesizers do not predictably name flip
# flop Q output nets. Most synthesizers do assign predictable instance
# names to flip flops, however.
#
# TIMEGRP example:
#TIMEGRP slowffs = FFS(inst_path/ff_q_output_net1* :
#inst_path/ff_q_output_net2*);
#
# TNM attached to instance example:
#INST inst_path/ff_instance_name1_reg* TNM = slowffs ;
#INST inst_path/ff_instance_name2_reg* TNM = slowffs ;
#
# If a FF clock-enable is used on all flip flops of a multi-cycle path,
# you can attach TNM to the clock enable net. NOTE: TNM attached to a
# net "forward traces" to any FF, LATCH, RAM, or PAD attached to the
# net.
#NET ff_clock_enable_net TNM = slowffs ;
#
# Example of using "slowffs" timegroup, in a FROM:TO timespec, with
# either of the three timegroup methods shown above:
#TIMESPEC TS10 = FROM : slowffs : TO : FFS : 100 ;
#
# Constrain the skew or delay associate with a net.
#NET any_net_name MAXSKEW = 7 ;
#NET any_net_name MAXDELAY = 20 ns;
#
#
# Constraint priority in your .ucf file is as follows:
#
# highest 1. Timing Ignore (TIG)
# 2. FROM : THRU : TO specs
# 3. FROM : TO specs
# lowest 4. PERIOD specs
#
# See the on-line "Library Reference Guide" document for
# additional timespec features and more information.
#
#
############################################################
# #
# LOCATION and ATTRIBUTE SPECIFICATIONS #
# #
############################################################
# Pin and CLB location locking constraints #
############################################################
#
# -----------------------
# Assign an IO pin number
# -----------------------
#INST io_buf_instance_name LOC = P110 ;
#NET io_net_name LOC = P111 ;
#
# -----------------------
# Assign a signal to a range of I/O pins
# -----------------------
#NET "signal_name" LOC=P32, P33, P34;
#
# -----------------------
# Place a logic element(called a BEL) in a specific CLB location.
# BEL = FF, LUT, RAM, etc...
# -----------------------
#INST instance_path/BEL_inst_name LOC = CLB_R17C36 ;
#
# -----------------------
# Place CLB in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1/U2/reg<0> LOC=clb_r1c1:clb_r5c7;
#
# -----------------------
# Place hierarchical logic block in rectangular area from CLB R1C1 to CLB R5C7
# -----------------------
#INST /U1* LOC=clb_r1c1:clb_r5c7;
#
# -----------------------
# Prohibit IO pin P26 or CLBR5C3 from being used:
# -----------------------
#CONFIG PROHIBIT = P26 ;
#CONFIG PROHIBIT = CLB_R5C3 ;
# Config Prohibit is very important for forcing the software to not use critical
# configuration pins like INIT or DOUT on the FPGA. The Mode pins and JTAG
# Pins require a special pad so they will not be available to this constraint
#
# -----------------------
# Assign an OBUF to be FAST or SLOW:
# -----------------------
#INST obuf_instance_name FAST ;
#INST obuf_instance_name SLOW ;
#
# -----------------------
# FPGAs only: IOB input Flip-flop delay specification
# -----------------------
# Declare an IOB input FF delay (default = MAXDELAY).
# NOTE: MEDDELAY/NODELAY can be attached to a CLB FF that is pushed
# into an IOB by the "map -pr i" option.
#INST input_ff_instance_name MEDDELAY ;
#INST input_ff_instance_name NODELAY ;
#
# -----------------------
# Assign Global Clock Buffers Lower Left Right Side
# -----------------------
# INST gbuf1 LOC=SSW
#
# #
 
 
# define a group of metastable Flip-Flops
INST *sync_data_out* TNM = sync_ffs ;
TIMESPEC TS_sync_flops = FROM : sync_ffs : TO : FFS : 15 ;
INST *meta_q_o* TNM = meta_ffs ;
TIMESPEC TS_meta_flops = FROM : meta_ffs : TO : FFS : 15 ;
 
NET CLK TNM_NET = CLK_GRP ;
NET CRT_CLK TNM_NET = CRT_CLK_GRP ;
 
TIMESPEC TS_CLK_2_CRT_CLK = FROM : CLK_GRP : TO : CRT_CLK_GRP : 15 ;
TIMESPEC TS_CRT_CLK_2_CLK = FROM : CRT_CLK_GRP : TO : CLK_GRP : 15 ;
 
NET "AD0" IOSTANDARD = PCI33_5;
NET "AD1" IOSTANDARD = PCI33_5;
NET "AD2" IOSTANDARD = PCI33_5;
NET "AD3" IOSTANDARD = PCI33_5;
NET "AD4" IOSTANDARD = PCI33_5;
NET "AD5" IOSTANDARD = PCI33_5;
NET "AD6" IOSTANDARD = PCI33_5;
NET "AD7" IOSTANDARD = PCI33_5;
NET "AD8" IOSTANDARD = PCI33_5;
NET "AD9" IOSTANDARD = PCI33_5;
NET "AD10" IOSTANDARD = PCI33_5;
NET "AD11" IOSTANDARD = PCI33_5;
NET "AD12" IOSTANDARD = PCI33_5;
NET "AD13" IOSTANDARD = PCI33_5;
NET "AD14" IOSTANDARD = PCI33_5;
NET "AD15" IOSTANDARD = PCI33_5;
NET "AD16" IOSTANDARD = PCI33_5;
NET "AD17" IOSTANDARD = PCI33_5;
NET "AD18" IOSTANDARD = PCI33_5;
NET "AD19" IOSTANDARD = PCI33_5;
NET "AD20" IOSTANDARD = PCI33_5;
NET "AD21" IOSTANDARD = PCI33_5;
NET "AD22" IOSTANDARD = PCI33_5;
NET "AD23" IOSTANDARD = PCI33_5;
NET "AD24" IOSTANDARD = PCI33_5;
NET "AD25" IOSTANDARD = PCI33_5;
NET "AD26" IOSTANDARD = PCI33_5;
NET "AD27" IOSTANDARD = PCI33_5;
NET "AD28" IOSTANDARD = PCI33_5;
NET "AD29" IOSTANDARD = PCI33_5;
NET "AD30" IOSTANDARD = PCI33_5;
NET "AD31" IOSTANDARD = PCI33_5;
 
NET "CLK" IOSTANDARD = PCI33_5;
 
NET "CBE0" IOSTANDARD = PCI33_5;
NET "CBE1" IOSTANDARD = PCI33_5;
NET "CBE2" IOSTANDARD = PCI33_5;
NET "CBE3" IOSTANDARD = PCI33_5;
 
NET "DEVSEL" IOSTANDARD = PCI33_5;
 
NET "FRAME" IOSTANDARD = PCI33_5;
 
NET "GNT" IOSTANDARD = PCI33_5;
NET "RST" IOSTANDARD = PCI33_5;
NET "INTA" IOSTANDARD = PCI33_5;
 
NET "IRDY" IOSTANDARD = PCI33_5;
 
NET "PAR" IOSTANDARD = PCI33_5;
 
NET "PERR" IOSTANDARD = PCI33_5;
 
NET "REQ" IOSTANDARD = PCI33_5;
 
NET "SERR" IOSTANDARD = PCI33_5;
 
NET "STOP" IOSTANDARD = PCI33_5;
 
NET "TRDY" IOSTANDARD = PCI33_5;
 
NET "IDSEL" IOSTANDARD = PCI33_5;
trunk/apps/crt/syn/synplify/pci_crt.ucf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/apps/crt/syn/synplify/pci_crt.sdc =================================================================== --- trunk/apps/crt/syn/synplify/pci_crt.sdc (nonexistent) +++ trunk/apps/crt/syn/synplify/pci_crt.sdc (revision 59) @@ -0,0 +1,259 @@ +# Synplicity, Inc. constraint file +# /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.sdc +# Written on Fri Sep 27 11:42:06 2002 +# by Amplify, Amplify 3.1 Scope Editor + +# +# Clocks +# +define_clock -name {CLK} -period 30.000 -clockgroup pci_clkgrp +define_clock -name {CRT_CLK} -period 44.000 -clockgroup crt_clkgrp + +# +# Inputs/Outputs +# +define_input_delay {DEVSEL} 23.00 -ref CLK:r +define_input_delay {TRDY} 23.00 -ref CLK:r +define_input_delay {STOP} 23.00 -ref CLK:r +define_input_delay {IDSEL} 23.00 -ref CLK:r +define_input_delay {FRAME} 23.00 -ref CLK:r +define_input_delay {IRDY} 23.00 -ref CLK:r +define_input_delay {GNT} 20.00 -ref CLK:r +define_input_delay {PAR} 23.00 -ref CLK:r +define_input_delay {PERR} 23.00 -ref CLK:r +define_input_delay {AD0} 23.00 -ref CLK:r +define_input_delay {AD1} 23.00 -ref CLK:r +define_input_delay {AD2} 23.00 -ref CLK:r +define_input_delay {AD3} 23.00 -ref CLK:r +define_input_delay {AD4} 23.00 -ref CLK:r +define_input_delay {AD5} 23.00 -ref CLK:r +define_input_delay {AD6} 23.00 -ref CLK:r +define_input_delay {AD7} 23.00 -ref CLK:r +define_input_delay {AD8} 23.00 -ref CLK:r +define_input_delay {AD9} 23.00 -ref CLK:r +define_input_delay {AD10} 23.00 -ref CLK:r +define_input_delay {AD11} 23.00 -ref CLK:r +define_input_delay {AD12} 23.00 -ref CLK:r +define_input_delay {AD13} 23.00 -ref CLK:r +define_input_delay {AD14} 23.00 -ref CLK:r +define_input_delay {AD15} 23.00 -ref CLK:r +define_input_delay {AD16} 23.00 -ref CLK:r +define_input_delay {AD17} 23.00 -ref CLK:r +define_input_delay {AD18} 23.00 -ref CLK:r +define_input_delay {AD19} 23.00 -ref CLK:r +define_input_delay {AD20} 23.00 -ref CLK:r +define_input_delay {AD21} 23.00 -ref CLK:r +define_input_delay {AD22} 23.00 -ref CLK:r +define_input_delay {AD23} 23.00 -ref CLK:r +define_input_delay {AD24} 23.00 -ref CLK:r +define_input_delay {AD25} 23.00 -ref CLK:r +define_input_delay {AD26} 23.00 -ref CLK:r +define_input_delay {AD27} 23.00 -ref CLK:r +define_input_delay {AD28} 23.00 -ref CLK:r +define_input_delay {AD29} 23.00 -ref CLK:r +define_input_delay {AD30} 23.00 -ref CLK:r +define_input_delay {AD31} 23.00 -ref CLK:r +define_input_delay {CBE0} 23.00 -ref CLK:r +define_input_delay {CBE1} 23.00 -ref CLK:r +define_input_delay {CBE2} 23.00 -ref CLK:r +define_input_delay {CBE3} 23.00 -ref CLK:r +define_output_delay {AD0} 19.00 -ref CLK:r +define_output_delay {AD1} 19.00 -ref CLK:r +define_output_delay {AD2} 19.00 -ref CLK:r +define_output_delay {AD3} 19.00 -ref CLK:r +define_output_delay {AD4} 19.00 -ref CLK:r +define_output_delay {AD5} 19.00 -ref CLK:r +define_output_delay {AD6} 19.00 -ref CLK:r +define_output_delay {AD7} 19.00 -ref CLK:r +define_output_delay {AD8} 19.00 -ref CLK:r +define_output_delay {AD9} 19.00 -ref CLK:r +define_output_delay {AD10} 19.00 -ref CLK:r +define_output_delay {AD11} 19.00 -ref CLK:r +define_output_delay {AD12} 19.00 -ref CLK:r +define_output_delay {AD13} 19.00 -ref CLK:r +define_output_delay {AD14} 19.00 -ref CLK:r +define_output_delay {AD15} 19.00 -ref CLK:r +define_output_delay {AD16} 19.00 -ref CLK:r +define_output_delay {AD17} 19.00 -ref CLK:r +define_output_delay {AD18} 19.00 -ref CLK:r +define_output_delay {AD19} 19.00 -ref CLK:r +define_output_delay {AD20} 19.00 -ref CLK:r +define_output_delay {AD21} 19.00 -ref CLK:r +define_output_delay {AD22} 19.00 -ref CLK:r +define_output_delay {AD23} 19.00 -ref CLK:r +define_output_delay {AD24} 19.00 -ref CLK:r +define_output_delay {AD25} 19.00 -ref CLK:r +define_output_delay {AD26} 19.00 -ref CLK:r +define_output_delay {AD27} 19.00 -ref CLK:r +define_output_delay {AD28} 19.00 -ref CLK:r +define_output_delay {AD29} 19.00 -ref CLK:r +define_output_delay {AD30} 19.00 -ref CLK:r +define_output_delay {AD31} 19.00 -ref CLK:r +define_output_delay {CBE0} 19.00 -ref CLK:r +define_output_delay {CBE1} 19.00 -ref CLK:r +define_output_delay {CBE2} 19.00 -ref CLK:r +define_output_delay {CBE3} 19.00 -ref CLK:r +define_output_delay {DEVSEL} 19.00 -ref CLK:r +define_output_delay {TRDY} 19.00 -ref CLK:r +define_output_delay {STOP} 19.00 -ref CLK:r +define_output_delay {FRAME} 19.00 -ref CLK:r +define_output_delay {IRDY} 19.00 -ref CLK:r +define_output_delay {REQ} 18.00 -ref CLK:r +define_output_delay {PAR} 19.00 -ref CLK:r +define_output_delay {PERR} 19.00 -ref CLK:r +define_output_delay {SERR} 19.00 -ref CLK:r +define_input_delay -default 10.00 -ref CRT_CLK:r +define_output_delay -default 10.00 -ref CRT_CLK:r + +# +# Registers +# +#define_reg_output_delay {bridge.pci_target_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.cache_lsize_to_wb_bits_sync.sync_data_out[6:0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.command_bit_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.int_pin_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.isr_bit0_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.isr_bit2_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.pci_err_cs_bits_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_isr_2.clear_delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_isr_2.delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_pci_err_cs_8.clear_delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.configuration.sync_pci_err_cs_8.delete_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.req_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.rty_exp_back_prop_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.del_sync.rty_exp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.almost_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.full_out} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pcir_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.almost_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.almost_full} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.full_out} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_fifo_ctrl.two_left_out} -route 15.00 +#define_reg_output_delay {bridge.pci_target_unit.fifos.pciw_transaction_ready_out} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.comp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.done_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.req_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.rty_exp_back_prop_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.del_sync.rty_exp_sync.sync_data_out[0]} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbr_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbr_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.almost_full} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.full_out} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_fifo_ctrl.stretched_empty} -route 15.00 +#define_reg_output_delay {bridge.wishbone_slave_unit.fifos.wbw_transaction_ready_out} -route 15.00 + +define_reg_output_delay {*sync_data_out*} -route 20.00 +define_reg_output_delay {*meta_q_o*} -route 20.00 + +# +# Multicycle Path +# + +# +# False Path +# + +# +# Attributes +# +define_attribute {CLK} xc_loc {P185} +define_attribute {INTA} xc_loc {P195} +define_attribute {RST} xc_loc {P199} +define_attribute {GNT} xc_loc {P200} +define_attribute {REQ} xc_loc {P201} +define_attribute {AD31} xc_loc {P203} +define_attribute {AD30} xc_loc {P204} +define_attribute {AD29} xc_loc {P205} +define_attribute {AD28} xc_loc {P206} +define_attribute {AD27} xc_loc {P3} +define_attribute {AD26} xc_loc {P4} +define_attribute {AD25} xc_loc {P5} +define_attribute {AD24} xc_loc {P6} +define_attribute {CBE3} xc_loc {P8} +define_attribute {IDSEL} xc_loc {P9} +define_attribute {AD23} xc_loc {P10} +define_attribute {AD22} xc_loc {P14} +define_attribute {AD21} xc_loc {P15} +define_attribute {AD20} xc_loc {P16} +define_attribute {AD19} xc_loc {P17} +define_attribute {AD18} xc_loc {P18} +define_attribute {AD17} xc_loc {P20} +define_attribute {AD16} xc_loc {P21} +define_attribute {CBE2} xc_loc {P22} +define_attribute {FRAME} xc_loc {P23} +define_attribute {IRDY} xc_loc {P24} +define_attribute {TRDY} xc_loc {P27} +define_attribute {DEVSEL} xc_loc {P29} +define_attribute {STOP} xc_loc {P30} +define_attribute {PERR} xc_loc {P31} +define_attribute {SERR} xc_loc {P33} +define_attribute {PAR} xc_loc {P34} +define_attribute {CBE1} xc_loc {P35} +define_attribute {AD15} xc_loc {P36} +define_attribute {AD14} xc_loc {P37} +define_attribute {AD13} xc_loc {P41} +define_attribute {AD12} xc_loc {P42} +define_attribute {AD11} xc_loc {P43} +define_attribute {AD10} xc_loc {P45} +define_attribute {AD9} xc_loc {P46} +define_attribute {AD8} xc_loc {P47} +define_attribute {CBE0} xc_loc {P48} +define_attribute {AD7} xc_loc {P49} +define_attribute {AD6} xc_loc {P57} +define_attribute {AD5} xc_loc {P58} +define_attribute {AD4} xc_loc {P59} +define_attribute {AD3} xc_loc {P61} +define_attribute {AD2} xc_loc {P62} +define_attribute {AD1} xc_loc {P63} +define_attribute {AD0} xc_loc {P67} +define_attribute {CRT_CLK} xc_loc {P182} +define_attribute {HSYNC} xc_loc {P83} +define_attribute {VSYNC} xc_loc {P84} +define_attribute {RGB4} xc_loc {P166} +define_attribute {RGB5} xc_loc {P167} +define_attribute {RGB6} xc_loc {P168} +define_attribute {RGB7} xc_loc {P172} +define_attribute {RGB8} xc_loc {P173} +define_attribute {RGB9} xc_loc {P174} +define_attribute {RGB10} xc_loc {P175} +define_attribute {RGB11} xc_loc {P176} +define_attribute {RGB12} xc_loc {P178} +define_attribute {RGB13} xc_loc {P179} +define_attribute {RGB14} xc_loc {P180} +define_attribute {RGB15} xc_loc {P181} +define_attribute {LED} xc_loc {P202} +define_global_attribute syn_useioff {1} +define_attribute {v:work.CBE_EN_CRIT} syn_hier {hard} +define_attribute {v:work.FRAME_CRIT} syn_hier {hard} +define_attribute {v:work.FRAME_EN_CRIT} syn_hier {hard} +define_attribute {v:work.FRAME_LOAD_CRIT} syn_hier {hard} +define_attribute {v:work.IRDY_OUT_CRIT} syn_hier {hard} +define_attribute {v:work.MAS_AD_EN_CRIT} syn_hier {hard} +define_attribute {v:work.MAS_AD_LOAD_CRIT} syn_hier {hard} +define_attribute {v:work.MAS_CH_STATE_CRIT} syn_hier {hard} +define_attribute {v:work.PAR_CRIT} syn_hier {hard} +define_attribute {v:work.PCI_IO_MUX_AD_EN_CRIT} syn_hier {hard} +define_attribute {v:work.PCI_IO_MUX_AD_LOAD_CRIT} syn_hier {hard} +define_attribute {v:work.PCI_TARGET32_CLK_EN} syn_hier {hard} +define_attribute {v:work.PCI_TARGET32_DEVS_CRIT} syn_hier {hard} +define_attribute {v:work.PCI_TARGET32_STOP_CRIT} syn_hier {hard} +define_attribute {v:work.PCI_TARGET32_TRDY_CRIT} syn_hier {hard} +define_attribute {v:work.PERR_CRIT} syn_hier {hard} +define_attribute {v:work.PERR_EN_CRIT} syn_hier {hard} +define_attribute {v:work.SERR_CRIT} syn_hier {hard} +define_attribute {v:work.SERR_EN_CRIT} syn_hier {hard} + +# +# Other Constraints +# + +# +# Order of waveforms +#
trunk/apps/crt/syn/synplify/pci_crt.sdc Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/apps/crt/syn/synplify/pci_crt.prj =================================================================== --- trunk/apps/crt/syn/synplify/pci_crt.prj (nonexistent) +++ trunk/apps/crt/syn/synplify/pci_crt.prj (revision 59) @@ -0,0 +1,125 @@ +#-- Synplicity, Inc. +#-- Version Amplify 3.1 +#-- Project file /shared/projects/pci/mihad/pci/apps/crt/syn/synplify/pci_crt.prj +#-- Written on Fri Sep 27 16:20:50 2002 + + +#add_file options +add_file -verilog "$LIB/xilinx/virtex.v" +add_file -verilog "../../../../rtl/verilog/async_reset_flop.v" +add_file -verilog "../../../../rtl/verilog/cbe_en_crit.v" +add_file -verilog "../../../../rtl/verilog/conf_cyc_addr_dec.v" +add_file -verilog "../../../../rtl/verilog/conf_space.v" +add_file -verilog "../../../../rtl/verilog/cur_out_reg.v" +add_file -verilog "../../../../rtl/verilog/decoder.v" +add_file -verilog "../../../../rtl/verilog/delayed_sync.v" +add_file -verilog "../../../../rtl/verilog/delayed_write_reg.v" +add_file -verilog "../../../../rtl/verilog/fifo_control.v" +add_file -verilog "../../../../rtl/verilog/frame_crit.v" +add_file -verilog "../../../../rtl/verilog/frame_en_crit.v" +add_file -verilog "../../../../rtl/verilog/frame_load_crit.v" +add_file -verilog "../../../../rtl/verilog/irdy_out_crit.v" +add_file -verilog "../../../../rtl/verilog/mas_ad_en_crit.v" +add_file -verilog "../../../../rtl/verilog/mas_ad_load_crit.v" +add_file -verilog "../../../../rtl/verilog/mas_ch_state_crit.v" +add_file -verilog "../../../../rtl/verilog/out_reg.v" +add_file -verilog "../../../../rtl/verilog/par_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_bridge32.v" +add_file -verilog "../../../../rtl/verilog/pci_decoder.v" +add_file -verilog "../../../../rtl/verilog/pci_in_reg.v" +add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_en_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_io_mux_ad_load_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_io_mux.v" +add_file -verilog "../../../../rtl/verilog/pci_master32_sm_if.v" +add_file -verilog "../../../../rtl/verilog/pci_master32_sm.v" +add_file -verilog "../../../../rtl/verilog/pci_parity_check.v" +add_file -verilog "../../../../rtl/verilog/pci_ram_16x40d.v" +add_file -verilog "../../../../rtl/verilog/pci_rst_int.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_clk_en.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_devs_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_interface.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_sm.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_stop_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_target32_trdy_crit.v" +add_file -verilog "../../../../rtl/verilog/pci_target_unit.v" +add_file -verilog "../../../../rtl/verilog/pci_tpram.v" +add_file -verilog "../../../../rtl/verilog/pciw_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/pciw_pcir_fifos.v" +add_file -verilog "../../../../rtl/verilog/perr_crit.v" +add_file -verilog "../../../../rtl/verilog/perr_en_crit.v" +add_file -verilog "../../../../rtl/verilog/serr_crit.v" +add_file -verilog "../../../../rtl/verilog/serr_en_crit.v" +add_file -verilog "../../../../rtl/verilog/synchronizer_flop.v" +add_file -verilog "../../../../rtl/verilog/sync_module.v" +add_file -verilog "../../../../rtl/verilog/wb_addr_mux.v" +add_file -verilog "../../../../rtl/verilog/wb_master.v" +add_file -verilog "../../../../rtl/verilog/wbr_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/wb_slave_unit.v" +add_file -verilog "../../../../rtl/verilog/wb_slave.v" +add_file -verilog "../../../../rtl/verilog/wb_tpram.v" +add_file -verilog "../../../../rtl/verilog/wbw_fifo_control.v" +add_file -verilog "../../../../rtl/verilog/wbw_wbr_fifos.v" +add_file -verilog "../../rtl/verilog/crtc_iob.v" +add_file -verilog "../../rtl/verilog/ssvga_crtc.v" +add_file -verilog "../../rtl/verilog/ssvga_fifo.v" +add_file -verilog "../../rtl/verilog/ssvga_top.v" +add_file -verilog "../../rtl/verilog/ssvga_wbm_if.v" +add_file -verilog "../../rtl/verilog/ssvga_wbs_if.v" +add_file -constraint "pci_crt.sdc" +add_file -verilog "/shared/projects/pci/mihad/pci/rtl/verilog/meta_flop.v" +add_file -verilog "../../rtl/verilog/top.v" + +#reporting options + + +#implementation: "rev_1" +impl -add rev_1 + +#device options +set_option -technology SPARTAN2 +set_option -part XC2S150 +set_option -package PQ208 +set_option -speed_grade -5 + +#compilation/mapping options +set_option -default_enum_encoding default +set_option -symbolic_fsm_compiler 0 +set_option -resource_sharing 0 +set_option -use_fsm_explorer 0 + +#map options +set_option -frequency 50.000 +set_option -fanout_limit 50 +set_option -disable_io_insertion 0 +set_option -pipe 0 +set_option -fixgatedclocks 0 +set_option -retiming 0 +set_option -modular 0 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "rev_1/top.edf" + +#implementation attributes +set_option -vlog_std v95 +set_option -compiler_compatible 0 +set_option -random_floorplan 0 +set_option -include_path "../../../../rtl/verilog/;../../rtl/verilog/" + +#netlist optimizer options +set_option -enable_nfilter 0 +set_option -feedthrough 1 +set_option -constant_prop 1 +set_option -level_hierarchy 0 + +#physical constraint options +set_option -floorplan "" +set_option -nfilter_user_path "" +set_option -pin_assignment "" +impl -active "rev_1"
trunk/apps/crt/syn/synplify/pci_crt.prj Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/rtl_sim/bin/rtl_file_list.lst =================================================================== --- trunk/sim/rtl_sim/bin/rtl_file_list.lst (revision 58) +++ trunk/sim/rtl_sim/bin/rtl_file_list.lst (revision 59) @@ -51,3 +51,4 @@ ../../../rtl/verilog/pci_rst_int.v ../../../rtl/verilog/sync_module.v ../../../rtl/verilog/wb_tpram.v +../../../rtl/verilog/meta_flop.v

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