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https://opencores.org/ocsvn/thor/thor/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 58 to Rev 59
- ↔ Reverse comparison
Rev 58 → Rev 59
/thor/trunk/FT64v5/rtl/common/FT64_cache.v
26,9 → 26,6
// |
`define TRUE 1'b1 |
`define FALSE 1'b0 |
`define BRK 6'd0 |
`define FLT_EXF 9'd497 |
`define FLT_IBE 9'd509 |
|
// ----------------------------------------------------------------------------- |
// Small, 64 line cache memory (2kiB) made from distributed RAM. Access is |
37,7 → 34,7
|
module FT64_L1_icache_mem(rst, clk, wr, en, lineno, i, o, ov, invall, invline); |
parameter pLines = 64; |
parameter pLineWidth = 288; |
parameter pLineWidth = 290; |
localparam pLNMSB = pLines==128 ? 6 : 5; |
input rst; |
input clk; |
50,6 → 47,8
input invall; |
input invline; |
|
integer n; |
|
(* ram_style="distributed" *) |
reg [pLineWidth-1:0] mem [0:pLines-1]; |
reg [pLines-1:0] valid0; |
62,6 → 61,11
reg [pLines-1:0] valid7; |
reg [pLines-1:0] valid8; |
|
initial begin |
for (n = 0; n < pLines; n = n + 1) |
mem[n][289:288] <= 2'b00; |
end |
|
always @(posedge clk) |
if (wr & en[0]) mem[lineno][31:0] <= i[31:0]; |
always @(posedge clk) |
79,7 → 83,7
always @(posedge clk) |
if (wr & en[7]) mem[lineno][255:224] <= i[255:224]; |
always @(posedge clk) |
if (wr & en[8]) mem[lineno][287:256] <= i[287:256]; |
if (wr & en[8]) mem[lineno][289:256] <= i[289:256]; |
always @(posedge clk) |
if (rst) begin |
valid0 <= 64'd0; |
306,7 → 310,7
// ----------------------------------------------------------------------------- |
// ----------------------------------------------------------------------------- |
|
module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, hit, invall, invline); |
module FT64_L1_icache(rst, clk, nxt, wr, wr_ack, en, wadr, adr, i, o, fault, hit, invall, invline); |
parameter pSize = 2; |
parameter CAMTAGS = 1'b0; // 32 way |
parameter FOURWAY = 1'b1; |
320,14 → 324,15
input [8:0] en; |
input [37:0] adr; |
input [37:0] wadr; |
input [287:0] i; |
input [289:0] i; |
output reg [47:0] o; |
output reg [1:0] fault; |
output hit; |
input invall; |
input invline; |
|
wire [287:0] ic; |
reg [287:0] i1, i2; |
wire [289:0] ic; |
reg [289:0] i1, i2; |
wire [8:0] lv; // line valid |
wire [pLNMSB:0] lineno; |
wire [pLNMSB:0] wlineno; |
343,7 → 348,7
always @(posedge clk) |
wr2 <= wr1; |
always @(posedge clk) |
i1 <= i[287:0]; |
i1 <= i[289:0]; |
always @(posedge clk) |
i2 <= i1; |
always @(posedge clk) |
421,6 → 426,8
//always @(radr or ic0 or ic1) |
always @(adr or ic) |
o <= ic >> {adr[4:1],4'h0}; |
always @* |
fault <= ic[289:288]; |
|
assign wr_ack = wr2; |
|
429,13 → 436,14
// ----------------------------------------------------------------------------- |
// ----------------------------------------------------------------------------- |
|
module FT64_L2_icache_mem(clk, wr, lineno, sel, i, o, ov, invall, invline); |
module FT64_L2_icache_mem(clk, wr, lineno, sel, i, fault, o, ov, invall, invline); |
input clk; |
input wr; |
input [8:0] lineno; |
input [2:0] sel; |
input [63:0] i; |
output [287:0] o; |
input [1:0] fault; |
output [289:0] o; |
output reg ov; |
input invall; |
input invline; |
446,6 → 454,7
reg [63:0] mem2 [0:511]; |
reg [63:0] mem3 [0:511]; |
reg [31:0] mem4 [0:511]; |
reg [1:0] memf [0:511]; |
reg [511:0] valid; |
reg [8:0] rrcl; |
|
453,8 → 462,10
wire [8:0] cache_line; |
integer n; |
initial begin |
for (n = 0; n < 512; n = n + 1) |
for (n = 0; n < 512; n = n + 1) begin |
valid[n] <= 0; |
memf[n] <= 2'b00; |
end |
end |
|
always @(posedge clk) |
466,11 → 477,11
begin |
if (wr) begin |
case(sel[2:0]) |
3'd0: mem0[lineno] <= i; |
3'd1: mem1[lineno] <= i; |
3'd2: mem2[lineno] <= i; |
3'd3: mem3[lineno] <= i; |
3'd4: mem4[lineno] <= i[31:0]; |
3'd0: begin mem0[lineno] <= i; memf[lineno] <= fault; end |
3'd1: begin mem1[lineno] <= i; memf[lineno] <= memf[lineno] | fault; end |
3'd2: begin mem2[lineno] <= i; memf[lineno] <= memf[lineno] | fault; end |
3'd3: begin mem3[lineno] <= i; memf[lineno] <= memf[lineno] | fault; end |
3'd4: begin mem4[lineno] <= i[31:0]; memf[lineno] <= memf[lineno] | fault; end |
endcase |
end |
end |
481,7 → 492,7
always @(posedge clk) |
ov <= valid[lineno]; |
|
assign o = {mem4[rrcl],mem3[rrcl],mem2[rrcl],mem1[rrcl],mem0[rrcl]}; |
assign o = {memf[rrcl],mem4[rrcl],mem3[rrcl],mem2[rrcl],mem1[rrcl],mem0[rrcl]}; |
|
endmodule |
|
508,7 → 519,7
input exv_i; |
input [63:0] i; |
input err_i; |
output [287:0] o; |
output [289:0] o; |
output hit; |
input invall; |
input invline; |
519,6 → 530,7
reg wr1,wr2; |
reg [2:0] sel1,sel2; |
reg [63:0] i1,i2; |
reg [1:0] f1, f2; |
reg [37:0] last_adr; |
|
// Must update the cache memory on the cycle after a write to the tag memmory. |
533,7 → 545,11
sel2 <= sel1; |
always @(posedge clk) |
last_adr <= adr; |
|
always @(posedge clk) |
f1 <= {err_i,exv_i}; |
always @(posedge clk) |
f2 <= f1; |
|
reg [3:0] rdackx; |
always @(posedge clk) |
if (rst) |
547,10 → 563,8
|
assign rd_ack = rdackx[3] & ~(last_adr!=adr || wr || wr1 || wr2); |
|
// An exception is forced to be stored in the event of an error loading the |
// the instruction line. |
always @(posedge clk) |
i1 <= err_i ? {2{15'd0,1'b0,`FLT_IBE,2'b00,`BRK}} : exv_i ? {2{15'd0,1'b0,`FLT_EXF,2'b00,`BRK}} : i; |
i1 <= i; |
always @(posedge clk) |
i2 <= i1; |
|
564,6 → 578,7
.lineno(lineno), |
.sel(sel2), |
.i(i2), |
.fault(f2), |
.o(o), |
.ov(lv), |
.invall(invall), |
/thor/trunk/FT64v5/rtl/common/FT64_config.vh
22,12 → 22,15
// |
// ============================================================================ |
// |
// The following line is to enable simulation versions of some modules. |
// Comment out for synthesis. |
`define SIM 1'b1 |
|
//`define SUPPORT_SMT 1'b1 |
`define SUPPORT_VECTOR 1'b1 |
//`define SUPPORT_VECTOR 1'b1 |
//`define SUPPORT_DCI 1'b1 // dynamically compressed instructions |
//`define DEBUG_LOGIC 1'b1 |
`define L1_ICACHE_SIZE 4 // 2 or 4 for 2 or 4 kB |
`define L1_ICACHE_SIZE 2 // 2 or 4 for 2 or 4 kB |
|
// One way to tweak the size of the core a little bit is to limit the number |
// of address bits processed. The test system for instance has only 512MB of |
55,15 → 58,15
// register file, the number of ports on the instruction cache, and how |
// many entries are contained in the fetch buffers. It also indirectly |
// affects how many instructions are queued. |
`define WAYS 2 // number of ways parallel (1-3 3 not working yet) |
`define NUM_IDU 2 // number of instruction decode units (1-3) |
`define NUM_ALU 2 // number of ALU's (1-2) |
`define NUM_MEM 2 // number of memory queues (1-3) |
`define NUM_FPU 2 // number of floating-point units (0-2) |
`define WAYS 1 // number of ways parallel (1-3 3 not working yet) |
`define NUM_IDU 1 // number of instruction decode units (1-3) |
`define NUM_ALU 1 // number of ALU's (1-2) |
`define NUM_MEM 1 // number of memory queues (1-3) |
`define NUM_FPU 1 // number of floating-point units (0-2) |
// Note that even with just a single commit bus, multiple instructions may |
// commit if they do not target any registers. Up to three instruction may |
// commit even with just a single bus. |
`define NUM_CMT 2 // number of commit busses (1-2) |
`define NUM_CMT 1 // number of commit busses (1-2) |
// Comment out the following to remove FCU enhancements (branch predictor, BTB, RSB) |
`define FCU_ENH 1 |
// Comment out the following to remove bypassing logic on the functional units |
/thor/trunk/FT64v5/rtl/common/FT64_defines.vh
303,6 → 303,8
`define EXR 8'h7F |
|
`define NOP_INSN {42'd0,`NOP} |
`define INSN_FLT_EXF 16'h1180 |
`define INSN_FLT_IBE 16'h10A0 |
|
`define CSR_CR0 11'h000 |
`define CSR_HARTID 11'h001 |
/thor/trunk/FT64v5/rtl/common/FT64_iexpander.v
72,8 → 72,8
expand[7:6] = 2'b10; |
expand[15:8] = {3'd1,cinstr[11:8],cinstr[5]}; |
expand[16] = 1'b0; |
expand[19:17] = 3'd0; |
expand[23:20] = 4'd1; |
expand[20:17] = 4'd0; |
expand[23:21] = 3'd1; |
expand[31:24] = 8'd0; |
end |
// LDI |
/thor/trunk/FT64v5/rtl/twoway/FT64.v
91,7 → 91,11
parameter NMAP = QENTRIES; |
parameter BRANCH_PRED = 1'b0; |
parameter SUP_TXE = 1'b0; |
parameter SUP_VECTOR = `SUPPORT_VECTOR; |
`ifdef SUPPORT_VECTOR |
parameter SUP_VECTOR = 1'b1; |
`else |
parameter SUP_VECTOR = 1'b0; |
`endif |
parameter DBW = 64; |
parameter ABW = 32; |
parameter AMSB = ABW-1; |
466,7 → 470,7
reg [47:0] iqentry_instr[0:QENTRIES-1]; // instruction opcode |
reg [2:0] iqentry_insln[0:QENTRIES-1]; // instruction length |
reg [7:0] iqentry_exc [0:QENTRIES-1]; // only for branches ... indicates a HALT instruction |
reg [RBIT:0] iqentry_tgt [0:QENTRIES-1]; // Rt field or ZERO -- this is the instruction's target (if any) |
reg [RBIT:0] iqentry_tgt[0:QENTRIES-1]; // Rt field or ZERO -- this is the instruction's target (if any) |
reg [7:0] iqentry_vl [0:QENTRIES-1]; |
reg [5:0] iqentry_ven [0:QENTRIES-1]; // vector element number |
reg [63:0] iqentry_a0 [0:QENTRIES-1]; // argument 0 (immediate) |
871,9 → 875,9
parameter B_DCacheLoadWait1 = 5'd4; |
parameter B_DCacheLoadWait2 = 5'd5; |
parameter B_DCacheLoadResetBusy = 5'd6; |
parameter B7 = 5'd7; |
parameter B_ICacheAck = 5'd7; |
parameter B8 = 5'd8; |
parameter B9 = 5'd9; |
parameter B_ICacheNack = 5'd9; |
parameter B10 = 5'd10; |
parameter B11 = 5'd11; |
parameter B12 = 5'd12; |
897,11 → 901,11
parameter IC1 = 4'd1; |
parameter IC2 = 4'd2; |
parameter IC3 = 4'd3; |
parameter IC4 = 4'd4; |
parameter IC_WaitL2 = 4'd4; |
parameter IC5 = 4'd5; |
parameter IC6 = 4'd6; |
parameter IC7 = 4'd7; |
parameter IC8 = 4'd8; |
parameter IC_Next = 4'd8; |
parameter IC9 = 4'd9; |
parameter IC10 = 4'd10; |
parameter IC3a = 4'd11; |
917,10 → 921,11
reg [2:0] iccnt; |
reg L1_wr0,L1_wr1,L1_wr2; |
reg L1_invline; |
wire [1:0] ic0_fault,ic1_fault,ic2_fault; |
reg [8:0] L1_en; |
reg [37:0] L1_adr, L2_adr; |
reg [287:0] L2_rdat; |
wire [287:0] L2_dato; |
reg [289:0] L2_rdat; |
wire [289:0] L2_dato; |
reg L2_xsel; |
|
generate begin : gRegfileInst |
1054,10 → 1059,11
.nxt(icnxt), |
.wr(L1_wr0), |
.en(L1_en), |
.adr(icstate==IDLE||icstate==IC8 ? {pcr[5:0],pc0} : L1_adr), |
.adr(icstate==IDLE||icstate==IC_Next ? {pcr[5:0],pc0} : L1_adr), |
.wadr(L1_adr), |
.i(L2_rdat), |
.o(insn0a), |
.fault(ic0_fault), |
.hit(ihit0), |
.invall(invic), |
.invline(L1_invline) |
1071,10 → 1077,11
.nxt(icnxt), |
.wr(L1_wr1), |
.en(L1_en), |
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc1}: {pcr[5:0],pc0plus6} ): L1_adr), |
.adr(icstate==IDLE||icstate==IC_Next ? (thread_en ? {pcr[5:0],pc1}: {pcr[5:0],pc0plus6} ): L1_adr), |
.wadr(L1_adr), |
.i(L2_rdat), |
.o(insn1b), |
.fault(ic1_fault), |
.hit(ihit1), |
.invall(invic), |
.invline(L1_invline) |
1091,10 → 1098,11
.nxt(icnxt), |
.wr(L1_wr2), |
.en(L1_en), |
.adr(icstate==IDLE||icstate==IC8 ? (thread_en ? {pcr[5:0],pc2} : {pcr[5:0],pc0plus12}) : L1_adr), |
.adr(icstate==IDLE||icstate==IC_Next ? (thread_en ? {pcr[5:0],pc2} : {pcr[5:0],pc0plus12}) : L1_adr), |
.wadr(L1_adr), |
.i(L2_rdat), |
.o(insn2b), |
.fault(ic2_fault), |
.hit(ihit2), |
.invall(invic), |
.invline(L1_invline) |
1110,7 → 1118,7
.rst(rst), |
.clk(clk), |
.nxt(L2_nxt), |
.wr(bstate==B7 && ack_i), |
.wr(bstate==B_ICacheAck && ack_i), |
.xsel(L2_xsel), |
.adr(L2_adr), |
.cnt(iccnt), |
1653,7 → 1661,7
if (insn0a[`INSTRUCTION_OP]==`BRK && insn0a[23:21]==3'd0 && insn0a[7:6]==2'b00) |
insn0 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK}; |
else |
insn0 <= insn0a; |
insn0 <= ic0_fault[1] ? `INSN_FLT_IBE : ic0_fault[0] ? `INSN_FLT_EXF : insn0a; |
end |
else |
insn0 <= `NOP_INSN; |
1666,7 → 1674,7
if (insn1a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn1a[7:6]==2'b00) |
insn1 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK}; |
else |
insn1 <= insn1a; |
insn1 <= ic1_fault[1] ? `INSN_FLT_IBE : ic1_fault[0] ? `INSN_FLT_EXF : insn1a; |
end |
else |
insn1 <= `NOP_INSN; |
1679,7 → 1687,7
if (insn2a[`INSTRUCTION_OP]==`BRK && insn1a[23:21]==3'd0 && insn2a[7:6]==2'b00) |
insn2 <= {8'd1,3'd0,4'b0,1'b0,`FLT_PRIV,2'b00,`BRK}; |
else |
insn2 <= insn2a; |
insn2 <= ic2_fault[1] ? `INSN_FLT_IBE : ic2_fault[0] ? `INSN_FLT_EXF : insn2a; |
end |
else |
insn2 <= `NOP_INSN; |
3871,6 → 3879,106
) begin |
iqentry_alu0_issue[head7] = `TRUE; |
end |
else if (could_issue[head8] && iqentry_alu[head8] |
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0]) |
&& (!(iqentry_v[head2] && iqentry_sync[head2]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1])) |
) |
&& (!(iqentry_v[head3] && iqentry_sync[head3]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2])) |
) |
&& (!(iqentry_v[head4] && iqentry_sync[head4]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3])) |
) |
&& (!(iqentry_v[head5] && iqentry_sync[head5]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4])) |
) |
&& (!(iqentry_v[head6] && iqentry_sync[head6]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5])) |
) |
&& (!(iqentry_v[head7] && iqentry_sync[head7]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5]) |
&& (!iqentry_v[head6]) |
) |
) |
) begin |
iqentry_alu0_issue[head8] = `TRUE; |
end |
else if (could_issue[head9] && iqentry_alu[head9] |
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0]) |
&& (!(iqentry_v[head2] && iqentry_sync[head2]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1])) |
) |
&& (!(iqentry_v[head3] && iqentry_sync[head3]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2])) |
) |
&& (!(iqentry_v[head4] && iqentry_sync[head4]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3])) |
) |
&& (!(iqentry_v[head5] && iqentry_sync[head5]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4])) |
) |
&& (!(iqentry_v[head6] && iqentry_sync[head6]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5])) |
) |
&& (!(iqentry_v[head7] && iqentry_sync[head7]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5]) |
&& (!iqentry_v[head6])) |
) |
&& (!(iqentry_v[head8] && iqentry_sync[head8]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5]) |
&& (!iqentry_v[head6]) |
&& (!iqentry_v[head7]) |
) |
) |
) begin |
iqentry_alu0_issue[head9] = `TRUE; |
end |
`endif |
end |
|
4663,6 → 4771,106
) begin |
iqentry_fcu_issue[head7] = `TRUE; |
end |
else if (could_issue[head8] && iqentry_fc[head8] |
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0]) |
&& (!(iqentry_v[head2] && iqentry_sync[head2]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1])) |
) |
&& (!(iqentry_v[head3] && iqentry_sync[head3]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2])) |
) |
&& (!(iqentry_v[head4] && iqentry_sync[head4]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3])) |
) |
&& (!(iqentry_v[head5] && iqentry_sync[head5]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4])) |
) |
&& (!(iqentry_v[head6] && iqentry_sync[head6]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5])) |
) |
&& (!(iqentry_v[head7] && iqentry_sync[head7]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5]) |
&& (!iqentry_v[head6]) |
) |
) |
) begin |
iqentry_fcu_issue[head8] = `TRUE; |
end |
else if (could_issue[head9] && iqentry_fc[head9] |
&& (!(iqentry_v[head1] && iqentry_sync[head1]) || !iqentry_v[head0]) |
&& (!(iqentry_v[head2] && iqentry_sync[head2]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1])) |
) |
&& (!(iqentry_v[head3] && iqentry_sync[head3]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2])) |
) |
&& (!(iqentry_v[head4] && iqentry_sync[head4]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3])) |
) |
&& (!(iqentry_v[head5] && iqentry_sync[head5]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4])) |
) |
&& (!(iqentry_v[head6] && iqentry_sync[head6]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5])) |
) |
&& (!(iqentry_v[head7] && iqentry_sync[head7]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5]) |
&& (!iqentry_v[head6])) |
) |
&& (!(iqentry_v[head8] && iqentry_sync[head8]) || |
((!iqentry_v[head0]) |
&& (!iqentry_v[head1]) |
&& (!iqentry_v[head2]) |
&& (!iqentry_v[head3]) |
&& (!iqentry_v[head4]) |
&& (!iqentry_v[head5]) |
&& (!iqentry_v[head6]) |
&& (!iqentry_v[head7]) |
) |
) |
) begin |
iqentry_fcu_issue[head9] = `TRUE; |
end |
`endif |
end |
end |
5103,6 → 5311,310
&& !(iqentry_fc[head4]||iqentry_canex[head4]) |
&& !(iqentry_fc[head5]||iqentry_canex[head5]) |
&& !(iqentry_fc[head6]||iqentry_canex[head6])); |
|
memissue[ head8 ] = ~iqentry_stomp[head8] && iqentry_memready[ head8 ] // addr and data are valid |
// ... and no preceding instruction is ready to go |
&& issue_count < `NUM_MEM |
//&& ~iqentry_memready[head0] |
//&& ~iqentry_memready[head1] |
//&& ~iqentry_memready[head2] |
//&& ~iqentry_memready[head3] |
//&& ~iqentry_memready[head4] |
//&& ~iqentry_memready[head5] |
//&& ~iqentry_memready[head6] |
// ... and there is no address-overlap with any preceding instruction |
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0] |
|| (iqentry_a1_v[head0] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0]))) |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1] |
|| (iqentry_a1_v[head1] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1]))) |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2] |
|| (iqentry_a1_v[head2] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2]))) |
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3] |
|| (iqentry_a1_v[head3] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3]))) |
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4] |
|| (iqentry_a1_v[head4] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4]))) |
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5] |
|| (iqentry_a1_v[head5] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5]))) |
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6]) || iqentry_done[head6] |
|| (iqentry_a1_v[head6] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head6][AMSB:3] || iqentry_out[head6] || iqentry_done[head6]))) |
&& (!iqentry_mem[head7] || (iqentry_agen[head7] & iqentry_out[head7]) || iqentry_done[head7] |
|| (iqentry_a1_v[head7] && (iqentry_a1[head8][AMSB:3] != iqentry_a1[head7][AMSB:3] || iqentry_out[head7] || iqentry_done[head7]))) |
&& (iqentry_rl[head8] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5] || !iqentry_mem[head5]) |
&& (iqentry_done[head6] || !iqentry_v[head6] || !iqentry_mem[head6]) |
&& (iqentry_done[head7] || !iqentry_v[head7] || !iqentry_mem[head7]) |
: 1'b1) |
// ... if a preivous op has the aquire bit set |
&& !(iqentry_aq[head0] && iqentry_v[head0]) |
&& !(iqentry_aq[head1] && iqentry_v[head1]) |
&& !(iqentry_aq[head2] && iqentry_v[head2]) |
&& !(iqentry_aq[head3] && iqentry_v[head3]) |
&& !(iqentry_aq[head4] && iqentry_v[head4]) |
&& !(iqentry_aq[head5] && iqentry_v[head5]) |
&& !(iqentry_aq[head6] && iqentry_v[head6]) |
&& !(iqentry_aq[head7] && iqentry_v[head7]) |
// ... and there isn't a barrier, or everything before the barrier is done or invalid |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0])) |
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1])) |
) |
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2])) |
) |
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3])) |
) |
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4])) |
) |
&& (!(iqentry_iv[head6] && iqentry_memsb[head6]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5])) |
) |
&& (!(iqentry_iv[head7] && iqentry_memsb[head7]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5]) |
&& (iqentry_done[head6] || !iqentry_v[head6]) |
) |
) |
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])) |
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])) |
) |
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])) |
) |
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])) |
) |
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])) |
) |
&& (!(iqentry_iv[head6] && iqentry_memdb[head6]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]) |
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5])) |
) |
&& (!(iqentry_iv[head7] && iqentry_memdb[head7]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]) |
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5]) |
&& (!iqentry_mem[head6] || iqentry_done[head6] || !iqentry_v[head6]) |
) |
) |
// ... and, if it is a SW, there is no chance of it being undone |
&& (iqentry_load[head8] || |
!(iqentry_fc[head0]||iqentry_canex[head0]) |
&& !(iqentry_fc[head1]||iqentry_canex[head1]) |
&& !(iqentry_fc[head2]||iqentry_canex[head2]) |
&& !(iqentry_fc[head3]||iqentry_canex[head3]) |
&& !(iqentry_fc[head4]||iqentry_canex[head4]) |
&& !(iqentry_fc[head5]||iqentry_canex[head5]) |
&& !(iqentry_fc[head6]||iqentry_canex[head6]) |
&& !(iqentry_fc[head7]||iqentry_canex[head7]) |
); |
memissue[ head9 ] = ~iqentry_stomp[head9] && iqentry_memready[ head9 ] // addr and data are valid |
// ... and no preceding instruction is ready to go |
&& issue_count < `NUM_MEM |
//&& ~iqentry_memready[head0] |
//&& ~iqentry_memready[head1] |
//&& ~iqentry_memready[head2] |
//&& ~iqentry_memready[head3] |
//&& ~iqentry_memready[head4] |
//&& ~iqentry_memready[head5] |
//&& ~iqentry_memready[head6] |
// ... and there is no address-overlap with any preceding instruction |
&& (!iqentry_mem[head0] || (iqentry_agen[head0] & iqentry_out[head0]) || iqentry_done[head0] |
|| (iqentry_a1_v[head0] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head0][AMSB:3] || iqentry_out[head0] || iqentry_done[head0]))) |
&& (!iqentry_mem[head1] || (iqentry_agen[head1] & iqentry_out[head1]) || iqentry_done[head1] |
|| (iqentry_a1_v[head1] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head1][AMSB:3] || iqentry_out[head1] || iqentry_done[head1]))) |
&& (!iqentry_mem[head2] || (iqentry_agen[head2] & iqentry_out[head2]) || iqentry_done[head2] |
|| (iqentry_a1_v[head2] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head2][AMSB:3] || iqentry_out[head2] || iqentry_done[head2]))) |
&& (!iqentry_mem[head3] || (iqentry_agen[head3] & iqentry_out[head3]) || iqentry_done[head3] |
|| (iqentry_a1_v[head3] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head3][AMSB:3] || iqentry_out[head3] || iqentry_done[head3]))) |
&& (!iqentry_mem[head4] || (iqentry_agen[head4] & iqentry_out[head4]) || iqentry_done[head4] |
|| (iqentry_a1_v[head4] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head4][AMSB:3] || iqentry_out[head4] || iqentry_done[head4]))) |
&& (!iqentry_mem[head5] || (iqentry_agen[head5] & iqentry_out[head5]) || iqentry_done[head5] |
|| (iqentry_a1_v[head5] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head5][AMSB:3] || iqentry_out[head5] || iqentry_done[head5]))) |
&& (!iqentry_mem[head6] || (iqentry_agen[head6] & iqentry_out[head6]) || iqentry_done[head6] |
|| (iqentry_a1_v[head6] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head6][AMSB:3] || iqentry_out[head6] || iqentry_done[head6]))) |
&& (!iqentry_mem[head7] || (iqentry_agen[head7] & iqentry_out[head7]) || iqentry_done[head7] |
|| (iqentry_a1_v[head7] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head7][AMSB:3] || iqentry_out[head7] || iqentry_done[head7]))) |
&& (!iqentry_mem[head8] || (iqentry_agen[head8] & iqentry_out[head8]) || iqentry_done[head8] |
|| (iqentry_a1_v[head8] && (iqentry_a1[head9][AMSB:3] != iqentry_a1[head8][AMSB:3] || iqentry_out[head8] || iqentry_done[head8]))) |
&& (iqentry_rl[head9] ? (iqentry_done[head0] || !iqentry_v[head0] || !iqentry_mem[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1] || !iqentry_mem[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2] || !iqentry_mem[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3] || !iqentry_mem[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4] || !iqentry_mem[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5] || !iqentry_mem[head5]) |
&& (iqentry_done[head6] || !iqentry_v[head6] || !iqentry_mem[head6]) |
&& (iqentry_done[head7] || !iqentry_v[head7] || !iqentry_mem[head7]) |
&& (iqentry_done[head8] || !iqentry_v[head8] || !iqentry_mem[head8]) |
: 1'b1) |
// ... if a preivous op has the aquire bit set |
&& !(iqentry_aq[head0] && iqentry_v[head0]) |
&& !(iqentry_aq[head1] && iqentry_v[head1]) |
&& !(iqentry_aq[head2] && iqentry_v[head2]) |
&& !(iqentry_aq[head3] && iqentry_v[head3]) |
&& !(iqentry_aq[head4] && iqentry_v[head4]) |
&& !(iqentry_aq[head5] && iqentry_v[head5]) |
&& !(iqentry_aq[head6] && iqentry_v[head6]) |
&& !(iqentry_aq[head7] && iqentry_v[head7]) |
&& !(iqentry_aq[head8] && iqentry_v[head8]) |
// ... and there isn't a barrier, or everything before the barrier is done or invalid |
&& (!(iqentry_iv[head1] && iqentry_memsb[head1]) || (iqentry_done[head0] || !iqentry_v[head0])) |
&& (!(iqentry_iv[head2] && iqentry_memsb[head2]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1])) |
) |
&& (!(iqentry_iv[head3] && iqentry_memsb[head3]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2])) |
) |
&& (!(iqentry_iv[head4] && iqentry_memsb[head4]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3])) |
) |
&& (!(iqentry_iv[head5] && iqentry_memsb[head5]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4])) |
) |
&& (!(iqentry_iv[head6] && iqentry_memsb[head6]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5])) |
) |
&& (!(iqentry_iv[head7] && iqentry_memsb[head7]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5]) |
&& (iqentry_done[head6] || !iqentry_v[head6])) |
) |
&& (!(iqentry_iv[head8] && iqentry_memsb[head8]) || |
((iqentry_done[head0] || !iqentry_v[head0]) |
&& (iqentry_done[head1] || !iqentry_v[head1]) |
&& (iqentry_done[head2] || !iqentry_v[head2]) |
&& (iqentry_done[head3] || !iqentry_v[head3]) |
&& (iqentry_done[head4] || !iqentry_v[head4]) |
&& (iqentry_done[head5] || !iqentry_v[head5]) |
&& (iqentry_done[head6] || !iqentry_v[head6]) |
&& (iqentry_done[head7] || !iqentry_v[head7]) |
) |
) |
&& (!(iqentry_iv[head1] && iqentry_memdb[head1]) || (!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0])) |
&& (!(iqentry_iv[head2] && iqentry_memdb[head2]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1])) |
) |
&& (!(iqentry_iv[head3] && iqentry_memdb[head3]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2])) |
) |
&& (!(iqentry_iv[head4] && iqentry_memdb[head4]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3])) |
) |
&& (!(iqentry_iv[head5] && iqentry_memdb[head5]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4])) |
) |
&& (!(iqentry_iv[head6] && iqentry_memdb[head6]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]) |
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5])) |
) |
&& (!(iqentry_iv[head7] && iqentry_memdb[head7]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]) |
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5]) |
&& (!iqentry_mem[head6] || iqentry_done[head6] || !iqentry_v[head6])) |
) |
&& (!(iqentry_iv[head8] && iqentry_memdb[head8]) || |
((!iqentry_mem[head0] || iqentry_done[head0] || !iqentry_v[head0]) |
&& (!iqentry_mem[head1] || iqentry_done[head1] || !iqentry_v[head1]) |
&& (!iqentry_mem[head2] || iqentry_done[head2] || !iqentry_v[head2]) |
&& (!iqentry_mem[head3] || iqentry_done[head3] || !iqentry_v[head3]) |
&& (!iqentry_mem[head4] || iqentry_done[head4] || !iqentry_v[head4]) |
&& (!iqentry_mem[head5] || iqentry_done[head5] || !iqentry_v[head5]) |
&& (!iqentry_mem[head6] || iqentry_done[head6] || !iqentry_v[head6]) |
&& (!iqentry_mem[head7] || iqentry_done[head7] || !iqentry_v[head7]) |
) |
) |
// ... and, if it is a SW, there is no chance of it being undone |
&& (iqentry_load[head9] || |
!(iqentry_fc[head0]||iqentry_canex[head0]) |
&& !(iqentry_fc[head1]||iqentry_canex[head1]) |
&& !(iqentry_fc[head2]||iqentry_canex[head2]) |
&& !(iqentry_fc[head3]||iqentry_canex[head3]) |
&& !(iqentry_fc[head4]||iqentry_canex[head4]) |
&& !(iqentry_fc[head5]||iqentry_canex[head5]) |
&& !(iqentry_fc[head6]||iqentry_canex[head6]) |
&& !(iqentry_fc[head7]||iqentry_canex[head7]) |
&& !(iqentry_fc[head8]||iqentry_canex[head8]) |
); |
`endif |
end |
|
5565,7 → 6077,7
|
always @* |
for (n = 0; n < QENTRIES; n = n + 1) |
iqentry_memready[n] <= (iqentry_v[n] & iqentry_memopsvalid[n] & ~iqentry_memissue[n] & ~iqentry_done[n] & ~iqentry_out[n] & ~iqentry_stomp[n]); |
iqentry_memready[n] <= (iqentry_v[n] & iqentry_iv[n] & iqentry_memopsvalid[n] & ~iqentry_memissue[n] & ~iqentry_done[n] & ~iqentry_out[n] & ~iqentry_stomp[n]); |
|
assign outstanding_stores = (dram0 && dram0_store) || |
(dram1 && dram1_store) || |
6558,7 → 7070,7
iqentry_res [ alu0_id[`QBITS] ] <= alu0_bus; |
iqentry_exc [ alu0_id[`QBITS] ] <= alu0_exc; |
iqentry_done[ alu0_id[`QBITS] ] <= !iqentry_mem[ alu0_id[`QBITS] ] && alu0_done; |
iqentry_cmt[ alu0_id[`QBITS] ] <= !iqentry_mem[ alu0_id[`QBITS] ] && alu0_done; |
iqentry_cmt [ alu0_id[`QBITS] ] <= !iqentry_mem[ alu0_id[`QBITS] ] && alu0_done; |
iqentry_out [ alu0_id[`QBITS] ] <= `INV; |
iqentry_agen[ alu0_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET |
alu0_dataready <= FALSE; |
6569,7 → 7081,7
iqentry_res [ alu1_id[`QBITS] ] <= alu1_bus; |
iqentry_exc [ alu1_id[`QBITS] ] <= alu1_exc; |
iqentry_done[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done; |
iqentry_cmt[ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done; |
iqentry_cmt [ alu1_id[`QBITS] ] <= !iqentry_mem[ alu1_id[`QBITS] ] && alu1_done; |
iqentry_out [ alu1_id[`QBITS] ] <= `INV; |
iqentry_agen[ alu1_id[`QBITS] ] <= `VAL;//!iqentry_fc[alu0_id[`QBITS]]; // RET |
alu1_dataready <= FALSE; |
6633,7 → 7145,7
fcu_clearbm <= `TRUE; |
end |
|
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ]) begin |
if (mem1_available && dramA_v && iqentry_v[ dramA_id[`QBITS] ] && iqentry_load[ dramA_id[`QBITS] ] && !iqentry_stomp[dramA_id[`QBITS]]) begin |
iqentry_res [ dramA_id[`QBITS] ] <= dramA_bus; |
iqentry_exc [ dramA_id[`QBITS] ] <= dramA_exc; |
iqentry_done[ dramA_id[`QBITS] ] <= `VAL; |
6641,7 → 7153,7
iqentry_cmt [ dramA_id[`QBITS] ] <= `VAL; |
iqentry_aq [ dramA_id[`QBITS] ] <= `INV; |
end |
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ]) begin |
if (mem2_available && `NUM_MEM > 1 && dramB_v && iqentry_v[ dramB_id[`QBITS] ] && iqentry_load[ dramB_id[`QBITS] ] && !iqentry_stomp[dramB_id[`QBITS]]) begin |
iqentry_res [ dramB_id[`QBITS] ] <= dramB_bus; |
iqentry_exc [ dramB_id[`QBITS] ] <= dramB_exc; |
iqentry_done[ dramB_id[`QBITS] ] <= `VAL; |
6649,7 → 7161,7
iqentry_cmt [ dramB_id[`QBITS] ] <= `VAL; |
iqentry_aq [ dramB_id[`QBITS] ] <= `INV; |
end |
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ]) begin |
if (mem3_available && `NUM_MEM > 2 && dramC_v && iqentry_v[ dramC_id[`QBITS] ] && iqentry_load[ dramC_id[`QBITS] ] && !iqentry_stomp[dramC_id[`QBITS]]) begin |
iqentry_res [ dramC_id[`QBITS] ] <= dramC_bus; |
iqentry_exc [ dramC_id[`QBITS] ] <= dramC_exc; |
iqentry_done[ dramC_id[`QBITS] ] <= `VAL; |
7074,7 → 7586,7
// grab requests that have finished and put them on the dram_bus |
if (mem1_available && dram0 == `DRAMREQ_READY) begin |
dram0 <= `DRAMSLOT_AVAIL; |
dramA_v <= dram0_load; |
dramA_v <= dram0_load && !iqentry_stomp[dram0_id[`QBITS]]; |
dramA_id <= dram0_id; |
dramA_exc <= dram0_exc; |
dramA_bus <= fnDati(dram0_instr,dram0_addr,rdat0); |
7084,7 → 7596,7
// dramA_v <= `INV; |
if (mem2_available && dram1 == `DRAMREQ_READY && `NUM_MEM > 1) begin |
dram1 <= `DRAMSLOT_AVAIL; |
dramB_v <= dram1_load; |
dramB_v <= dram1_load && !iqentry_stomp[dram1_id[`QBITS]]; |
dramB_id <= dram1_id; |
dramB_exc <= dram1_exc; |
dramB_bus <= fnDati(dram1_instr,dram1_addr,rdat1); |
7094,12 → 7606,26
// dramB_v <= `INV; |
if (mem3_available && dram2 == `DRAMREQ_READY && `NUM_MEM > 2) begin |
dram2 <= `DRAMSLOT_AVAIL; |
dramC_v <= dram2_load; |
dramC_v <= dram2_load && !iqentry_stomp[dram2_id[`QBITS]]; |
dramC_id <= dram2_id; |
dramC_exc <= dram2_exc; |
dramC_bus <= fnDati(dram2_instr,dram2_addr,rdat2); |
if (dram2_store) $display("m[%h] <- %h", dram2_addr, dram2_data); |
end |
/* |
// Squash load results for stomped on instructions |
begin |
if (iqentry_stomp[dram0_id[`QBITS]]) |
dram0_load <= `FALSE; |
if (`NUM_MEM > 1) |
if (iqentry_stomp[dram1_id[`QBITS]]) |
dram1_load <= `FALSE; |
if (`NUM_MEM > 2) |
if (iqentry_stomp[dram2_id[`QBITS]]) |
dram2_load <= `FALSE; |
end |
*/ |
|
// else |
// dramC_v <= `INV; |
|
7405,7 → 7931,7
IDLE: |
// If the bus unit is busy doing an update involving L1_adr or L2_adr |
// we have to wait. |
if (bstate != B7 && bstate != B9) begin |
if (bstate != B_ICacheAck && bstate != B_ICacheNack) begin |
if (!ihit0) begin |
L1_adr <= {pcr[5:0],pc0[31:5],5'h0}; |
L2_adr <= {pcr[5:0],pc0[31:5],5'h0}; |
7445,14 → 7971,14
end |
IC2: icstate <= IC3; |
IC3: icstate <= IC3a; |
IC3a: icstate <= IC4; |
// If data was in the L2 cache already there's no need to wait on the |
// BIU to retrieve data. It can be determined if the hit signal was |
// already active when this state was entered in which case waiting |
// will do no good. |
// The IC machine will stall in this state until the BIU has loaded the |
// L2 cache. |
IC4: |
IC3a: icstate <= IC_WaitL2; |
// If data was in the L2 cache already there's no need to wait on the |
// BIU to retrieve data. It can be determined if the hit signal was |
// already active when this state was entered in which case waiting |
// will do no good. |
// The IC machine will stall in this state until the BIU has loaded the |
// L2 cache. |
IC_WaitL2: |
if (ihitL2 && picstate==IC3a) begin |
L1_en <= 9'h1FF; |
L1_wr0 <= TRUE; |
7462,7 → 7988,7
L2_rdat <= L2_dato; |
icstate <= IC5; |
end |
else if (bstate!=B9) |
else if (bstate!=B_ICacheNack) |
; |
else begin |
L1_en <= 9'h1FF; |
7470,7 → 7996,8
L1_wr1 <= TRUE && `WAYS > 1; |
L1_wr2 <= TRUE && `WAYS > 2; |
L1_adr <= L2_adr; |
L2_rdat <= L2_dato; |
// L2_rdat set below while loading cache line |
//L2_rdat <= L2_dato; |
icstate <= IC5; |
end |
IC5: |
7482,11 → 8009,12
icstate <= IC6; |
end |
IC6: icstate <= IC7; |
IC7: icstate <= IC8; |
IC8: begin |
icstate <= IDLE; |
icnxt <= TRUE; |
end |
IC7: icstate <= IC_Next; |
IC_Next: |
begin |
icstate <= IDLE; |
icnxt <= TRUE; |
end |
default: icstate <= IDLE; |
endcase |
|
7493,10 → 8021,23
if (mem1_available && dram0_load) |
case(dram0) |
`DRAMSLOT_AVAIL: ; |
`DRAMSLOT_BUSY: dram0 <= dram0 + !dram0_unc; |
3'd2: dram0 <= dram0 + 3'd1; |
3'd3: dram0 <= dram0 + 3'd1; |
3'd4: if (dhit0) dram0 <= `DRAMREQ_READY; else dram0 <= `DRAMSLOT_REQBUS; |
`DRAMSLOT_BUSY: |
dram0 <= dram0 + !dram0_unc; |
3'd2: |
dram0 <= dram0 + 3'd1; |
3'd3: |
dram0 <= dram0 + 3'd1; |
3'd4: |
if (iqentry_v[dram0_id[`QBITS]] && !iqentry_stomp[dram0_id[`QBITS]]) begin |
if (dhit0) |
dram0 <= `DRAMREQ_READY; |
else |
dram0 <= `DRAMSLOT_REQBUS; |
end |
else begin |
dram0 <= `DRAMSLOT_AVAIL; |
dram0_load <= `FALSE; |
end |
`DRAMSLOT_REQBUS: ; |
`DRAMSLOT_HASBUS: ; |
`DRAMREQ_READY: ; |
7505,10 → 8046,23
if (mem2_available && dram1_load && `NUM_MEM > 1) |
case(dram1) |
`DRAMSLOT_AVAIL: ; |
`DRAMSLOT_BUSY: dram1 <= dram1 + !dram1_unc; |
3'd2: dram1 <= dram1 + 3'd1; |
3'd3: dram1 <= dram1 + 3'd1; |
3'd4: if (dhit1) dram1 <= `DRAMREQ_READY; else dram1 <= `DRAMSLOT_REQBUS; |
`DRAMSLOT_BUSY: |
dram1 <= dram1 + !dram1_unc; |
3'd2: |
dram1 <= dram1 + 3'd1; |
3'd3: |
dram1 <= dram1 + 3'd1; |
3'd4: |
if (iqentry_v[dram1_id[`QBITS]] && !iqentry_stomp[dram1_id[`QBITS]]) begin |
if (dhit1) |
dram1 <= `DRAMREQ_READY; |
else |
dram1 <= `DRAMSLOT_REQBUS; |
end |
else begin |
dram1 <= `DRAMSLOT_AVAIL; |
dram1_load <= `FALSE; |
end |
`DRAMSLOT_REQBUS: ; |
`DRAMSLOT_HASBUS: ; |
`DRAMREQ_READY: ; |
7517,10 → 8071,23
if (mem3_available && dram2_load && `NUM_MEM > 2) |
case(dram2) |
`DRAMSLOT_AVAIL: ; |
`DRAMSLOT_BUSY: dram2 <= dram2 + !dram2_unc; |
3'd2: dram2 <= dram2 + 3'd1; |
3'd3: dram2 <= dram2 + 3'd1; |
3'd4: if (dhit2) dram2 <= `DRAMREQ_READY; else dram2 <= `DRAMSLOT_REQBUS; |
`DRAMSLOT_BUSY: |
dram2 <= dram2 + !dram2_unc; |
3'd2: |
dram2 <= dram2 + 3'd1; |
3'd3: |
dram2 <= dram2 + 3'd1; |
3'd4: |
if (iqentry_v[dram2_id[`QBITS]] && !iqentry_stomp[dram2_id[`QBITS]]) begin |
if (dhit2) |
dram2 <= `DRAMREQ_READY; |
else |
dram2 <= `DRAMSLOT_REQBUS; |
end |
else begin |
dram2 <= `DRAMSLOT_AVAIL; |
dram2_load <= `FALSE; |
end |
`DRAMSLOT_REQBUS: ; |
`DRAMSLOT_HASBUS: ; |
`DRAMREQ_READY: ; |
7923,7 → 8490,7
ol_o <= ol[0]; |
L2_adr <= {pcr[5:0],L1_adr[31:5],5'h0}; |
L2_xsel <= 1'b0; |
bstate <= B7; |
bstate <= B_ICacheAck; |
end |
end |
// Terminal state for a store operation. |
8080,7 → 8647,7
end |
|
// Ack state for instruction cache load |
B7: |
B_ICacheAck: |
if (ack_i|err_i) begin |
errq <= errq | err_i; |
exvq <= exvq | exv_i; |
8089,9 → 8656,17
// L1_wr1 <= `TRUE; |
// L1_adr <= L2_adr; |
if (err_i) |
L2_rdat <= {9{11'b0,4'd7,1'b0,`FLT_IBE,2'b00,`BRK}}; |
L2_rdat <= {18{`INSN_FLT_IBE}}; |
else |
L2_rdat <= {dat_i[31:0],{4{dat_i}}}; |
case(iccnt) |
3'd0: L2_rdat[63:0] <= dat_i; |
3'd1: L2_rdat[127:64] <= dat_i; |
3'd2: L2_rdat[191:128] <= dat_i; |
3'd3: L2_rdat[255:192] <= dat_i; |
3'd4: L2_rdat[287:256] <= dat_i[31:0]; |
default: ; |
endcase |
//L2_rdat <= {dat_i[31:0],{4{dat_i}}}; |
iccnt <= iccnt + 3'd1; |
//stb_o <= `LOW; |
if (iccnt==3'd3) |
8103,7 → 8678,7
stb_o <= `LOW; |
sel_o <= 8'h00; |
icl_o <= `LOW; |
bstate <= B9; |
bstate <= B_ICacheNack; |
end |
else begin |
L2_adr[4:3] <= L2_adr[4:3] + 2'd1; |
8111,7 → 8686,7
L2_xsel <= 1'b1; |
end |
end |
B9: |
B_ICacheNack: |
begin |
L1_wr0 <= `FALSE; |
L1_wr1 <= `FALSE; |
8549,15 → 9124,16
if (|panic && ~outstanding_stores) begin |
$finish; |
end |
/* |
for (n = 0; n < QENTRIES; n = n + 1) |
if (branchmiss) begin |
if (!setpred[n]) begin |
iqentry_instr[n][`INSTRUCTION_OP] <= `NOP; |
iqentry_done[n] <= `VAL; |
iqentry_cmt[n] <= `VAL; |
iqentry_done[n] <= iqentry_v[n]; |
iqentry_cmt[n] <= iqentry_v[n]; |
end |
end |
|
*/ |
if (snr) begin |
seq_num <= 32'd0; |
seq_num1 <= 32'd0; |
/thor/trunk/FT64v5/software/AS64/source/FT64.cpp
1312,9 → 1312,6
// So |
// addi r1,r2,#$12345678 |
// Becomes: |
// ldiq1 r52,#$00123 |
// oriq0 r52,#$45678 |
// addi r1,r2,r52 |
// --------------------------------------------------------------------------- |
|
static void process_riop(int64_t opcode6) |
4572,6 → 4569,7
case tk_ibne: process_ibne(0x26,2); break; |
case tk_inc: process_inc(0x1A); break; |
case tk_if: pif1 = inptr-2; doif(); break; |
case tk_ifdef: pif1 = inptr - 5; doifdef(); break; |
case tk_itof: process_itof(0x15); break; |
case tk_iret: process_iret(0xC8000002); break; |
case tk_isnull: process_rop(0x0C); break; |
/thor/trunk/FT64v5/software/AS64/source/main.cpp
1510,7 → 1510,7
|
// Cut out the if statement |
p1 = pif1; |
memmove(pif1,pif2,sizeof(masterFile)-(pif2-masterFile)); |
memmove(pif1,pif2,masterFileLength-(pif2-masterFile)); |
|
p1 = inptr = pif1; |
while(*inptr) { |
1526,13 → 1526,13
// If the if was false cut out the code between |
// if and endif |
if (val==0 && !codecut) { |
memmove(pif1,p3,sizeof(masterFile)-(p3-masterFile)); |
memmove(pif1,p3,masterFileLength-(p3-masterFile)); |
inptr = pif1; |
return; |
} |
else { |
// remove endif but leave remaining text |
memmove(p2,inptr,sizeof(masterFile)-(inptr-masterFile)); |
memmove(p2,inptr,masterFileLength-(inptr-masterFile)); |
inptr = p2; |
} |
} |
1542,7 → 1542,7
// cut out code between if and else |
// and keep going until endif |
if (val==0) { |
memmove(pif1,p2+4,sizeof(masterFile)-(p2+4-masterFile)); |
memmove(pif1,p2+4,masterFileLength-(p2+4-masterFile)); |
inptr = pif1; |
codecut = true; |
} |
1549,7 → 1549,7
else { |
// remove the else from text |
// and keep going until endif |
memmove(p2,inptr,sizeof(masterFile)-(inptr-masterFile)); |
memmove(p2,inptr,masterFileLength-(inptr-masterFile)); |
inptr = p2; |
} |
} |
1576,11 → 1576,12
{ |
int64_t val; |
|
SkipSpaces(); |
if (getIdentifier()==0) |
printf("Expecting an identifier %d.\n", lineno); |
val = (find_symbol(lastid)!=nullptr); |
val = (find_symbol(lastid)!=nullptr); |
pif2 = inptr; |
ScanToEOL(); |
pif2 = inptr; |
skipif(val); |
} |
|
1590,7 → 1591,7
|
if (getIdentifier()==0) |
printf("Expecting an identifier %d.\n", lineno); |
val = (find_symbol(lastid)==nullptr); |
val = (find_symbol(lastid)==nullptr); |
ScanToEOL(); |
pif2 = inptr; |
skipif(val); |
/thor/trunk/FT64v5/software/AS64/source/proto.h
1,4 → 1,5
#pragma once |
|
void process_macro(); |
|
void doif(); |
void doifdef(); |