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Rev 588 → Rev 589

/trunk/or1200/rtl/verilog/or1200_du.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
226,7 → 229,7
except_stop = 14'b0000_0000_0000;
casex (du_except)
13'b1_xxxx_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_HPINTE] = 1'b1;
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
end
13'b0_1xxx_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
249,7 → 252,7
13'b0_0000_0001_xxxx:
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
13'b0_0000_0000_1xxx:
except_stop[`OR1200_DU_DRR_LPINTE] = 1'b1;
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
13'b0_0000_0000_01xx: begin
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
end
273,17 → 276,13
//
always @(posedge clk or posedge rst)
if (rst)
// SIMON
// dbg_bp_r <= #1 1'b1;
dbg_bp_r <= #1 1'b0;
else if (!ex_freeze)
dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
// DAMJAN | ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
// DAMJAN | ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[0]) & (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
;
/trunk/or1200/rtl/verilog/or1200_defines.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/01/14 09:44:12 lampret
// Default ASIC configuration does not sample WB inputs.
//
// Revision 1.3 2002/01/08 00:51:08 lampret
// Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be.
//
289,7 → 292,7
//
// Define to use fast (and bigger) version of mem2reg aligner
//
`define OR1200_MEM2REG_FAST
//`define OR1200_MEM2REG_FAST
 
//
// Simulate l.div and l.divu
499,10 → 502,10
`define OR1200_EXCEPT_RANGE `OR1200_EXCEPT_WIDTH'hb
`define OR1200_EXCEPT_ITLBMISS `OR1200_EXCEPT_WIDTH'ha
`define OR1200_EXCEPT_DTLBMISS `OR1200_EXCEPT_WIDTH'h9
`define OR1200_EXCEPT_HPINT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_INT `OR1200_EXCEPT_WIDTH'h8
`define OR1200_EXCEPT_ILLEGAL `OR1200_EXCEPT_WIDTH'h7
`define OR1200_EXCEPT_ALIGN `OR1200_EXCEPT_WIDTH'h6
`define OR1200_EXCEPT_LPINT `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_TICK `OR1200_EXCEPT_WIDTH'h5
`define OR1200_EXCEPT_IPF `OR1200_EXCEPT_WIDTH'h4
`define OR1200_EXCEPT_DPF `OR1200_EXCEPT_WIDTH'h3
`define OR1200_EXCEPT_BUSERR `OR1200_EXCEPT_WIDTH'h2
557,10 → 560,10
//
// SR bits
//
`define OR1200_SR_WIDTH 10
`define OR1200_SR_SUPV 0
`define OR1200_SR_EXR 1
`define OR1200_SR_EIR 2
`define OR1200_SR_WIDTH 16
`define OR1200_SR_SM 0
`define OR1200_SR_TEE 1
`define OR1200_SR_IEE 2
`define OR1200_SR_DCE 3
`define OR1200_SR_ICE 4
`define OR1200_SR_DME 5
568,6 → 571,13
`define OR1200_SR_LEE 7
`define OR1200_SR_CE 8
`define OR1200_SR_F 9
`define OR1200_SR_CY 10 // Unused
`define OR1200_SR_OV 11 // Unused
`define OR1200_SR_OVE 12 // Unused
`define OR1200_SR_DSX 13 // Unused
`define OR1200_SR_EPH 14
`define OR1200_SR_FO 15
`define OR1200_SR_CID 31:28 // Unimplemented
 
// Bits that define offset inside the group
`define OR1200_SPROFS_BITS 10:0
820,10 → 830,10
`define OR1200_DU_DSR_BUSEE 1
`define OR1200_DU_DSR_DPFE 2
`define OR1200_DU_DSR_IPFE 3
`define OR1200_DU_DSR_LPINTE 4
`define OR1200_DU_DSR_TTE 4
`define OR1200_DU_DSR_AE 5
`define OR1200_DU_DSR_IIE 6
`define OR1200_DU_DSR_HPINTE 7
`define OR1200_DU_DSR_IE 7
`define OR1200_DU_DSR_DME 8
`define OR1200_DU_DSR_IME 9
`define OR1200_DU_DSR_RE 10
836,10 → 846,10
`define OR1200_DU_DRR_BUSEE 1
`define OR1200_DU_DRR_DPFE 2
`define OR1200_DU_DRR_IPFE 3
`define OR1200_DU_DRR_LPINTE 4
`define OR1200_DU_DRR_TTE 4
`define OR1200_DU_DRR_AE 5
`define OR1200_DU_DRR_IIE 6
`define OR1200_DU_DRR_HPINTE 7
`define OR1200_DU_DRR_IE 7
`define OR1200_DU_DRR_DME 8
`define OR1200_DU_DRR_IME 9
`define OR1200_DU_DRR_RE 10
871,7 → 881,6
 
// Address offsets of PIC registers inside PIC group
`define OR1200_PIC_OFS_PICMR 2'd0
`define OR1200_PIC_OFS_PICPR 2'd1
`define OR1200_PIC_OFS_PICSR 2'd2
 
// Position of offset bits inside SPR address
879,7 → 888,6
 
// Define if you want these PIC registers to be implemented
`define OR1200_PIC_PICMR
`define OR1200_PIC_PICPR
`define OR1200_PIC_PICSR
 
// Define if reading PIC registers is allowed
/trunk/or1200/rtl/verilog/or1200_sprs.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12 2001/11/23 21:42:31 simons
// Program counter divided to PPC and NPC.
//
256,7 → 259,7
//
// What to write into SR
//
assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : spr_dataout[`OR1200_SR_WIDTH-1:0];
assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dataout[`OR1200_SR_WIDTH-2:0]};
 
//
// Selects for system SPRs
303,32 → 306,16
if (rst)
sr <= #1 `OR1200_SR_WIDTH'b011;
else if (except_started) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: exception started. SR[SUPV] set and SR[EIR] cleared.");
// synopsys translate_on
`endif
sr[`OR1200_SR_SUPV] <= #1 1'b1;
sr[`OR1200_SR_EIR] <= #1 1'b0;
sr[`OR1200_SR_SM] <= #1 1'b1;
sr[`OR1200_SR_TEE] <= #1 1'b0;
sr[`OR1200_SR_IEE] <= #1 1'b0;
sr[`OR1200_SR_DME] <= #1 1'b0;
sr[`OR1200_SR_IME] <= #1 1'b0;
end
else if (sr_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: writing into SR register: %h", spr_dataout);
// synopsys translate_on
`endif
sr <= #1 {to_sr[`OR1200_SR_WIDTH-1:2], 1'b1, to_sr[0]};
end
else if (flag_we) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
$display(" INFO: setting SR[F] bit: %b", flagforw);
// synopsys translate_on
`endif
else if (sr_we)
sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
else if (flag_we)
sr[`OR1200_SR_F] <= #1 flagforw;
end
 
//
// MTSPR/MFSPR interface
/trunk/or1200/rtl/verilog/or1200_cpu.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
123,8 → 126,8
dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
dmmu_en,
 
// Interrupt exceptions
int_high, int_low,
// Interrupt & tick exceptions
sig_int, sig_tick,
 
// SPR interface
supv, spr_addr, spr_dataout, spr_dat_pic, spr_dat_tt, spr_dat_pm,
220,8 → 223,8
//
// Interrupt exceptions
//
input int_high;
input int_low;
input sig_int;
input sig_tick;
 
//
// Internal wires
343,7 → 346,7
//
// SUPV bit
//
assign supv = sr[`OR1200_SR_SUPV];
assign supv = sr[`OR1200_SR_SM];
 
//
// Instantiation of instruction fetch block
364,6 → 367,7
.branch_op(branch_op),
.except_type(except_type),
.except_start(except_start),
.except_prefix(sr[`OR1200_SR_EPH]),
.branch_addrofs(branch_addrofs),
.lr_restor(operand_b),
.flag(flag),
453,7 → 457,7
or1200_rf or1200_rf(
.clk(clk),
.rst(rst),
.supv(sr[`OR1200_SR_SUPV]),
.supv(sr[`OR1200_SR_SM]),
.wb_freeze(wb_freeze),
.addrw(rf_addrw),
.dataw(rf_dataw),
595,6 → 599,7
.lsu_stall(lsu_stall),
.lsu_unstall(lsu_unstall),
.du_stall(du_stall),
.flushpipe(flushpipe),
.except_align(except_align),
.except_dtlbmiss(except_dtlbmiss),
.except_dmmufault(except_dmmufault),
666,12 → 671,12
.sig_range(1'b0),
.sig_dtlbmiss(except_dtlbmiss),
.sig_dmmufault(except_dmmufault),
.sig_inthigh(int_high),
.sig_int(sig_int),
.sig_syscall(sig_syscall),
.sig_trap(sig_trap),
.sig_itlbmiss(except_itlbmiss),
.sig_immufault(except_immufault),
.sig_intlow(int_low),
.sig_tick(sig_tick),
.branch_taken(branch_taken),
.id_freeze(id_freeze),
.ex_freeze(ex_freeze),
685,12 → 690,9
.except_start(except_start),
.except_started(except_started),
.except_stop(except_stop),
.wb_pc(spr_dat_ppc),
.ex_pc(spr_dat_npc),
.id_pc(),
// .wb_pc(),
// .ex_pc(spr_dat_ppc),
// .id_pc(spr_dat_npc),
.has_dslot(has_dslot),
.spr_dat_ppc(spr_dat_ppc),
.spr_dat_npc(spr_dat_npc),
 
.datain(operand_b),
.du_dsr(du_dsr),
/trunk/or1200/rtl/verilog/or1200_pic.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
69,7 → 72,7
module or1200_pic(
// RISC Internal Interface
clk, rst, spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
pic_wakeup, int_low, int_high,
pic_wakeup, int,
// PIC Interface
pic_int
86,10 → 89,8
input [31:0] spr_dat_i; // SPR Write Data
output [31:0] spr_dat_o; // SPR Read Data
output pic_wakeup; // Wakeup to the PM
output int_low; // Low priority interrupt
output int; // interrupt
// exception request
output int_high; // High priority interrupt
// exception request
 
//
// PIC Interface
108,15 → 109,6
`endif
 
//
// PIC Priority Register bits (or no register)
//
`ifdef OR1200_PIC_PICPR
reg [`OR1200_PIC_INTS-1:2] picpr; // PICPR bits
`else
wire [`OR1200_PIC_INTS-1:2] picpr; // No PICPR register
`endif
 
//
// PIC Status Register bits (or no register)
//
`ifdef OR1200_PIC_PICSR
129,7 → 121,6
// Internal wires & regs
//
wire picmr_sel; // PICMR select
wire picpr_sel; // PICPR select
wire picsr_sel; // PICSR select
wire [`OR1200_PIC_INTS-1:0] um_ints;// Unmasked interrupts
reg [31:0] spr_dat_o; // SPR data out
138,7 → 129,6
// PIC registers address decoder
//
assign picmr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICMR)) ? 1'b1 : 1'b0;
assign picpr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICPR)) ? 1'b1 : 1'b0;
assign picsr_sel = (spr_cs && (spr_addr[`OR1200_PICOFS_BITS] == `OR1200_PIC_OFS_PICSR)) ? 1'b1 : 1'b0;
 
//
147,30 → 137,15
`ifdef OR1200_PIC_PICMR
always @(posedge clk or posedge rst)
if (rst)
// picmr <= {`OR1200_PIC_INTS-2{1'b0}};
picmr <= {1'b1, {`OR1200_PIC_INTS-3{1'b0}}};
else if (picmr_sel && spr_write) begin
picmr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
end
`else
assign picpr = (`OR1200_PIC_INTS)'b1;
assign picmr = (`OR1200_PIC_INTS)'b1;
`endif
 
//
// Write to PICPR
//
`ifdef OR1200_PIC_PICPR
always @(posedge clk or posedge rst)
if (rst)
picpr <= {`OR1200_PIC_INTS-2{1'b0}};
else if (picpr_sel && spr_write) begin
picpr <= #1 spr_dat_i[`OR1200_PIC_INTS-1:2];
end
`else
assign picpr = 0;
`endif
 
//
// Write to PICSR, both CPU and external ints
//
`ifdef OR1200_PIC_PICSR
188,7 → 163,7
//
// Read PIC registers
//
always @(spr_addr or picmr or picpr or picsr)
always @(spr_addr or picmr or picsr)
case (spr_addr[`OR1200_PICOFS_BITS]) // synopsys full_case parallel_case
`ifdef OR1200_PIC_READREGS
`OR1200_PIC_OFS_PICMR: begin
197,13 → 172,7
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
`OR1200_PIC_OFS_PICPR: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = {picpr, 2'b0};
`ifdef OR1200_PIC_UNUSED_ZERO
spr_dat_o[31:`OR1200_PIC_INTS] = {32-`OR1200_PIC_INTS{1'b0}};
`endif
end
`endif
default: begin
spr_dat_o[`OR1200_PIC_INTS-1:0] = picsr;
`ifdef OR1200_PIC_UNUSED_ZERO
218,28 → 187,22
assign um_ints = pic_int & {picmr, 2'b11};
 
//
// Generate int_low
// Generate int
//
assign int_low = (um_ints & {~picpr, 2'b10}) ? 1'b1 : 1'b0;
assign int = |um_ints;
 
//
// Generate int_high
// Assert pic_wakeup when int is asserted
//
assign int_high = (um_ints & {picpr, 2'b01}) ? 1'b1 : 1'b0;
assign pic_wakeup = int;
 
//
// Assert pic_wakeup when either intlow or int_high is asserted
//
assign pic_wakeup = int_low | int_high;
 
`else
 
//
// When PIC is not implemented, drive all outputs as would when PIC is disabled
//
assign int_low = pic_int[1];
assign int_high = pic_int[0];
assign pic_wakeup= int_low | int_high;
assign int = pic_int[1] | pic_int[0];
assign pic_wakeup= int;
 
//
// Read PIC registers
/trunk/or1200/rtl/verilog/or1200_except.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4 2002/01/14 21:11:50 lampret
// Changed alignment exception EPCR. Not tested yet.
//
// Revision 1.3 2002/01/14 19:09:57 lampret
// Fixed order of syscall and range exceptions.
//
114,11 → 117,11
 
// Internal i/f
sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
sig_inthigh, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_intlow,
sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
except_started, except_stop,
wb_pc, ex_pc, id_pc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
except_started, except_stop, has_dslot,
spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
esr, sr, lsu_addr
);
 
134,12 → 137,12
input sig_range;
input sig_dtlbmiss;
input sig_dmmufault;
input sig_inthigh;
input sig_int;
input sig_syscall;
input sig_trap;
input sig_itlbmiss;
input sig_immufault;
input sig_intlow;
input sig_tick;
input branch_taken;
input id_freeze;
input ex_freeze;
164,9 → 167,9
output except_start;
output except_started;
output [12:0] except_stop;
output [31:0] wb_pc;
output [31:0] ex_pc;
output [31:0] id_pc;
input has_dslot;
output [31:0] spr_dat_ppc;
output [31:0] spr_dat_npc;
 
//
// Internal regs and wires
178,8 → 181,8
reg [31:0] epcr;
reg [31:0] eear;
reg [`OR1200_SR_WIDTH-1:0] esr;
reg [3:0] id_exceptflags;
reg [3:0] ex_exceptflags;
reg [2:0] id_exceptflags;
reg [2:0] ex_exceptflags;
reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
reg extend_flush;
reg extend_flush_last;
189,9 → 192,10
wire except_started;
wire [12:0] except_trig;
wire except_flushpipe;
reg [2:0] delayed_eir;
wire inthigh_pending;
wire intlow_pending;
reg [2:0] delayed_iee;
reg [2:0] delayed_tee;
wire int_pending;
wire tick_pending;
 
//
// Simple combinatorial logic
198,40 → 202,42
//
assign except_started = extend_flush & except_start;
assign lr_sav = ex_pc[31:2];
assign spr_dat_ppc = wb_pc;
assign spr_dat_npc = has_dslot ? ex_pc : id_pc;
//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
assign inthigh_pending = sig_inthigh & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign intlow_pending = sig_intlow & sr[`OR1200_SR_EIR] & delayed_eir[2] & ~ex_freeze & ~branch_taken & ~ex_dslot & ~delayed1_ex_dslot & ~delayed2_ex_dslot;
assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
 
//
// Order defines exception detection priority
//
assign except_trig = {
inthigh_pending & ~du_dsr[`OR1200_DU_DSR_HPINTE],
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[3] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_LPINTE],
tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
};
assign except_stop = {
inthigh_pending & du_dsr[`OR1200_DU_DSR_HPINTE],
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[3] & du_dsr[`OR1200_DU_DSR_BUSEE],
int_pending & du_dsr[`OR1200_DU_DSR_IE],
ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
sig_align & du_dsr[`OR1200_DU_DSR_AE],
sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_LPINTE],
tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
sig_range & du_dsr[`OR1200_DU_DSR_RE],
sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
243,35 → 249,51
always @(posedge clk or posedge rst) begin
if (rst) begin
id_pc <= #1 32'd0;
id_exceptflags <= #1 4'b0000;
id_exceptflags <= #1 3'b000;
end
else if (flushpipe) begin
id_pc <= #1 32'h0000_0000;
id_exceptflags <= #1 4'b0000;
id_exceptflags <= #1 3'b000;
end
else if (!id_freeze) begin
id_pc <= #1 if_pc;
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault, intlow_pending };
id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
end
end
 
//
// delayed_eir
// delayed_iee
//
// SR[EIR] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_eir
// together with SR[EIR] enables interrupts once
// SR[IEE] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_iee
// together with SR[IEE] enables interrupts once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
if (rst)
delayed_eir <= #1 3'b000;
else if (!sr[`OR1200_SR_EIR])
delayed_eir <= #1 3'b000;
delayed_iee <= #1 3'b000;
else if (!sr[`OR1200_SR_IEE])
delayed_iee <= #1 3'b000;
else
delayed_eir <= #1 {delayed_eir[1:0], 1'b1};
delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
 
//
// delayed_tee
//
// SR[TEE] should not enable tick exceptions right away
// when it is restored with l.rfe. Instead delayed_tee
// together with SR[TEE] enables tick exceptions once
// pipeline is again ready.
//
always @(posedge rst or posedge clk)
if (rst)
delayed_tee <= #1 3'b000;
else if (!sr[`OR1200_SR_TEE])
delayed_tee <= #1 3'b000;
else
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or posedge rst) begin
278,7 → 300,7
if (rst) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 32'd0;
ex_exceptflags <= #1 4'b0000;
ex_exceptflags <= #1 3'b000;
delayed1_ex_dslot <= #1 1'b0;
delayed2_ex_dslot <= #1 1'b0;
end
285,7 → 307,7
else if (flushpipe) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 32'h0000_0000;
ex_exceptflags <= #1 4'b0000;
ex_exceptflags <= #1 3'b000;
delayed1_ex_dslot <= #1 1'b0;
delayed2_ex_dslot <= #1 1'b0;
end
292,7 → 314,7
else if (!ex_freeze & id_freeze) begin
ex_dslot <= #1 1'b0;
ex_pc <= #1 id_pc;
ex_exceptflags <= #1 4'b0000;
ex_exceptflags <= #1 3'b000;
delayed1_ex_dslot <= #1 ex_dslot;
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
end
347,7 → 369,7
extend_flush <= #1 1'b0;
epcr <= #1 32'b0;
eear <= #1 32'b0;
esr <= #1 `OR1200_SR_WIDTH'b010;
esr <= #1 `OR1200_SR_WIDTH'b001;
extend_flush_last <= #1 1'b0;
end
else begin
388,7 → 410,7
esr <= #1 sr;
casex (except_trig)
13'b1_xxxx_xxxx_xxxx: begin
except_type <= #1 `OR1200_EXCEPT_HPINT;
except_type <= #1 `OR1200_EXCEPT_INT;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
13'b0_1xxx_xxxx_xxxx: begin
431,7 → 453,7
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
end
13'b0_0000_0000_1xxx: begin
except_type <= #1 `OR1200_EXCEPT_LPINT;
except_type <= #1 `OR1200_EXCEPT_TICK;
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
end
13'b0_0000_0000_01xx: begin
460,7 → 482,7
if (eear_we)
eear <= #1 datain;
if (esr_we)
esr <= #1 {datain[`OR1200_SR_WIDTH-1:2], 1'b1, datain[0]};
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
end
`OR1200_EXCEPTFSM_FLU1:
// if (!if_stall & !id_freeze)
/trunk/or1200/rtl/verilog/or1200_genpc.v
45,6 → 45,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/01/14 06:18:22 lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
85,7 → 88,7
icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
 
// Internal i/f
branch_op, except_type,
branch_op, except_type, except_prefix,
branch_addrofs, lr_restor, flag, taken, except_start,
binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
genpc_freeze, flushpipe
119,6 → 122,7
//
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
input except_prefix;
input [31:2] branch_addrofs;
input [31:0] lr_restor;
input flag;
158,7 → 162,7
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i) begin
or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case
{2'b00, `OR1200_BRANCHOP_NOP}: begin
pc = {pcreg + 'd1, 2'b0};
244,7 → 248,7
$display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
pc = { 20'h0_0000, except_type, 8'h00};
pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
taken = 1'b1;
end
default: begin
/trunk/or1200/rtl/verilog/or1200_top.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.13 2001/11/23 08:38:51 lampret
// Changed DSR/DRR behavior and exception detection.
//
295,9 → 298,7
//
wire [dw-1:0] spr_dat_pic;
wire pic_wakeup;
wire int_low;
wire int_high;
wire int_high_tt;
wire sig_int;
 
//
// Connection between CPU and PM
308,7 → 309,7
// CPU and TT
//
wire [dw-1:0] spr_dat_tt;
wire tt_int;
wire sig_tick;
 
//
// Debug port and caches/MMUs
328,11 → 329,6
wire [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
 
//
// Assignments
//
assign int_high_tt = int_high | tt_int;
 
//
// Instantiation of Instruction WISHBONE BIU
//
or1200_wb_biu iwb_biu(
537,8 → 533,8
.dmmu_en(dmmu_en),
 
// Connection PIC and CPU's EXCEPT
.int_high(int_high_tt),
.int_low(int_low),
.sig_int(sig_int),
.sig_tick(sig_tick),
 
// SPRs
.supv(supv),
689,8 → 685,7
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_pic),
.pic_wakeup(pic_wakeup),
.int_low(int_low),
.int_high(int_high),
.int(sig_int),
 
// PIC Interface
.pic_int(pic_ints_i)
708,7 → 703,7
.spr_addr(spr_addr),
.spr_dat_i(spr_dat_cpu),
.spr_dat_o(spr_dat_tt),
.int(tt_int)
.int(sig_tick)
);
 
//
/trunk/or1200/rtl/verilog/or1200_lsu.v
44,6 → 44,9
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9 2001/11/30 18:59:47 simons
// *** empty log message ***
//
75,7 → 78,7
 
// Internal i/f
addrbase, addrofs, lsu_op, lsu_datain, lsu_dataout, lsu_stall, lsu_unstall,
du_stall, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
du_stall, flushpipe, except_align, except_dtlbmiss, except_dmmufault, except_dbuserr,
 
// External i/f to DC
dcpu_adr_o, dcpu_cyc_o, dcpu_stb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o, dcpu_dat_o,
106,6 → 109,7
output lsu_stall;
output lsu_unstall;
input du_stall;
input flushpipe;
output except_align;
output except_dtlbmiss;
output except_dmmufault;

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