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https://opencores.org/ocsvn/can/can/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 59 to Rev 60
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Rev 59 → Rev 60
/trunk/bench/verilog/can_testbench.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.30 2003/03/12 04:16:40 mohor |
// 8051 interface added (besides WISHBONE interface). Selection is made in |
// can_defines.v file. |
// |
// Revision 1.29 2003/03/05 15:33:37 mohor |
// tx_o is now tristated signal. tx_oen and tx_o combined together. |
// |
177,8 → 181,8
`else |
reg rst_i; |
reg ale_i; |
reg rd_i; // active low |
reg wr_i; // active low |
reg rd_i; |
reg wr_i; |
wire [7:0] port_0; |
wire [7:0] port_0_i; |
reg [7:0] port_0_o; |
220,8 → 224,8
`else |
.rst_i(rst_i), |
.ale_i(ale_i), |
.rd_i(rd_i), // active low |
.wr_i(wr_i), // active low |
.rd_i(rd_i), |
.wr_i(wr_i), |
.port_0_i(port_0), |
`endif |
.cs_can(cs_can), |
279,8 → 283,8
`else |
rst_i = 1'b0; |
ale_i = 1'b0; |
rd_i = 1'b1; // active low |
wr_i = 1'b1; // active low |
rd_i = 1'b0; |
wr_i = 1'b0; |
port_0_o = 8'h0; |
port_0_en = 0; |
port_free = 1; |
1638,11 → 1642,11
ale_i = 0; |
#90; // 73 - 103 ns |
port_0_en = 0; |
rd_i = 0; // active low |
rd_i = 1; |
#158; |
$display("(%0t) Reading register [%0d] = 0x%0x", $time, can_testbench.i_can_top.addr_latched, port_0_i); |
#1; |
rd_i = 1; // active low |
rd_i = 0; |
cs_can = 0; |
port_free = 1; |
end |
1692,9 → 1696,9
ale_i = 0; |
#90; // 73 - 103 ns |
port_0_o = reg_data; |
wr_i = 0; // active low |
wr_i = 1; |
#158; |
wr_i = 1; // active low |
wr_i = 0; |
port_0_en = 0; |
cs_can = 0; |
port_free = 1; |
/trunk/rtl/verilog/can_top.v
50,6 → 50,10
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.25 2003/03/12 04:17:36 mohor |
// 8051 interface added (besides WISHBONE interface). Selection is made in |
// can_defines.v file. |
// |
// Revision 1.24 2003/03/10 17:24:40 mohor |
// wire declaration added. |
// |
152,8 → 156,8
`else |
rst_i, |
ale_i, |
rd_i, // active low |
wr_i, // active low |
rd_i, |
wr_i, |
port_0_i, |
`endif |
cs_can, |
190,8 → 194,8
`else |
input rst_i; |
input ale_i; |
input rd_i; // active low |
input wr_i; // active low |
input rd_i; |
input wr_i; |
inout [7:0] port_0_i; |
|
reg [7:0] addr_latched; |
714,14 → 718,14
end |
|
|
assign cs = ((~wr_i) & wr_i_q) | ((~rd_i) & rd_i_q) & cs_can; |
assign cs = (wr_i & (~wr_i_q)) | (rd_i & (~rd_i_q)) & cs_can; |
|
|
assign rst = rst_i; |
assign we = ~wr_i; |
assign we = wr_i; |
assign addr = addr_latched; |
assign data_in = port_0_i; |
assign port_0_i = (cs_can & (~rd_i))? data_out : 8'hz; |
assign port_0_i = (cs_can & rd_i)? data_out : 8'hz; |
|
`endif |
|