URL
https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
Subversion Repositories or1k_old
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 59 to Rev 60
- ↔ Reverse comparison
Rev 59 → Rev 60
/trunk/or1ksim/support/dumpverilog.h
1,7 → 1,8
#define DW 32 /* Data width of memory model generated by dumpverilog in bits */ |
#define DWQ (DW/8) /* Same as DW but units are bytes */ |
#define DISWIDTH 20 /* Width of disassembled message in bytes */ |
|
#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR) "\n\ |
#define OR1K_MEM_VERILOG_HEADER(MODNAME, FROMADDR, TOADDR, DISWIDTH) "\n\ |
`include \"general.h\"\n\n\ |
`timescale 1ns/100ps\n\n\ |
// Simple dw-wide Sync SRAM with initial content generated by or1ksim.\n\ |
19,21 → 20,21
input ce;\n\ |
input we;\n\n\ |
reg [dw-1:0] mem [amax:amin];\n\ |
reg [199:0] dis [amax:amin];\n\ |
reg [%d-1:0] dis [amax:amin];\n\ |
reg [dw-1:0] dataout;\n\ |
tri [dw-1:0] data = (ce && ~we) ? dataout : 'bz;\n\n\ |
initial begin\n", MODNAME, FROMADDR, TOADDR |
initial begin\n", MODNAME, FROMADDR, TOADDR, DISWIDTH |
|
#define OR1K_MEM_VERILOG_FOOTER "\n\ |
end\n\n\ |
always @(posedge clk) begin\n\ |
if (ce && ~we) begin\n\ |
dataout = #1 mem[addr];\n\ |
dataout <= #1 mem[addr];\n\ |
$display(\"or1k_mem: reading mem[%%0d]:%%h dis: %%0s\", addr, dataout, dis[addr]);\n\ |
end else\n\ |
if (ce && we) begin\n\ |
mem[addr] = data;\n\ |
dis[addr] = \"(data)\";\n\ |
mem[addr] <= #1 data;\n\ |
dis[addr] <= #1 \"(data)\";\n\ |
$display(\"or1k_mem: writing mem[%%0d]:%%h dis: %%0s\", addr, mem[addr], dis[addr]);\n\ |
end\n\ |
end\n\n\ |
/trunk/or1ksim/support/dumpverilog.c
43,9 → 43,10
{ |
unsigned int i, done = 0; |
struct label_entry *tmp; |
char dis[DISWIDTH + 100]; |
|
printf("// This file was generated by or1ksim %s\n", rcsrev); |
printf(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ)); |
printf(OR1K_MEM_VERILOG_HEADER(verilog_modname, from/DWQ, to/DWQ, (DISWIDTH*8))); |
|
for(i = from; i < to && i < (MEMORY_START + MEMORY_LEN); i++) { |
if (mem[i].insn) { |
56,14 → 57,18
printf("\n\tmem['h%x] = %d'h%.2x%.2x", i/DWQ, DW, mem[i].data, mem[i+1].data); |
printf("%.2x%.2x;", mem[i+2].data, mem[i+3].data); |
if (mem[i].insn) |
printf("\n\tdis['h%x] = {\"%s\t%s\"", i/DWQ, mem[i].insn->insn, mem[i].insn->op1); |
sprintf(dis, "%s %s", mem[i].insn->insn, mem[i].insn->op1); |
if (strlen(mem[i].insn->op2)) |
printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op2); |
sprintf(dis, "%s%s%s", dis, OPERAND_DELIM, mem[i].insn->op2); |
if (strlen(mem[i].insn->op3)) |
printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op3); |
sprintf(dis, "%s%s%s", dis, OPERAND_DELIM, mem[i].insn->op3); |
if (strlen(mem[i].insn->op4)) |
printf(",\"%s%s\"", OPERAND_DELIM, mem[i].insn->op4); |
printf("};"); |
sprintf(dis, "%s%s%s", dis, OPERAND_DELIM, mem[i].insn->op4); |
if (strlen(dis) < DISWIDTH) |
memset(dis + strlen(dis), ' ', DISWIDTH); |
dis[DISWIDTH] = '\0'; |
printf("\n\tdis['h%x] = {\"%s\"};", i/DWQ, dis); |
dis[0] = '\0'; |
i += (insn_len(mem[i].insn->insn) - 1); |
} else |
{ |