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/thor/trunk/FT64v7/doc/FT64v7.docx
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Index: thor/trunk/FT64v7/rtl/common/FT64_AMO_alu.v
===================================================================
--- thor/trunk/FT64v7/rtl/common/FT64_AMO_alu.v (nonexistent)
+++ thor/trunk/FT64v7/rtl/common/FT64_AMO_alu.v (revision 60)
@@ -0,0 +1,244 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2018 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+// FT64_AMO_alu.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_BMM.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_EvalBranch.v
+// - FT64 branch evaluation
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_FCU_Calc.v
+// - FT64 flow control calcs
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_InsLength.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_RMW_alu.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_RSB.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_alu.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_bitfield.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_config.vh
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_dcache.v
+// - a simple direct mapped cache
+// - three cycle latency
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_defines.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_cache.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_idecoder.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_iexpander.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_ipt.v
+// - 64 bit CPU inverted page table memory management unit
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_MMU.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_MPU.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_pit.v
+// - programmable interval timer
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_pmmu.v
+// - 64 bit CPU paged memory management unit
+// - 512 entry TLB, 8 way associative
+// - variable page table depth
+// - address short-cutting for larger page sizes (8MB)
+// - hardware clearing of access bit
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_shift.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_shiftb.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_shiftc.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_shifth.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @opencores.org
+// ||
+//
+// BCDMath.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// lfsr.v
+// - linear feedback shift register
+// - parameterized
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @opencores.org
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @opencores.org
+//
+//
+// vtdl - variable tap delay line
+// (dynamic shift register)
+//
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64.v
+// Features include:
+// - 16/32/48 bit instructions
+// - vector instruction set,
+// - SIMD instructions
+// - data width of 64 bits
+// - 32 general purpose registers
+// - 32 floating point registers
+// - 32 vector registers, length 63
+// - powerful branch prediction
+// - branch target buffer (BTB)
+// - return address predictor (RSB)
+// - bus interface unit
+// - instruction and data caches
+// - fine-grained simultaneous multi-threading (SMT)
+// - bus randomizer on exceptional conditions
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see 1)
+ $display("%d %h %h %c%h %o #",
+ dram1, dram1_addr, dram1_data, (IsFlowCtrl(dram1_instr) ? 98 : (IsMem(dram1_instr)) ? 109 : 97),
+ dram1_instr, dram1_id);
+ if (`NUM_MEM > 2)
+ $display("%d %h %h %c%h %o #",
+ dram2, dram2_addr, dram2_data, (IsFlowCtrl(dram2_instr) ? 98 : (IsMem(dram2_instr)) ? 109 : 97),
+ dram2_instr, dram2_id);
+ $display("%d %h %o %h #", dramA_v, dramA_bus, dramA_id, dramA_exc);
+ if (`NUM_MEM > 1)
+ $display("%d %h %o %h #", dramB_v, dramB_bus, dramB_id, dramB_exc);
+ if (`NUM_MEM > 2)
+ $display("%d %h %o %h #", dramC_v, dramC_bus, dramC_id, dramC_exc);
+ $display("ALU");
+ $display("%d %h %h %h %c%h %o %h #",
+ alu0_dataready, alu0_argI, alu0_argA, alu0_argB,
+ (IsFlowCtrl(alu0_instr) ? 98 : IsMem(alu0_instr) ? 109 : 97),
+ alu0_instr, alu0_sourceid, alu0_pc);
+ $display("%d %h %o 0 #", alu0_v, alu0_bus, alu0_id);
+ if (`NUM_ALU > 1) begin
+ $display("%d %h %h %h %c%h %o %h #",
+ alu1_dataready, alu1_argI, alu1_argA, alu1_argB,
+ (IsFlowCtrl(alu1_instr) ? 98 : IsMem(alu1_instr) ? 109 : 97),
+ alu1_instr, alu1_sourceid, alu1_pc);
+ $display("%d %h %o 0 #", alu1_v, alu1_bus, alu1_id);
+ end
+ $display("FCU");
+ $display("%d %h %h %h %h %c%c #", fcu_v, fcu_bus, fcu_argI, fcu_argA, fcu_argB, fcu_takb?"T":"-", fcu_pt?"T":"-");
+ $display("%c %h %h %h %h #", fcu_branchmiss?"m":" ", fcu_sourceid, fcu_misspc, fcu_nextpc, fcu_brdisp);
+ $display("Commit");
+ $display("0: %c %h %o %d #", commit0_v?"v":" ", commit0_bus, commit0_id, commit0_tgt[4:0]);
+ $display("1: %c %h %o %d #", commit1_v?"v":" ", commit1_bus, commit1_id, commit1_tgt[4:0]);
+ $display("instructions committed: %d valid committed: %d ticks: %d ", CC, I, tick);
+ $display("Write Buffer:");
+ for (n = `WB_DEPTH-1; n >= 0; n = n - 1)
+ $display("%c adr: %h dat: %h", wb_v[n]?" ":"*", wb_addr[n], wb_data[n]);
+ $display("Write merges: %d", wb_merges);
+`endif // SIM
+
+//
+// $display("\n\n\n\n\n\n\n\n");
+// $display("TIME %0d", $time);
+// $display(" pc0=%h", pc0);
+// $display(" pc1=%h", pc1);
+// $display(" reg0=%h, v=%d, src=%o", rf[0], rf_v[0], rf_source[0]);
+// $display(" reg1=%h, v=%d, src=%o", rf[1], rf_v[1], rf_source[1]);
+// $display(" reg2=%h, v=%d, src=%o", rf[2], rf_v[2], rf_source[2]);
+// $display(" reg3=%h, v=%d, src=%o", rf[3], rf_v[3], rf_source[3]);
+// $display(" reg4=%h, v=%d, src=%o", rf[4], rf_v[4], rf_source[4]);
+// $display(" reg5=%h, v=%d, src=%o", rf[5], rf_v[5], rf_source[5]);
+// $display(" reg6=%h, v=%d, src=%o", rf[6], rf_v[6], rf_source[6]);
+// $display(" reg7=%h, v=%d, src=%o", rf[7], rf_v[7], rf_source[7]);
+
+// $display("Fetch Buffers:");
+// $display(" %c%c fbA: v=%d instr=%h pc=%h %c%c fbC: v=%d instr=%h pc=%h",
+// fetchbuf?32:45, fetchbuf?32:62, fetchbufA_v, fetchbufA_instr, fetchbufA_pc,
+// fetchbuf?45:32, fetchbuf?62:32, fetchbufC_v, fetchbufC_instr, fetchbufC_pc);
+// $display(" %c%c fbB: v=%d instr=%h pc=%h %c%c fbD: v=%d instr=%h pc=%h",
+// fetchbuf?32:45, fetchbuf?32:62, fetchbufB_v, fetchbufB_instr, fetchbufB_pc,
+// fetchbuf?45:32, fetchbuf?62:32, fetchbufD_v, fetchbufD_instr, fetchbufD_pc);
+// $display(" branchback=%d backpc=%h", branchback, backpc);
+
+// $display("Instruction Queue:");
+// for (i=0; i<8; i=i+1)
+// $display(" %c%c%d: v=%d done=%d out=%d agen=%d res=%h op=%d bt=%d tgt=%d a1=%h (v=%d/s=%o) a2=%h (v=%d/s=%o) im=%h pc=%h exc=%h",
+// (i[`QBITS]==heads[0])?72:32, (i[`QBITS]==tail0)?84:32, i,
+// iqentry_v[i], iqentry_done[i], iqentry_out[i], iqentry_agen[i], iqentry_res[i], iqentry_op[i],
+// iqentry_bt[i], iqentry_tgt[i], iqentry_a1[i], iqentry_a1_v[i], iqentry_a1_s[i], iqentry_a2[i], iqentry_a2_v[i],
+// iqentry_a2_s[i], iqentry_a0[i], iqentry_pc[i], iqentry_exc[i]);
+
+// $display("Scheduling Status:");
+// $display(" iqentry0 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_0_issue, iqentry_0_islot, iqentry_stomp[0], iqentry_source[0], iqentry_memready[0], iqentry_memissue[0]);
+// $display(" iqentry1 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_1_issue, iqentry_1_islot, iqentry_stomp[1], iqentry_source[1], iqentry_memready[1], iqentry_memissue[1]);
+// $display(" iqentry2 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_2_issue, iqentry_2_islot, iqentry_stomp[2], iqentry_source[2], iqentry_memready[2], iqentry_memissue[2]);
+// $display(" iqentry3 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_3_issue, iqentry_3_islot, iqentry_stomp[3], iqentry_source[3], iqentry_memready[3], iqentry_memissue[3]);
+// $display(" iqentry4 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_4_issue, iqentry_4_islot, iqentry_stomp[4], iqentry_source[4], iqentry_memready[4], iqentry_memissue[4]);
+// $display(" iqentry5 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_5_issue, iqentry_5_islot, iqentry_stomp[5], iqentry_source[5], iqentry_memready[5], iqentry_memissue[5]);
+// $display(" iqentry6 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_6_issue, iqentry_6_islot, iqentry_stomp[6], iqentry_source[6], iqentry_memready[6], iqentry_memissue[6]);
+// $display(" iqentry7 issue=%d islot=%d stomp=%d source=%d - memready=%d memissue=%b",
+// iqentry_7_issue, iqentry_7_islot, iqentry_stomp[7], iqentry_source[7], iqentry_memready[7], iqentry_memissue[7]);
+
+// $display("ALU Inputs:");
+// $display(" 0: avail=%d data=%d id=%o op=%d a1=%h a2=%h im=%h bt=%d",
+// alu0_available, alu0_dataready, alu0_sourceid, alu0_op, alu0_argA,
+// alu0_argB, alu0_argI, alu0_bt);
+// $display(" 1: avail=%d data=%d id=%o op=%d a1=%h a2=%h im=%h bt=%d",
+// alu1_available, alu1_dataready, alu1_sourceid, alu1_op, alu1_argA,
+// alu1_argB, alu1_argI, alu1_bt);
+
+// $display("ALU Outputs:");
+// $display(" 0: v=%d bus=%h id=%o bmiss=%d misspc=%h missid=%o",
+// alu0_v, alu0_bus, alu0_id, alu0_branchmiss, alu0_misspc, alu0_sourceid);
+// $display(" 1: v=%d bus=%h id=%o bmiss=%d misspc=%h missid=%o",
+// alu1_v, alu1_bus, alu1_id, alu1_branchmiss, alu1_misspc, alu1_sourceid);
+
+// $display("DRAM Status:");
+// $display(" OUT: v=%d data=%h tgt=%d id=%o", dram_v, dram_bus, dram_tgt, dram_id);
+// $display(" dram0: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
+// dram0, dram0_addr, dram0_data, dram0_op, dram0_tgt, dram0_id);
+// $display(" dram1: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
+// dram1, dram1_addr, dram1_data, dram1_op, dram1_tgt, dram1_id);
+// $display(" dram2: status=%h addr=%h data=%h op=%d tgt=%d id=%o",
+// dram2, dram2_addr, dram2_data, dram2_op, dram2_tgt, dram2_id);
+
+// $display("Commit Buses:");
+// $display(" 0: v=%d id=%o data=%h", commit0_v, commit0_id, commit0_bus);
+// $display(" 1: v=%d id=%o data=%h", commit1_v, commit1_id, commit1_bus);
+
+//
+// $display("Memory Contents:");
+// for (j=0; j<64; j=j+16)
+// $display(" %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h %h",
+// m[j+0], m[j+1], m[j+2], m[j+3], m[j+4], m[j+5], m[j+6], m[j+7],
+// m[j+8], m[j+9], m[j+10], m[j+11], m[j+12], m[j+13], m[j+14], m[j+15]);
+
+ $display("");
+
+ if (|panic) begin
+ $display("");
+ $display("-----------------------------------------------------------------");
+ $display("-----------------------------------------------------------------");
+ $display("--------------- PANIC:%s -----------------", message[panic]);
+ $display("-----------------------------------------------------------------");
+ $display("-----------------------------------------------------------------");
+ $display("");
+ $display("instructions committed: %d", I);
+ $display("total execution cycles: %d", $time / 10);
+ $display("");
+ end
+ if (|panic && ~outstanding_stores) begin
+ $finish;
+ end
+/*
+ for (n = 0; n < QENTRIES; n = n + 1)
+ if (branchmiss) begin
+ if (!setpred[n]) begin
+ iqentry_instr[n][`INSTRUCTION_OP] <= `NOP;
+ iqentry_done[n] <= iqentry_v[n];
+ iqentry_cmt[n] <= iqentry_v[n];
+ end
+ end
+*/
+ rf_source[ 0] <= {`QBIT{1'b1}};
+ rf_source[32] <= {`QBIT{1'b1}};
+ rf_source[64] <= {`QBIT{1'b1}};
+ rf_source[96] <= {`QBIT{1'b1}};
+`ifdef SUPPORTSMT
+ rf_source[128] <= {`QBIT{1'b1}};
+ rf_source[160] <= {`QBIT{1'b1}};
+ rf_source[192] <= {`QBIT{1'b1}};
+ rf_source[224] <= {`QBIT{1'b1}};
+`endif
+
+end // clock domain
+/*
+always @(posedge clk)
+if (rst) begin
+ tail0 <= 3'd0;
+ tail1 <= 3'd1;
+end
+else begin
+if (!branchmiss) begin
+ case({fetchbuf0_v, fetchbuf1_v})
+ 2'b00: ;
+ 2'b01:
+ if (canq1) begin
+ tail0 <= idp1(tail0);
+ tail1 <= idp1(tail1);
+ end
+ 2'b10:
+ if (canq1) begin
+ tail0 <= idp1(tail0);
+ tail1 <= idp1(tail1);
+ end
+ 2'b11:
+ if (canq1) begin
+ if (IsBranch(fetchbuf0_instr) && predict_taken0) begin
+ tail0 <= idp1(tail0);
+ tail1 <= idp1(tail1);
+ end
+ else begin
+ if (vqe < vl || !IsVector(fetchbuf0_instr)) begin
+ if (canq2) begin
+ tail0 <= idp2(tail0);
+ tail1 <= idp2(tail1);
+ end
+ else begin // queued1 will be true
+ tail0 <= idp1(tail0);
+ tail1 <= idp1(tail1);
+ end
+ end
+ end
+ end
+ endcase
+end
+else begin // if branchmiss
+ if (iqentry_stomp[0] & ~iqentry_stomp[7]) begin
+ tail0 <= 3'd0;
+ tail1 <= 3'd1;
+ end
+ else if (iqentry_stomp[1] & ~iqentry_stomp[0]) begin
+ tail0 <= 3'd1;
+ tail1 <= 3'd2;
+ end
+ else if (iqentry_stomp[2] & ~iqentry_stomp[1]) begin
+ tail0 <= 3'd2;
+ tail1 <= 3'd3;
+ end
+ else if (iqentry_stomp[3] & ~iqentry_stomp[2]) begin
+ tail0 <= 3'd3;
+ tail1 <= 3'd4;
+ end
+ else if (iqentry_stomp[4] & ~iqentry_stomp[3]) begin
+ tail0 <= 3'd4;
+ tail1 <= 3'd5;
+ end
+ else if (iqentry_stomp[5] & ~iqentry_stomp[4]) begin
+ tail0 <= 3'd5;
+ tail1 <= 3'd6;
+ end
+ else if (iqentry_stomp[6] & ~iqentry_stomp[5]) begin
+ tail0 <= 3'd6;
+ tail1 <= 3'd7;
+ end
+ else if (iqentry_stomp[7] & ~iqentry_stomp[6]) begin
+ tail0 <= 3'd7;
+ tail1 <= 3'd0;
+ end
+ // otherwise, it is the last instruction in the queue that has been mispredicted ... do nothing
+end
+end
+*/
+
+// Update the write buffer.
+task wb_update;
+input [`QBITS] id;
+input rmw;
+input [7:0] sel;
+input [1:0] ol;
+input [`ABITS] addr;
+input [63:0] data;
+begin
+ if (wbm && wbptr > 1 && wb_addr[wbptr-1][AMSB:3]==addr[AMSB:3]
+ && wb_ol[wbptr-1]==ol && wb_rmw[wbptr-1]==rmw && wb_v[wbptr-1]) begin
+ // The write buffer is always shifted during the bus IDLE state. That means
+ // the data is out of place by a slot. The slot the data is moved from is
+ // invalidated.
+ wb_v[wbptr-2] <= `INV;
+ wb_v[wbptr-1] <= wb_en;
+ wb_id[wbptr-1] <= wb_id[wbptr-1] | (16'd1 << id);
+ wb_rmw[wbptr-1] <= rmw;
+ wb_ol[wbptr-1] <= ol;
+ wb_sel[wbptr-1] <= wb_sel[wbptr-1] | sel;
+ wb_addr[wbptr-1] <= wb_addr[wbptr-1];
+ wb_data[wbptr-1] <= wb_data[wbptr-1];
+ if (sel[0]) wb_data[wbptr-1][ 7: 0] <= data[ 7: 0];
+ if (sel[1]) wb_data[wbptr-1][15: 8] <= data[15: 8];
+ if (sel[2]) wb_data[wbptr-1][23:16] <= data[23:16];
+ if (sel[3]) wb_data[wbptr-1][31:24] <= data[31:24];
+ if (sel[4]) wb_data[wbptr-1][39:32] <= data[39:32];
+ if (sel[5]) wb_data[wbptr-1][47:40] <= data[47:40];
+ if (sel[6]) wb_data[wbptr-1][55:48] <= data[55:48];
+ if (sel[7]) wb_data[wbptr-1][63:56] <= data[63:56];
+ wb_merges <= wb_merges + 32'd1;
+ end
+ else begin
+ wb_v[wbptr] <= wb_en;
+ wb_id[wbptr] <= (16'd1 << id);
+ wb_rmw[wbptr] <= rmw;
+ wb_ol[wbptr] <= ol;
+ wb_sel[wbptr] <= sel;
+ wb_addr[wbptr] <= {addr[AMSB:3],3'b0};
+ wb_data[wbptr] <= data;
+ wbptr <= wbptr + 2'd1;
+ end
+end
+endtask
+
+// Increment the head pointers
+// Also increments the instruction counter
+// Used when instructions are committed.
+// Also clear any outstanding state bits that foul things up.
+//
+task head_inc;
+input [`QBITS] amt;
+begin
+ for (n = 0; n < QENTRIES; n = n + 1)
+ heads[n] <= (heads[n] + amt) % QENTRIES;
+ CC <= CC + amt;
+ if (amt==3'd3) begin
+ I = I + iqentry_v[heads[0]] + iqentry_v[heads[1]] + iqentry_v[heads[2]];
+ iqentry_state[heads[0]] <= IQS_INVALID;
+ iqentry_state[heads[1]] <= IQS_INVALID;
+ iqentry_state[heads[2]] <= IQS_INVALID;
+ iqentry_mem[heads[0]] <= `FALSE;
+ iqentry_mem[heads[1]] <= `FALSE;
+ iqentry_mem[heads[2]] <= `FALSE;
+ iqentry_iv[heads[0]] <= `INV;
+ iqentry_iv[heads[1]] <= `INV;
+ iqentry_iv[heads[2]] <= `INV;
+ iqentry_alu[heads[0]] <= `FALSE;
+ iqentry_alu[heads[1]] <= `FALSE;
+ iqentry_alu[heads[2]] <= `FALSE;
+ for (n = 0; n < QENTRIES; n = n + 1)
+ if (iqentry_v[n])
+ iqentry_sn[n] <= iqentry_sn[n] - (iqentry_v[heads[2]] ? iqentry_sn[heads[2]]
+ : iqentry_v[heads[1]] ? iqentry_sn[heads[1]]
+ : iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
+ : 4'b0);
+ end
+ else if (amt==3'd2) begin
+ I = I + iqentry_v[heads[0]] + iqentry_v[heads[1]];
+ iqentry_state[heads[0]] <= IQS_INVALID;
+ iqentry_state[heads[1]] <= IQS_INVALID;
+ iqentry_mem[heads[0]] <= `FALSE;
+ iqentry_mem[heads[1]] <= `FALSE;
+ iqentry_iv[heads[0]] <= `INV;
+ iqentry_iv[heads[1]] <= `INV;
+ iqentry_alu[heads[0]] <= `FALSE;
+ iqentry_alu[heads[1]] <= `FALSE;
+ for (n = 0; n < QENTRIES; n = n + 1)
+ if (iqentry_v[n])
+ iqentry_sn[n] <= iqentry_sn[n] - (iqentry_v[heads[1]] ? iqentry_sn[heads[1]]
+ : iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
+ : 4'b0);
+ end else if (amt==3'd1) begin
+ I = I + iqentry_v[heads[0]];
+ iqentry_state[heads[0]] <= IQS_INVALID;
+ iqentry_mem[heads[0]] <= `FALSE;
+ iqentry_iv[heads[0]] <= `INV;
+ iqentry_alu[heads[0]] <= `FALSE;
+ for (n = 0; n < QENTRIES; n = n + 1)
+ if (iqentry_v[n])
+ iqentry_sn[n] <= iqentry_sn[n] - (iqentry_v[heads[0]] ? iqentry_sn[heads[0]]
+ : 4'b0);
+ end
+end
+endtask
+
+task setargs;
+input [`QBITS] nn;
+input [`QBITSP1] id;
+input v;
+input [63:0] bus;
+begin
+ if (iqentry_a1_v[nn] == `INV && iqentry_a1_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
+ iqentry_a1[nn] <= bus;
+ iqentry_a1_v[nn] <= `VAL;
+ end
+ if (iqentry_a2_v[nn] == `INV && iqentry_a2_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
+ iqentry_a2[nn] <= bus;
+ iqentry_a2_v[nn] <= `VAL;
+ end
+ if (iqentry_a3_v[nn] == `INV && iqentry_a3_s[nn] == id && iqentry_v[nn] == `VAL && v == `VAL) begin
+ iqentry_a3[nn] <= bus;
+ iqentry_a3_v[nn] <= `VAL;
+ end
+end
+endtask
+
+task setinsn1;
+input [`QBITS] nn;
+input [143:0] bus;
+begin
+ iqentry_iv [nn] <= `VAL;
+// iqentry_Rt [nn] <= bus[`IB_RT];
+// iqentry_Rc [nn] <= bus[`IB_RC];
+// iqentry_Ra [nn] <= bus[`IB_RA];
+ iqentry_a0 [nn] <= bus[`IB_CONST];
+ iqentry_imm [nn] <= bus[`IB_IMM];
+// iqentry_insln[nn] <= bus[`IB_LN];
+`ifndef INLINE_DECODE
+ if (iqentry_insln[nn] != bus[`IB_LN]) begin
+ $display("Insn length mismatch.");
+ $stop;
+ end
+`endif
+ iqentry_cmp [nn] <= bus[`IB_CMP];
+ iqentry_tlb [nn] <= bus[`IB_TLB];
+ iqentry_sz [nn] <= bus[`IB_SZ];
+ iqentry_jal [nn] <= bus[`IB_JAL];
+ iqentry_ret [nn] <= bus[`IB_RET];
+ iqentry_irq [nn] <= bus[`IB_IRQ];
+ iqentry_brk [nn] <= bus[`IB_BRK];
+ iqentry_rti [nn] <= bus[`IB_RTI];
+ iqentry_bt [nn] <= bus[`IB_BT];
+ iqentry_alu [nn] <= bus[`IB_ALU];
+ iqentry_alu0 [nn] <= bus[`IB_ALU0];
+ iqentry_fpu [nn] <= bus[`IB_FPU];
+ iqentry_fc [nn] <= bus[`IB_FC];
+ iqentry_canex[nn] <= bus[`IB_CANEX];
+ iqentry_loadv[nn] <= bus[`IB_LOADV];
+ iqentry_load [nn] <= bus[`IB_LOAD];
+ iqentry_preload[nn]<= bus[`IB_PRELOAD];
+ iqentry_store[nn] <= bus[`IB_STORE];
+ iqentry_push [nn] <= bus[`IB_PUSH];
+ iqentry_oddball[nn] <= bus[`IB_ODDBALL];
+ iqentry_memsz[nn] <= bus[`IB_MEMSZ];
+ iqentry_mem [nn] <= bus[`IB_MEM];
+ iqentry_memndx[nn] <= bus[`IB_MEMNDX];
+ iqentry_rmw [nn] <= bus[`IB_RMW];
+ iqentry_memdb[nn] <= bus[`IB_MEMDB];
+ iqentry_memsb[nn] <= bus[`IB_MEMSB];
+ iqentry_shft [nn] <= bus[`IB_SHFT]; // 48 bit shift instructions
+ iqentry_sei [nn] <= bus[`IB_SEI];
+ iqentry_aq [nn] <= bus[`IB_AQ];
+ iqentry_rl [nn] <= bus[`IB_RL];
+ iqentry_jmp [nn] <= bus[`IB_JMP];
+ iqentry_br [nn] <= bus[`IB_BR];
+ iqentry_sync [nn] <= bus[`IB_SYNC];
+ iqentry_fsync[nn] <= bus[`IB_FSYNC];
+ iqentry_rfw [nn] <= bus[`IB_RFW];
+`ifdef SUPPORT_PREDICATION
+ iqentry_prfw [nn] <= bus[`IB_PRFW];
+`endif
+ iqentry_we [nn] <= bus[`IB_WE];
+end
+endtask
+
+task setinsn;
+input [`QBITS] nn;
+input [4:0] id;
+input v;
+input [143:0] bus;
+begin
+ if (iqentry_iv[nn] == `INV && iqentry_is[nn] == id && iqentry_v[nn] == `VAL && v == `VAL)
+ setinsn1(nn,bus);
+end
+endtask
+
+task a1_vs;
+begin
+ // if there is not an overlapping write to the register file.
+ if (Ra1s != Rt0s || !fetchbuf0_rfw) begin
+ iqentry_a1_v [tail1] <= regIsValid[Ra1s];
+ iqentry_a1_s [tail1] <= rf_source [Ra1s];
+ end
+ else begin
+ iqentry_a1_v [tail1] <= `INV;
+ iqentry_a1_s [tail1] <= { 1'b0, fetchbuf0_mem, tail0 };
+ end
+end
+endtask
+
+task a2_vs;
+begin
+ // if there is not an overlapping write to the register file.
+ if (Rb1s != Rt0s || !fetchbuf0_rfw) begin
+ iqentry_a2_v [tail1] <= regIsValid[Rb1s];
+ iqentry_a2_s [tail1] <= rf_source [Rb1s];
+ end
+ else begin
+ iqentry_a2_v [tail1] <= `INV;
+ iqentry_a2_s [tail1] <= { 1'b0, fetchbuf0_mem, tail0 };
+ end
+end
+endtask
+
+task a3_vs;
+begin
+ // if there is not an overlapping write to the register file.
+ if (Rc1s != Rt0s || !fetchbuf0_rfw) begin
+ iqentry_a3_v [tail1] <= regIsValid[Rc1s];
+ iqentry_a3_s [tail1] <= rf_source [Rc1s];
+ end
+ else begin
+ iqentry_a3_v [tail1] <= `INV;
+ iqentry_a3_s [tail1] <= { 1'b0, fetchbuf0_mem, tail0 };
+ end
+end
+endtask
+
+task enque0x;
+begin
+ if (IsVector(fetchbuf0_instr) && SUP_VECTOR) begin
+ vqe0 <= vqe0 + 4'd1;
+ if (IsVCmprss(fetchbuf0_instr)) begin
+ if (vm[fetchbuf0_instr[25:23]][vqe0])
+ vqet0 <= vqet0 + 4'd1;
+ end
+ else
+ vqet0 <= vqet0 + 4'd1;
+ if (vqe0 >= vl-2)
+ nop_fetchbuf <= fetchbuf ? 4'b1000 : 4'b0010;
+ enque0(tail0, fetchbuf0_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, vqe0);
+ iq_ctr = iq_ctr + 4'd1;
+ if (fetchbuf0_rfw) begin
+ rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail0 }; // top bit indicates ALU/MEM bus
+ rf_v[Rt0s] <= `INV;
+ end
+ if (canq2) begin
+ if (vqe0 < vl-2) begin
+ vqe0 <= vqe0 + 4'd2;
+ if (IsVCmprss(fetchbuf0_instr)) begin
+ if (vm[fetchbuf0_instr[25:23]][vqe0+6'd1])
+ vqet0 <= vqet0 + 4'd2;
+ end
+ else
+ vqet0 <= vqet0 + 4'd2;
+ enque0(tail1, fetchbuf0_thrd ? maxsn[1] + 4'd2 : maxsn[0]+4'd2, vqe0 + 6'd1);
+ iq_ctr = iq_ctr + 4'd2;
+ if (fetchbuf0_rfw) begin
+ rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail1 }; // top bit indicates ALU/MEM bus
+ rf_v[Rt0s] <= `INV;
+ end
+ end
+ end
+ end
+ else begin
+ enque0(tail0, fetchbuf0_thrd ? maxsn[1]+4'd1 : maxsn[0]+4'd1, 6'd0);
+ iq_ctr = iq_ctr + 4'd1;
+ if (fetchbuf0_rfw) begin
+ rf_source[ Rt0s ] <= { 1'b0, fetchbuf0_mem, tail0 }; // top bit indicates ALU/MEM bus
+ rf_v[Rt0s] <= `INV;
+ end
+ end
+end
+endtask
+
+// Enqueue fetchbuf0 onto the tail of the instruction queue
+task enque0;
+input [`QBITS] tail;
+input [`SNBITS] seqnum;
+input [5:0] venno;
+begin
+ iqentry_exc[tail] <= `FLT_NONE;
+`ifdef SUPPORT_DBG
+ if (dbg_imatchA)
+ iqentry_exc[tail] <= `FLT_DBG;
+ else if (dbg_ctrl[63])
+ iqentry_exc[tail] <= `FLT_SSM;
+`endif
+ iqentry_state[tail] <= IQS_QUEUED;
+ iqentry_sn [tail] <= seqnum;
+ iqentry_iv [tail] <= `INV;
+ iqentry_is [tail] <= tail;
+ iqentry_thrd [tail] <= fetchbuf0_thrd;
+ iqentry_res [tail] <= `ZERO;
+ iqentry_instr[tail] <= IsVLS(fetchbuf0_instr) ? (vm[fnM2(fetchbuf0_instr)] ? fetchbuf0_instr : `NOP_INSN) : fetchbuf0_instr;
+ iqentry_insln[tail] <= fetchbuf0_insln;
+ iqentry_fc [tail] <= `INV;
+ iqentry_mem [tail] <= `INV;
+ iqentry_alu [tail] <= `INV;
+ iqentry_fpu [tail] <= `INV;
+ iqentry_load [tail] <= `INV;
+ iqentry_pt [tail] <= predict_taken0;
+// If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
+// inherit the previous pc.
+//if (IsBrk(fetchbuf0_instr) && !fetchbuf0_instr[15] &&
+// (IsBrk(iqentry_instr[idm1(tail)]) && !iqentry_instr[idm1(tail1)][15] && iqentry_v[idm1(tail)]))
+// iqentry_pc [tail] <= iqentry_pc[idm1(tail)];
+//else
+ iqentry_pc [tail] <= fetchbuf0_pc;
+ iqentry_rtop [tail] <= IsRtop(fetchbuf0_instr);
+ iqentry_tgt [tail] <= Rt0;
+ iqentry_Ra [tail] <= Ra0;
+ iqentry_Rb [tail] <= Rb0;
+ iqentry_Rc [tail] <= Rc0;
+ iqentry_vl [tail] <= vl;
+ iqentry_ven [tail] <= venno;
+ iqentry_exc [tail] <= `EXC_NONE;
+ iqentry_a1 [tail] <= rfoa0;
+ iqentry_a1_v [tail] <= Source1Valid(fetchbuf0_instr) | regIsValid[Ra0s];
+ iqentry_a1_s [tail] <= rf_source[Ra0s];
+ iqentry_a2 [tail] <= rfob0;
+ iqentry_a2_v [tail] <= Source2Valid(fetchbuf0_instr) | regIsValid[Rb0s];
+ iqentry_a2_s [tail] <= rf_source[Rb0s];
+ iqentry_a3 [tail] <= rfoc0;
+ iqentry_a3_v [tail] <= Source3Valid(fetchbuf0_instr) | regIsValid[Rc0s];
+ iqentry_a3_s [tail] <= rf_source[Rc0s];
+`ifdef INLINE_DECODE
+/* This decoding cannot be done here because it'll introduce a 1 cycle delay
+ id1_Rt <= Rt0[4:0];
+ id1_vl <= vl;
+ id1_ven <= venno;
+ id1_id <= tail;
+ id1_pt <= predict_taken0;
+ id1_thrd <= fetchbuf0_thrd;
+*/
+ setinsn1(tail,id1_bus);
+`endif
+end
+endtask
+
+// Enque fetchbuf1. Fetchbuf1 might be the second instruction to queue so some
+// of this code checks to see which tail it is being queued on.
+task enque1;
+input [`QBITS] tail;
+input [`SNBITS] seqnum;
+input [5:0] venno;
+begin
+ iqentry_exc[tail] <= `FLT_NONE;
+`ifdef SUPPORT_DBG
+ if (dbg_imatchB)
+ iqentry_exc[tail] <= `FLT_DBG;
+ else if (dbg_ctrl[63])
+ iqentry_exc[tail] <= `FLT_SSM;
+`endif
+ iqentry_state[tail] <= IQS_QUEUED;
+ iqentry_sn [tail] <= seqnum;
+ iqentry_iv [tail] <= `INV;
+ iqentry_is [tail] <= tail;
+ iqentry_thrd [tail] <= fetchbuf1_thrd;
+ iqentry_res [tail] <= `ZERO;
+ iqentry_instr[tail] <= IsVLS(fetchbuf1_instr) ? (vm[fnM2(fetchbuf1_instr)] ? fetchbuf1_instr : `NOP_INSN) : fetchbuf1_instr;
+ iqentry_insln[tail] <= fetchbuf1_insln;
+ iqentry_fc [tail] <= `INV;
+ iqentry_mem [tail] <= `INV;
+ iqentry_alu [tail] <= `INV;
+ iqentry_fpu [tail] <= `INV;
+ iqentry_load [tail] <= `INV;
+ iqentry_pt [tail] <= predict_taken1;
+// If queing 2nd instruction must read from first
+if (tail==tail1) begin
+ // If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
+ // inherit the previous pc.
+// if (IsBrk(fetchbuf1_instr) && !fetchbuf1_instr[15] &&
+// IsBrk(fetchbuf0_instr) && !fetchbuf0_instr[15])
+// iqentry_pc [tail] <= fetchbuf0_pc;
+// else
+ iqentry_pc [tail] <= fetchbuf1_pc;
+end
+else begin
+ // If the previous instruction was a hardware interrupt and this instruction is a hardware interrupt
+ // inherit the previous pc.
+// if (IsBrk(fetchbuf1_instr) && !fetchbuf1_instr[15] &&
+// (IsBrk(iqentry_instr[idp7(tail)]) && !iqentry_instr[idm1(tail)][15] && iqentry_v[idm1(tail)]))
+// iqentry_pc [tail] <= iqentry_pc[idm1(tail)];
+// else
+ iqentry_pc [tail] <= fetchbuf1_pc;
+end
+ iqentry_rtop [tail] <= IsRtop(fetchbuf1_instr);
+ iqentry_tgt [tail] <= Rt1;
+ iqentry_Ra [tail] <= Ra1;
+ iqentry_Rb [tail] <= Rb1;
+ iqentry_Rc [tail] <= Rc1;
+ iqentry_vl [tail] <= vl;
+ iqentry_ven [tail] <= venno;
+ iqentry_exc [tail] <= `EXC_NONE;
+ iqentry_a1 [tail] <= rfoa1;
+ iqentry_a1_v [tail] <= Source1Valid(fetchbuf1_instr) | regIsValid[Ra1s];
+ iqentry_a1_s [tail] <= rf_source[Ra1s];
+ iqentry_a2 [tail] <= rfob1;
+ iqentry_a2_v [tail] <= Source2Valid(fetchbuf1_instr) | regIsValid[Rb1s];
+ iqentry_a2_s [tail] <= rf_source[Rb1s];
+ iqentry_a3 [tail] <= rfoc1;
+ iqentry_a3_v [tail] <= Source3Valid(fetchbuf1_instr) | regIsValid[Rc1s];
+ iqentry_a3_s [tail] <= rf_source[Rc1s];
+`ifdef INLINE_DECODE
+/* This decoding cannot be done here because it'll introduce a 1 cycle delay
+ id2_Rt <= Rt1[4:0];
+ id2_vl <= vl;
+ id2_ven <= venno;
+ id2_id <= tail;
+ id2_pt <= predict_taken1;
+ id2_thrd <= fetchbuf1_thrd;
+*/
+ setinsn1(tail,id2_bus);
+`endif
+end
+endtask
+
+// This task takes care of commits for things other than the register file.
+task oddball_commit;
+input v;
+input [`QBITS] head;
+input [1:0] which;
+reg thread;
+begin
+ thread = iqentry_thrd[head];
+ if (v) begin
+ if (|iqentry_exc[head]) begin
+ excmiss <= TRUE;
+`ifdef SUPPORT_SMT
+ excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol[thread],5'h00};
+ excthrd <= iqentry_thrd[head];
+ badaddr[{thread,2'd0}] <= iqentry_ma[head];
+ bad_instr[{thread,2'd0}] <= iqentry_instr[head];
+ epc0[thread] <= iqentry_pc[head];
+ epc1[thread] <= epc0[thread];
+ epc2[thread] <= epc1[thread];
+ epc3[thread] <= epc2[thread];
+ epc4[thread] <= epc3[thread];
+ epc5[thread] <= epc4[thread];
+ epc6[thread] <= epc5[thread];
+ epc7[thread] <= epc6[thread];
+ epc8[thread] <= epc7[thread];
+ im_stack[thread] <= {im_stack[thread][27:0],im};
+ ol_stack[thread] <= {ol_stack[thread][13:0],ol[thread]};
+ dl_stack[thread] <= {dl_stack[thread][13:0],dl[thread]};
+ pl_stack[thread] <= {pl_stack[thread][55:0],cpl[thread]};
+ rs_stack[thread] <= {rs_stack[thread][59:0],`EXC_RGS};
+ brs_stack[thread] <= {brs_stack[thread][59:0],`EXC_RGS};
+ cause[{thread,2'd0}] <= {8'd0,iqentry_exc[head]};
+ mstatus[thread][5:4] <= 2'd0;
+ mstatus[thread][13:6] <= 8'h00;
+ mstatus[thread][19:14] <= `EXC_RGS;
+`else
+ excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol,5'h00};
+ excthrd <= 1'b0;
+ badaddr[{1'b0,2'd0}] <= iqentry_ma[head];
+ bad_instr[3'd0] <= iqentry_instr[head];
+ epc0 <= iqentry_pc[head];
+ epc1 <= epc0;
+ epc2 <= epc1;
+ epc3 <= epc2;
+ epc4 <= epc3;
+ epc5 <= epc4;
+ epc6 <= epc5;
+ epc7 <= epc6;
+ epc8 <= epc7;
+ im_stack <= {im_stack[27:0],im};
+ ol_stack <= {ol_stack[13:0],ol};
+ dl_stack <= {dl_stack[13:0],dl};
+ pl_stack <= {pl_stack[55:0],cpl};
+ rs_stack <= {rs_stack[59:0],`EXC_RGS};
+ brs_stack <= {rs_stack[59:0],`EXC_RGS};
+ cause[3'd0] <= {8'd0,iqentry_exc[head]};
+ mstatus[5:4] <= 2'd0;
+ mstatus[13:6] <= 8'h00;
+ mstatus[19:14] <= `EXC_RGS;
+`endif
+ wb_en <= `TRUE;
+ sema[0] <= 1'b0;
+ ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
+`ifdef SUPPORT_DBG
+ dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
+ dbg_ctrl[63] <= FALSE;
+`endif
+ end
+ else
+ case(iqentry_instr[head][`INSTRUCTION_OP])
+`ifdef SUPPORT_PREDICATION
+ `CMPI: pregs[{rgs,iqentry_tgt[head][3:0]}] <= which==2'd1 ? cmt1nyb[iqentry_tgt[head][3:0]] : cmt0nyb[iqentry_tgt[head][3:0]];//commit_bus[3:0];
+`endif
+
+ `BRK:
+ // BRK is treated as a nop unless it's a software interrupt or a
+ // hardware interrupt at a higher priority than the current priority.
+ if ((|iqentry_instr[head][25:21]) || iqentry_instr[head][20:17] > im) begin
+ excmiss <= TRUE;
+`ifdef SUPPORT_SMT
+ excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol[thread],5'h00};
+ excthrd <= iqentry_thrd[head];
+ epc0[thread] <= iqentry_pc[head] + {iqentry_instr[head][25:21],1'b0};
+ epc1[thread] <= epc0[thread];
+ epc2[thread] <= epc1[thread];
+ epc3[thread] <= epc2[thread];
+ epc4[thread] <= epc3[thread];
+ epc5[thread] <= epc4[thread];
+ epc6[thread] <= epc5[thread];
+ epc7[thread] <= epc6[thread];
+ epc8[thread] <= epc7[thread];
+ im_stack[thread] <= {im_stack[thread][27:0],im};
+ ol_stack[thread] <= {ol_stack[thread][13:0],ol[thread]};
+ dl_stack[thread] <= {dl_stack[thread][13:0],dl[thread]};
+ pl_stack[thread] <= {pl_stack[thread][55:0],cpl[thread]};
+ rs_stack[thread] <= {rs_stack[thread][59:0],`BRK_RGS};
+ brs_stack[thread] <= {brs_stack[thread][59:0],`BRK_RGS};
+ cause[{thread,2'd0}] <= iqentry_res[head][7:0];
+ mstatus[thread][5:4] <= 2'd0;
+ mstatus[thread][13:6] <= 8'h00;
+ // For hardware interrupts only, set a new mask level. Setting a
+ // new mask level will effectively prevent subsequent brks that
+ // are streaming from an interrupt from being processed.
+ // Select register set according to interrupt level
+ if (iqentry_instr[head][25:21]==5'd0) begin
+ mstatus[thread][ 3: 0] <= iqentry_instr[head][20:17];
+ mstatus[thread][31:28] <= iqentry_instr[head][20:17];
+ mstatus[thread][19:14] <= {2'b0,iqentry_instr[head][20:17]};
+ rs_stack[thread][5:0] <= {2'b0,iqentry_instr[head][20:17]};
+ brs_stack[thread][5:0] <= {2'b0,iqentry_instr[head][20:17]};
+ end
+ else begin
+ mstatus[thread][19:14] <= `BRK_RGS;
+ rs_stack[thread][5:0] <= `BRK_RGS;
+ brs_stack[thread][5:0] <= `BRK_RGS;
+ end
+`else
+ excmisspc <= {tvec[3'd0][AMSB:8],1'b0,ol,5'h00};
+ excthrd <= 1'b0;
+ epc0 <= iqentry_pc[head] + {iqentry_instr[head][25:21],1'b0};
+ epc1 <= epc0;
+ epc2 <= epc1;
+ epc3 <= epc2;
+ epc4 <= epc3;
+ epc5 <= epc4;
+ epc6 <= epc5;
+ epc7 <= epc6;
+ epc8 <= epc7;
+ im_stack <= {im_stack[27:0],im};
+ ol_stack <= {ol_stack[13:0],ol};
+ dl_stack <= {dl_stack[13:0],dl};
+ pl_stack <= {pl_stack[55:0],cpl};
+ rs_stack <= {rs_stack[59:0],`BRK_RGS};
+ brs_stack <= {brs_stack[59:0],`BRK_RGS};
+ cause[3'd0] <= iqentry_res[head][7:0];
+ mstatus[5:4] <= 2'd0;
+ mstatus[13:6] <= 8'h00;
+ // For hardware interrupts only, set a new mask level. Setting a
+ // new mask level will effectively prevent subsequent brks that
+ // are streaming from an interrupt from being processed.
+ // Select register set according to interrupt level
+ if (iqentry_instr[head][25:21]==5'd0) begin
+ mstatus[ 3: 0] <= iqentry_instr[head][20:17];
+ mstatus[31:28] <= iqentry_instr[head][20:17];
+ mstatus[19:14] <= {2'b0,iqentry_instr[head][20:17]};
+ rs_stack[5:0] <= {2'b0,iqentry_instr[head][20:17]};
+ brs_stack[5:0] <= {2'b0,iqentry_instr[head][20:17]};
+ end
+ else begin
+ mstatus[19:14] <= `BRK_RGS;
+ rs_stack[5:0] <= `BRK_RGS;
+ brs_stack[5:0] <= `BRK_RGS;
+ end
+`endif
+ sema[0] <= 1'b0;
+ ve_hold <= {vqet1,10'd0,vqe1,10'd0,vqet0,10'd0,vqe0};
+`ifdef SUPPORT_DBG
+ dbg_ctrl[62:55] <= {dbg_ctrl[61:55],dbg_ctrl[63]};
+ dbg_ctrl[63] <= FALSE;
+`endif
+ end
+ `IVECTOR:
+ casez(iqentry_tgt[head])
+ 8'b00100???: vm[iqentry_tgt[head][2:0]] <= iqentry_res[head];
+ 8'b00101111: vl <= iqentry_res[head];
+ default: ;
+ endcase
+ `R2:
+ case(iqentry_instr[head][`INSTRUCTION_S2])
+`ifdef SUPPORT_PREDICATION
+ `CMP: pregs[{rgs,iqentry_tgt[head][3:0]}] <= which==2'd1 ? cmt1nyb[iqentry_tgt[head][3:0]] : cmt0nyb[iqentry_tgt[head][3:0]];//commit_bus[3:0];
+`endif
+ `R1: case(iqentry_instr[head][20:16])
+ `CHAIN_OFF: cr0[18] <= 1'b0;
+ `CHAIN_ON: cr0[18] <= 1'b1;
+ //`SETWB: wbrcd[pcr[5:0]] <= 1'b1;
+ default: ;
+ endcase
+ `VMOV: casez(iqentry_tgt[head])
+ 12'b1111111_00???: vm[iqentry_tgt[head][2:0]] <= iqentry_res[head];
+ 12'b1111111_01111: vl <= iqentry_res[head];
+ default: ;
+ endcase
+`ifdef SUPPORT_SMT
+ `SEI: mstatus[thread][3:0] <= iqentry_res[head][3:0]; // S1
+`else
+ `SEI: mstatus[3:0] <= iqentry_res[head][3:0]; // S1
+`endif
+ `RTI: begin
+ excmiss <= TRUE;
+`ifdef SUPPORT_SMT
+ excmisspc <= epc0[thread];
+ excthrd <= thread;
+ mstatus[thread][3:0] <= im_stack[thread][3:0];
+ mstatus[thread][5:4] <= ol_stack[thread][1:0];
+ mstatus[thread][21:20] <= dl_stack[thread][1:0];
+ mstatus[thread][13:6] <= pl_stack[thread][7:0];
+ mstatus[thread][19:14] <= rs_stack[thread][5:0];
+ im_stack[thread] <= {4'd15,im_stack[thread][31:4]};
+ ol_stack[thread] <= {2'd0,ol_stack[thread][15:2]};
+ dl_stack[thread] <= {2'd0,dl_stack[thread][15:2]};
+ pl_stack[thread] <= {8'h00,pl_stack[thread][63:8]};
+ rs_stack[thread] <= {6'h00,rs_stack[thread][59:6]};
+ brs_stack[thread] <= {6'h00,brs_stack[thread][59:6]};
+ epc0[thread] <= epc1[thread];
+ epc1[thread] <= epc2[thread];
+ epc2[thread] <= epc3[thread];
+ epc3[thread] <= epc4[thread];
+ epc4[thread] <= epc5[thread];
+ epc5[thread] <= epc6[thread];
+ epc6[thread] <= epc7[thread];
+ epc7[thread] <= epc8[thread];
+ epc8[thread] <= {tvec[0][AMSB:8], 1'b0, ol[thread], 5'h0};
+`else
+ excmisspc <= epc0;
+ excthrd <= thread;
+ mstatus[3:0] <= im_stack[3:0];
+ mstatus[5:4] <= ol_stack[1:0];
+ mstatus[21:20] <= dl_stack[1:0];
+ mstatus[13:6] <= pl_stack[7:0];
+ mstatus[19:14] <= rs_stack[5:0];
+ im_stack <= {4'd15,im_stack[31:4]};
+ ol_stack <= {2'd0,ol_stack[15:2]};
+ dl_stack <= {2'd0,dl_stack[15:2]};
+ pl_stack <= {8'h00,pl_stack[63:8]};
+ rs_stack <= {6'h00,rs_stack[59:6]};
+ brs_stack <= {6'h00,brs_stack[59:6]};
+ epc0 <= epc1;
+ epc1 <= epc2;
+ epc2 <= epc3;
+ epc3 <= epc4;
+ epc4 <= epc5;
+ epc5 <= epc6;
+ epc6 <= epc7;
+ epc7 <= epc8;
+ epc8 <= {tvec[0][AMSB:8], 1'b0, ol, 5'h0};
+`endif
+ sema[0] <= 1'b0;
+ sema[iqentry_res[head][5:0]] <= 1'b0;
+ vqe0 <= ve_hold[ 5: 0];
+ vqet0 <= ve_hold[21:16];
+ vqe1 <= ve_hold[37:32];
+ vqet1 <= ve_hold[53:48];
+`ifdef SUPPORT_DBG
+ dbg_ctrl[62:55] <= {FALSE,dbg_ctrl[62:56]};
+ dbg_ctrl[63] <= dbg_ctrl[55];
+`endif
+ end
+ default: ;
+ endcase
+ `MEMNDX:
+ case(iqentry_instr[head][`INSTRUCTION_S2])
+ `CACHEX:
+ case(iqentry_instr[head][22:18])
+ 5'h03: invic <= TRUE;
+ 5'h10: cr0[30] <= FALSE;
+ 5'h11: cr0[30] <= TRUE;
+ default: ;
+ endcase
+ default: ;
+ endcase
+ `CSRRW:
+ begin
+ write_csr(iqentry_instr[head][31:18],iqentry_a1[head],thread);
+ end
+ `REX:
+`ifdef SUPPORT_SMT
+ // Can only redirect to a lower level
+ if (ol[thread] < iqentry_instr[head][14:13]) begin
+ mstatus[thread][5:4] <= iqentry_instr[head][14:13];
+ badaddr[{thread,iqentry_instr[head][14:13]}] <= badaddr[{thread,ol[thread]}];
+ bad_instr[{thread,iqentry_instr[head][14:13]}] <= bad_instr[{thread,ol[thread]}];
+ cause[{thread,iqentry_instr[head][14:13]}] <= cause[{thread,ol[thread]}];
+ mstatus[thread][13:6] <= iqentry_instr[head][25:18] | iqentry_a1[head][7:0];
+ end
+`else
+ if (ol < iqentry_instr[head][14:13]) begin
+ mstatus[5:4] <= iqentry_instr[head][14:13];
+ badaddr[{1'b0,iqentry_instr[head][14:13]}] <= badaddr[{1'b0,ol}];
+ bad_instr[{1'b0,iqentry_instr[head][14:13]}] <= bad_instr[{1'b0,ol}];
+ cause[{1'b0,iqentry_instr[head][14:13]}] <= cause[{1'b0,ol}];
+ mstatus[13:6] <= iqentry_instr[head][25:18] | iqentry_a1[head][7:0];
+ end
+`endif
+ `CACHE:
+ case(iqentry_instr[head][17:13])
+ 5'h03: invic <= TRUE;
+ 5'h10: cr0[30] <= FALSE;
+ 5'h11: cr0[30] <= TRUE;
+ default: ;
+ endcase
+ `FLOAT:
+ case(iqentry_instr[head][`INSTRUCTION_S2])
+ `FRM: begin
+ fp_rm <= iqentry_res[head][2:0];
+ end
+ `FCX:
+ begin
+ fp_sx <= fp_sx & ~iqentry_res[head][5];
+ fp_inex <= fp_inex & ~iqentry_res[head][4];
+ fp_dbzx <= fp_dbzx & ~(iqentry_res[head][3]|iqentry_res[head][0]);
+ fp_underx <= fp_underx & ~iqentry_res[head][2];
+ fp_overx <= fp_overx & ~iqentry_res[head][1];
+ fp_giopx <= fp_giopx & ~iqentry_res[head][0];
+ fp_infdivx <= fp_infdivx & ~iqentry_res[head][0];
+ fp_zerozerox <= fp_zerozerox & ~iqentry_res[head][0];
+ fp_subinfx <= fp_subinfx & ~iqentry_res[head][0];
+ fp_infzerox <= fp_infzerox & ~iqentry_res[head][0];
+ fp_NaNCmpx <= fp_NaNCmpx & ~iqentry_res[head][0];
+ fp_swtx <= 1'b0;
+ end
+ `FDX:
+ begin
+ fp_inexe <= fp_inexe & ~iqentry_res[head][4];
+ fp_dbzxe <= fp_dbzxe & ~iqentry_res[head][3];
+ fp_underxe <= fp_underxe & ~iqentry_res[head][2];
+ fp_overxe <= fp_overxe & ~iqentry_res[head][1];
+ fp_invopxe <= fp_invopxe & ~iqentry_res[head][0];
+ end
+ `FEX:
+ begin
+ fp_inexe <= fp_inexe | iqentry_res[head][4];
+ fp_dbzxe <= fp_dbzxe | iqentry_res[head][3];
+ fp_underxe <= fp_underxe | iqentry_res[head][2];
+ fp_overxe <= fp_overxe | iqentry_res[head][1];
+ fp_invopxe <= fp_invopxe | iqentry_res[head][0];
+ end
+ default:
+ begin
+ // 31 to 29 is rounding mode
+ // 28 to 24 are exception enables
+ // 23 is nsfp
+ // 22 is a fractie
+ fp_fractie <= iqentry_ares[head][22];
+ fp_raz <= iqentry_ares[head][21];
+ // 20 is a 0
+ fp_neg <= iqentry_ares[head][19];
+ fp_pos <= iqentry_ares[head][18];
+ fp_zero <= iqentry_ares[head][17];
+ fp_inf <= iqentry_ares[head][16];
+ // 15 swtx
+ // 14
+ fp_inex <= fp_inex | (fp_inexe & iqentry_ares[head][14]);
+ fp_dbzx <= fp_dbzx | (fp_dbzxe & iqentry_ares[head][13]);
+ fp_underx <= fp_underx | (fp_underxe & iqentry_ares[head][12]);
+ fp_overx <= fp_overx | (fp_overxe & iqentry_ares[head][11]);
+ //fp_giopx <= fp_giopx | (fp_giopxe & iqentry_res2[head][10]);
+ //fp_invopx <= fp_invopx | (fp_invopxe & iqentry_res2[head][24]);
+ //
+ fp_cvtx <= fp_cvtx | (fp_giopxe & iqentry_ares[head][7]);
+ fp_sqrtx <= fp_sqrtx | (fp_giopxe & iqentry_ares[head][6]);
+ fp_NaNCmpx <= fp_NaNCmpx | (fp_giopxe & iqentry_ares[head][5]);
+ fp_infzerox <= fp_infzerox | (fp_giopxe & iqentry_ares[head][4]);
+ fp_zerozerox <= fp_zerozerox | (fp_giopxe & iqentry_ares[head][3]);
+ fp_infdivx <= fp_infdivx | (fp_giopxe & iqentry_ares[head][2]);
+ fp_subinfx <= fp_subinfx | (fp_giopxe & iqentry_ares[head][1]);
+ fp_snanx <= fp_snanx | (fp_giopxe & iqentry_ares[head][0]);
+
+ end
+ endcase
+ default: ;
+ endcase
+ // Once the flow control instruction commits, NOP it out to allow
+ // pending stores to be issued.
+ iqentry_instr[head][5:0] <= `NOP;
+ end
+end
+endtask
+
+// CSR access tasks
+// This task does not work. Possibly because the always block @* doesn't
+// evaluate into the task to see which signals are changing. The following
+// code is simply included as an always block above.
+task read_csr;
+input [11:0] csrno;
+output [63:0] dat;
+input thread;
+begin
+`ifdef SUPPORT_SMT
+ if (csrno[11:10] >= ol[thread])
+`else
+ if (csrno[11:10] >= ol)
+`endif
+ casez(csrno[9:0])
+ `CSR_CR0: dat <= cr0;
+ `CSR_HARTID: dat <= hartid;
+ `CSR_TICK: dat <= tick;
+ `CSR_PCR: dat <= pcr;
+ `CSR_PCR2: dat <= pcr2;
+ `CSR_PMR: dat <= pmr;
+ `CSR_WBRCD: dat <= wbrcd;
+ `CSR_SEMA: dat <= sema;
+ `CSR_KEYS: dat <= keys;
+ `CSR_TCB: dat <= tcb;
+ `CSR_FSTAT: dat <= {fp_rgs,fp_status};
+`ifdef SUPPORT_DBG
+ `CSR_DBAD0: dat <= dbg_adr0;
+ `CSR_DBAD1: dat <= dbg_adr1;
+ `CSR_DBAD2: dat <= dbg_adr2;
+ `CSR_DBAD3: dat <= dbg_adr3;
+ `CSR_DBCTRL: dat <= dbg_ctrl;
+ `CSR_DBSTAT: dat <= dbg_stat;
+`endif
+ `CSR_CAS: dat <= cas;
+ `CSR_TVEC: dat <= tvec[csrno[2:0]];
+ `CSR_BADADR: dat <= badaddr[{thread,csrno[11:10]}];
+ `CSR_BADINSTR: dat <= bad_instr[{thread,csrno[11:10]}];
+ `CSR_CAUSE: dat <= {48'd0,cause[{thread,csrno[11:10]}]};
+`ifdef SUPPORT_SMT
+ `CSR_IM_STACK: dat <= im_stack[thread];
+ `CSR_OL_STACK: dat <= {dl_stack[thread],ol_stack[thread]};
+ `CSR_PL_STACK: dat <= pl_stack[thread];
+ `CSR_RS_STACK: dat <= rs_stack[thread];
+ `CSR_STATUS: dat <= mstatus[thread][63:0];
+ `CSR_EPC0: dat <= epc0[thread];
+ `CSR_EPC1: dat <= epc1[thread];
+ `CSR_EPC2: dat <= epc2[thread];
+ `CSR_EPC3: dat <= epc3[thread];
+ `CSR_EPC4: dat <= epc4[thread];
+ `CSR_EPC5: dat <= epc5[thread];
+ `CSR_EPC6: dat <= epc6[thread];
+ `CSR_EPC7: dat <= epc7[thread];
+`else
+ `CSR_IM_STACK: dat <= im_stack;
+ `CSR_OL_STACK: dat <= {dl_stack,ol_stack};
+ `CSR_PL_STACK: dat <= pl_stack;
+ `CSR_RS_STACK: dat <= rs_stack;
+ `CSR_STATUS: dat <= mstatus[63:0];
+ `CSR_EPC0: dat <= epc0;
+ `CSR_EPC1: dat <= epc1;
+ `CSR_EPC2: dat <= epc2;
+ `CSR_EPC3: dat <= epc3;
+ `CSR_EPC4: dat <= epc4;
+ `CSR_EPC5: dat <= epc5;
+ `CSR_EPC6: dat <= epc6;
+ `CSR_EPC7: dat <= epc7;
+`endif
+ `CSR_CODEBUF: dat <= codebuf[csrno[5:0]];
+`ifdef SUPPORT_BBMS
+ `CSR_TB: dat <= tb;
+ `CSR_CBL: dat <= cbl;
+ `CSR_CBU: dat <= cbu;
+ `CSR_RO: dat <= ro;
+ `CSR_DBL: dat <= dbl;
+ `CSR_DBU: dat <= dbu;
+ `CSR_SBL: dat <= sbl;
+ `CSR_SBU: dat <= sbu;
+ `CSR_ENU: dat <= en;
+`endif
+`ifdef SUPPORT_PREDICATION
+ `CSR_PREGS: read_pregs(dat);
+`endif
+ `CSR_Q_CTR: dat <= iq_ctr;
+ `CSR_BM_CTR: dat <= bm_ctr;
+ `CSR_ICL_CTR: dat <= icl_ctr;
+ `CSR_IRQ_CTR: dat <= irq_ctr;
+ `CSR_TIME: dat <= wc_times;
+ `CSR_INFO:
+ case(csrno[3:0])
+ 4'd0: dat <= "Finitron"; // manufacturer
+ 4'd1: dat <= " ";
+ 4'd2: dat <= "64 bit "; // CPU class
+ 4'd3: dat <= " ";
+ 4'd4: dat <= "FT64 "; // Name
+ 4'd5: dat <= " ";
+ 4'd6: dat <= 64'd1; // model #
+ 4'd7: dat <= 64'd1; // serial number
+ 4'd8: dat <= {32'd16384,32'd16384}; // cache sizes instruction,data
+ 4'd9: dat <= 64'd0;
+ default: dat <= 64'd0;
+ endcase
+ default: begin
+ $display("Unsupported CSR:%h",csrno[10:0]);
+ dat <= 64'hEEEEEEEEEEEEEEEE;
+ end
+ endcase
+ else
+ dat <= 64'h0;
+end
+endtask
+
+task write_csr;
+input [13:0] csrno;
+input [63:0] dat;
+input thread;
+begin
+`ifdef SUPPORT_SMT
+ if (csrno[11:10] >= ol[thread])
+`else
+ if (csrno[11:10] >= ol)
+`endif
+ case(csrno[13:12])
+ 2'd1: // CSRRW
+ casez(csrno[9:0])
+ `CSR_CR0: cr0 <= dat;
+ `CSR_PCR: pcr <= dat[31:0];
+ `CSR_PCR2: pcr2 <= dat;
+ `CSR_PMR: case(`NUM_IDU)
+ 0,1: pmr[0] <= 1'b1;
+ 2:
+ begin
+ if (dat[1:0]==2'b00)
+ pmr[1:0] <= 2'b01;
+ else
+ pmr[1:0] <= dat[1:0];
+ pmr[63:2] <= dat[63:2];
+ end
+ 3:
+ begin
+ if (dat[2:0]==3'b000)
+ pmr[2:0] <= 3'b001;
+ else
+ pmr[2:0] <= dat[2:0];
+ pmr[63:3] <= dat[63:3];
+ end
+ default: pmr[0] <= 1'b1;
+ endcase
+ `CSR_WBRCD: wbrcd <= dat;
+ `CSR_SEMA: sema <= dat;
+ `CSR_KEYS: keys <= dat;
+ `CSR_TCB: tcb <= dat;
+ `CSR_FSTAT: fpu_csr[37:32] <= dat[37:32];
+ `CSR_BADADR: badaddr[{thread,csrno[11:10]}] <= dat;
+ `CSR_BADINSTR: bad_instr[{thread,csrno[11:10]}] <= dat;
+ `CSR_CAUSE: cause[{thread,csrno[11:10]}] <= dat[15:0];
+`ifdef SUPPORT_DBG
+ `CSR_DBAD0: dbg_adr0 <= dat[AMSB:0];
+ `CSR_DBAD1: dbg_adr1 <= dat[AMSB:0];
+ `CSR_DBAD2: dbg_adr2 <= dat[AMSB:0];
+ `CSR_DBAD3: dbg_adr3 <= dat[AMSB:0];
+ `CSR_DBCTRL: dbg_ctrl <= dat;
+`endif
+ `CSR_CAS: cas <= dat;
+ `CSR_TVEC: tvec[csrno[2:0]] <= dat[31:0];
+`ifdef SUPPORT_SMT
+ `CSR_IM_STACK: im_stack[thread] <= dat[31:0];
+ `CSR_OL_STACK: begin
+ ol_stack[thread] <= dat[15:0];
+ dl_stack[thread] <= dat[31:16];
+ end
+ `CSR_PL_STACK: pl_stack[thread] <= dat;
+ `CSR_RS_STACK: rs_stack[thread] <= dat;
+ `CSR_STATUS: mstatus[thread][63:0] <= dat;
+ `CSR_EPC0: epc0[thread] <= dat;
+ `CSR_EPC1: epc1[thread] <= dat;
+ `CSR_EPC2: epc2[thread] <= dat;
+ `CSR_EPC3: epc3[thread] <= dat;
+ `CSR_EPC4: epc4[thread] <= dat;
+ `CSR_EPC5: epc5[thread] <= dat;
+ `CSR_EPC6: epc6[thread] <= dat;
+ `CSR_EPC7: epc7[thread] <= dat;
+`else
+ `CSR_IM_STACK: im_stack <= dat[31:0];
+ `CSR_OL_STACK: begin
+ ol_stack <= dat[15:0];
+ dl_stack <= dat[31:16];
+ end
+ `CSR_PL_STACK: pl_stack <= dat;
+ `CSR_RS_STACK: rs_stack <= dat;
+ `CSR_STATUS: mstatus[63:0] <= dat;
+ `CSR_EPC0: epc0 <= dat;
+ `CSR_EPC1: epc1 <= dat;
+ `CSR_EPC2: epc2 <= dat;
+ `CSR_EPC3: epc3 <= dat;
+ `CSR_EPC4: epc4 <= dat;
+ `CSR_EPC5: epc5 <= dat;
+ `CSR_EPC6: epc6 <= dat;
+ `CSR_EPC7: epc7 <= dat;
+`endif
+`ifdef SUPPORT_BBMS
+ `CSR_TB: prg_base[brgs] <= dat;
+ `CSR_CBL: cl_barrier[brgs] <= dat;
+ `CSR_CBU: cu_barrier[brgs] <= dat;
+ `CSR_RO: ro_barrier[brgs] <= dat;
+ `CSR_DBL: dl_barrier[brgs] <= dat;
+ `CSR_DBU: du_barrier[brgs] <= dat;
+ `CSR_SBL: sl_barrier[brgs] <= dat;
+ `CSR_SBU: su_barrier[brgs] <= dat;
+ `CSR_ENU: en_barrier[brgs] <= dat;
+`endif
+`ifdef SUPPORT_PREDICATION
+ `CSR_PREGS: write_pregs(dat);
+`endif
+ `CSR_TIME: begin
+ ld_time <= 6'h3f;
+ wc_time_dat <= dat;
+ end
+ `CSR_CODEBUF: codebuf[csrno[5:0]] <= dat;
+ default: ;
+ endcase
+ 2'd2: // CSRRS
+ case(csrno[9:0])
+ `CSR_CR0: cr0 <= cr0 | dat;
+ `CSR_PCR: pcr[31:0] <= pcr[31:0] | dat[31:0];
+ `CSR_PCR2: pcr2 <= pcr2 | dat;
+ `CSR_PMR: pmr <= pmr | dat;
+ `CSR_WBRCD: wbrcd <= wbrcd | dat;
+`ifdef SUPPORT_DBG
+ `CSR_DBCTRL: dbg_ctrl <= dbg_ctrl | dat;
+`endif
+ `CSR_SEMA: sema <= sema | dat;
+`ifdef SUPPORT_SMT
+ `CSR_STATUS: mstatus[thread][63:0] <= mstatus[thread][63:0] | dat;
+`else
+ `CSR_STATUS: mstatus[63:0] <= mstatus[63:0] | dat;
+`endif
+ default: ;
+ endcase
+ 2'd3: // CSRRC
+ case(csrno[9:0])
+ `CSR_CR0: cr0 <= cr0 & ~dat;
+ `CSR_PCR: pcr <= pcr & ~dat;
+ `CSR_PCR2: pcr2 <= pcr2 & ~dat;
+ `CSR_PMR: begin
+ if (dat[1:0]==2'b11)
+ pmr[1:0] <= 2'b01;
+ else
+ pmr[1:0] <= pmr[1:0] & ~dat[1:0];
+ pmr[63:2] <= pmr[63:2] & ~dat[63:2];
+ end
+ `CSR_WBRCD: wbrcd <= wbrcd & ~dat;
+`ifdef SUPPORT_DBG
+ `CSR_DBCTRL: dbg_ctrl <= dbg_ctrl & ~dat;
+`endif
+ `CSR_SEMA: sema <= sema & ~dat;
+`ifdef SUPPORT_SMT
+ `CSR_STATUS: mstatus[thread][63:0] <= mstatus[thread][63:0] & ~dat;
+`else
+ `CSR_STATUS: mstatus[63:0] <= mstatus[63:0] & ~dat;
+`endif
+ default: ;
+ endcase
+ default: ;
+ endcase
+end
+endtask
+
+task tDram0Issue;
+input [`QBITSP1] n;
+begin
+// dramA_v <= `INV;
+ dram0 <= `DRAMSLOT_BUSY;
+ dram0_id <= { 1'b1, n[`QBITS] };
+ dram0_instr <= iqentry_instr[n];
+ dram0_rmw <= iqentry_rmw[n];
+ dram0_preload <= iqentry_preload[n];
+ dram0_tgt <= iqentry_tgt[n];
+ dram0_data <= iqentry_a2[n];
+ dram0_addr <= iqentry_ma[n];
+ // if (ol[iqentry_thrd[n]]==`OL_USER)
+ // dram0_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
+ // else
+ dram0_unc <= iqentry_ma[n][31:20]==12'hFFD || !dce || iqentry_loadv[n];
+ dram0_memsize <= iqentry_memsz[n];
+ dram0_load <= iqentry_load[n];
+ dram0_store <= iqentry_store[n];
+`ifdef SUPPORT_SMT
+ dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
+`else
+ dram0_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol : dl;
+`endif
+ // Once the memory op is issued reset the a1_v flag.
+ // This will cause the a1 bus to look for new data from memory (a1_s is pointed to a memory bus)
+ // This is used for the load and compare instructions.
+ // must reset the a1 source too.
+ //iqentry_a1_v[n] <= `INV;
+ iqentry_state[n] <= IQS_MEM;
+end
+endtask
+
+task tDram1Issue;
+input [`QBITSP1] n;
+begin
+ dramB_v <= `INV;
+ dram1 <= `DRAMSLOT_BUSY;
+ dram1_id <= { 1'b1, n[`QBITS] };
+ dram1_instr <= iqentry_instr[n];
+ dram1_rmw <= iqentry_rmw[n];
+ dram1_preload <= iqentry_preload[n];
+ dram1_tgt <= iqentry_tgt[n];
+ dram1_data <= iqentry_a2[n];
+ dram1_addr <= iqentry_ma[n];
+ // if (ol[iqentry_thrd[n]]==`OL_USER)
+ // dram1_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
+ // else
+ dram1_unc <= iqentry_ma[n][31:20]==12'hFFD || !dce || iqentry_loadv[n];
+ dram1_memsize <= iqentry_memsz[n];
+ dram1_load <= iqentry_load[n];
+ dram1_store <= iqentry_store[n];
+`ifdef SUPPORT_SMT
+ dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
+`else
+ dram1_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol : dl;
+`endif
+ //iqentry_a1_v[n] <= `INV;
+ iqentry_state[n] <= IQS_MEM;
+end
+endtask
+
+task tDram2Issue;
+input [`QBITSP1] n;
+begin
+ dramC_v <= `INV;
+ dram2 <= `DRAMSLOT_BUSY;
+ dram2_id <= { 1'b1, n[`QBITS] };
+ dram2_instr <= iqentry_instr[n];
+ dram2_rmw <= iqentry_rmw[n];
+ dram2_preload <= iqentry_preload[n];
+ dram2_tgt <= iqentry_tgt[n];
+ dram2_data <= iqentry_a2[n];
+ dram2_addr <= iqentry_ma[n];
+ // if (ol[iqentry_thrd[n]]==`OL_USER)
+ // dram2_seg <= (iqentry_Ra[n]==5'd30 || iqentry_Ra[n]==5'd31) ? {ss[iqentry_thrd[n]],13'd0} : {ds[iqentry_thrd[n]],13'd0};
+ // else
+ dram2_unc <= iqentry_ma[n][31:20]==12'hFFD || !dce || iqentry_loadv[n];
+ dram2_memsize <= iqentry_memsz[n];
+ dram2_load <= iqentry_load[n];
+ dram2_store <= iqentry_store[n];
+`ifdef SUPPORT_SMT
+ dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol[iqentry_thrd[n]] : dl[iqentry_thrd[n]];
+`else
+ dram2_ol <= (iqentry_Ra[n][4:0]==5'd31 || iqentry_Ra[n][4:0]==5'd30) ? ol : dl;
+`endif
+ //iqentry_a1_v[n] <= `INV;
+ iqentry_state[n] <= IQS_MEM;
+end
+endtask
+
+task wb_nack;
+begin
+ cti_o <= 3'b000;
+ bte_o <= 2'b00;
+ cyc <= `LOW;
+ stb_o <= `LOW;
+ we <= `LOW;
+ sel_o <= 8'h00;
+end
+endtask
+
+endmodule
+
+
+module decoder5 (num, out);
+input [4:0] num;
+output [31:1] out;
+reg [31:1] out;
+
+always @(num)
+case (num)
+ 5'd0 : out <= 31'b0000000000000000000000000000000;
+ 5'd1 : out <= 31'b0000000000000000000000000000001;
+ 5'd2 : out <= 31'b0000000000000000000000000000010;
+ 5'd3 : out <= 31'b0000000000000000000000000000100;
+ 5'd4 : out <= 31'b0000000000000000000000000001000;
+ 5'd5 : out <= 31'b0000000000000000000000000010000;
+ 5'd6 : out <= 31'b0000000000000000000000000100000;
+ 5'd7 : out <= 31'b0000000000000000000000001000000;
+ 5'd8 : out <= 31'b0000000000000000000000010000000;
+ 5'd9 : out <= 31'b0000000000000000000000100000000;
+ 5'd10: out <= 31'b0000000000000000000001000000000;
+ 5'd11: out <= 31'b0000000000000000000010000000000;
+ 5'd12: out <= 31'b0000000000000000000100000000000;
+ 5'd13: out <= 31'b0000000000000000001000000000000;
+ 5'd14: out <= 31'b0000000000000000010000000000000;
+ 5'd15: out <= 31'b0000000000000000100000000000000;
+ 5'd16: out <= 31'b0000000000000001000000000000000;
+ 5'd17: out <= 31'b0000000000000010000000000000000;
+ 5'd18: out <= 31'b0000000000000100000000000000000;
+ 5'd19: out <= 31'b0000000000001000000000000000000;
+ 5'd20: out <= 31'b0000000000010000000000000000000;
+ 5'd21: out <= 31'b0000000000100000000000000000000;
+ 5'd22: out <= 31'b0000000001000000000000000000000;
+ 5'd23: out <= 31'b0000000010000000000000000000000;
+ 5'd24: out <= 31'b0000000100000000000000000000000;
+ 5'd25: out <= 31'b0000001000000000000000000000000;
+ 5'd26: out <= 31'b0000010000000000000000000000000;
+ 5'd27: out <= 31'b0000100000000000000000000000000;
+ 5'd28: out <= 31'b0001000000000000000000000000000;
+ 5'd29: out <= 31'b0010000000000000000000000000000;
+ 5'd30: out <= 31'b0100000000000000000000000000000;
+ 5'd31: out <= 31'b1000000000000000000000000000000;
+endcase
+
+endmodule
+
+module decoder6 (num, out);
+input [5:0] num;
+output [63:1] out;
+
+wire [63:0] out1;
+
+assign out1 = 64'd1 << num;
+assign out = out1[63:1];
+
+endmodule
+
+module decoder7 (num, out);
+input [6:0] num;
+output [127:1] out;
+
+wire [127:0] out1;
+
+assign out1 = 128'd1 << num;
+assign out = out1[127:1];
+
+endmodule
+
+module decoder8 (num, out);
+input [7:0] num;
+output [255:1] out;
+
+wire [255:0] out1;
+
+assign out1 = 256'd1 << num;
+assign out = out1[255:1];
+
+endmodule
+
Index: thor/trunk/FT64v7/rtl/twoway/FT64_BTB.v
===================================================================
--- thor/trunk/FT64v7/rtl/twoway/FT64_BTB.v (nonexistent)
+++ thor/trunk/FT64v7/rtl/twoway/FT64_BTB.v (revision 60)
@@ -0,0 +1,199 @@
+// ============================================================================
+// __
+// \\__/ o\ (C) 2017-2018 Robert Finch, Waterloo
+// \ __ / All rights reserved.
+// \/_// robfinch@finitron.ca
+// ||
+//
+// FT64_BTB.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_BranchPredictor.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_TLB.v
+//
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_fetchbuf.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// FT64_fetchbuf_x1.v
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see @finitron.ca
+// ||
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU Lesser General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see
thor/trunk/FT64v7/software/AS64/bin/AS64.exe
Property changes :
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Index: thor/trunk/FT64v7/software/CC64/bin/CC64.exe
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: thor/trunk/FT64v7/software/CC64/bin/CC64.exe
===================================================================
--- thor/trunk/FT64v7/software/CC64/bin/CC64.exe (nonexistent)
+++ thor/trunk/FT64v7/software/CC64/bin/CC64.exe (revision 60)
thor/trunk/FT64v7/software/CC64/bin/CC64.exe
Property changes :
Added: svn:mime-type
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+application/octet-stream
\ No newline at end of property