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URL https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk

Subversion Repositories 10_100m_ethernet-fifo_convertor

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Rev 6 → Rev 7

/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/RxModule.v
4,13 → 4,20
 
////Next task: make the feedback to PC showing need data.
 
//vertion 0.4, add the function for TxModule to get start in a configurable ff_clk time after
// RxModule receiving the first frame. To modify the delay time just to
// change the value of the macro-variable delay_cnt_config.
//version 0.3, changed the changes made by version 0.2 back
//version 0.2, set empty when ff_data_buf_index's less significant bits is 3'b111 or 3'b000
 
`include "common.v"
 
`define eth_buf_len 1416 //1416=8*(8+6+6+2+3+148+4)
`define nibble_cnt_step 9'h001
 
`define delay_cnt_config 4'h0
`define delay_cnt_step 4'h1
 
module RxModule(phy_rxd, phy_rxen, phy_rxclk, phy_rxer,
ff_clk, ff_data, ff_en,
47,6 → 54,7
reg start=1'b0;
reg start_intra=1'b0;
reg[3:0] delay_cnt;
reg[3:0] ff_data_buf_index = 4'h0;
reg ff_state;
95,16 → 103,20
ff_cnt <= 8'h00;
ff_data_buf_index <= 4'hf;
ff_en <= 1'b0;
delay_cnt <= `delay_cnt_config;
end
else
case(ff_state)
transfer: begin
delay_cnt <= delay_cnt - `delay_cnt_step;
if(delay_cnt == 0) start <=1'b1;
if(ff_cnt==8'h00) begin //load new 148 bits
{ff_d[146:0],ff_data} <= ff_data_buf[ff_data_buf_index+4'h1];
ff_data_buf_index <= ff_data_buf_index + 4'h1;
ff_cnt <= ff_cnt + 8'h01;
ff_en <= 1'b1;
start <= 1'b1;
end
else if(ff_cnt == 8'd148) begin //every 148 bit need a gap
ff_en <= 1'b0;
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/TxModule.v
59,6 → 59,7
reg[`ff_cnt_wide-1:0] ff_cnt=0;
reg[8:0] tx_cnt;
reg data_av;
reg Enable_Crc, Initialize_Crc; //declare the variables for the CRC module
wire [3:0] Data_Crc;
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/test_feedback.v
0,0 → 1,41
//version 0.4, the test_feedback is created, main task is to test the top module, EthernetModule.v
// the ff_data_source is feed back to ff_data_sink
 
module test_feedback(reset, clk_in,
phy_rxd, phy_rxen, phy_rxclk, phy_rxer,
phy_txd, phy_txen, phy_txclk, phy_txer,
phy_reset, phy_col, phy_linksts, phy_crs,
test1, test2, test3, test4
);
input reset, clk_in;
output phy_reset, test1, test2, test3, test4;
input[3:0] phy_rxd; //MII interface for the phy chip
input phy_rxclk, phy_rxer;
output[3:0] phy_txd;
output phy_txer, phy_txen;
//declare them as inout port because when powerup reset, they act as output pins to config DM9161
//after reset, phy_txclk and phy_rxen must be input ports
inout phy_txclk, phy_col, phy_rxen, phy_linksts, phy_crs;
wire ff_en, ff_data;
wire clk_10K, ff_clk;
EthernetModule EthernetModule_inst(.reset(reset), .clk_10K(clk_10K),
.ff_clk(ff_clk), .ff_en_source(ff_en), .ff_en_sink(1'b1),
.ff_data_source(ff_data), .ff_data_sink(ff_data), //ff_clk should be a 270.33KHz clock
.phy_rxd(phy_rxd), .phy_rxen(phy_rxen), .phy_rxclk(phy_rxclk), .phy_rxer(phy_rxer),
.phy_txd(phy_txd), .phy_txen(phy_txen), .phy_txclk(phy_txclk), .phy_txer(phy_txer),
.phy_reset(phy_reset), .phy_col(phy_col), .phy_linksts(phy_linksts), .phy_crs(phy_crs),
.test1(test1), .test2(test2), .test3(test3), .test4(test4)
);
pll pll_inst (
.inclk0 ( clk_in ),
.c0 ( clk_10K ),
.c1 ( ff_clk )
);
 
endmodule
/10_100m_ethernet-fifo_convertor/trunk/rtl/verilog/common.v
6,8 → 6,8
//This file used to define some macro-varibles which can be used by all other files
 
//NOTE!!! Olny one of the following two definitions can be open
//`define frameIDfromRx //frameID comes from Rxmodule
`define frameIDcount //frameID counts for itself by adding one every frame
`define frameIDfromRx //frameID comes from Rxmodule
//`define frameIDcount //frameID counts for itself by adding one every frame
 
`define Preamble 64'hd555_5555_5555_5555
 

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