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/trunk/bench/verilog/wb_mast_model.v
0,0 → 1,582
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Master Model ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_mast_model.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
 
`include "wb_model_defines.v"
 
module wb_mast(clk, rst, adr, din, dout, cyc, stb, sel, we, ack, err, rty);
 
input clk, rst;
output [31:0] adr;
input [31:0] din;
output [31:0] dout;
output cyc, stb;
output [3:0] sel;
output we;
input ack, err, rty;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
parameter mem_size = 4096;
 
reg [31:0] adr;
reg [31:0] dout;
reg cyc, stb;
reg [3:0] sel;
reg we;
 
reg [31:0] rd_mem[mem_size:0];
reg [31:0] wr_mem[mem_size:0];
integer rd_cnt;
integer wr_cnt;
 
////////////////////////////////////////////////////////////////////
//
// Memory Logic
//
 
initial
begin
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
cyc = 0;
stb = 0;
sel = 4'hx;
we = 1'hx;
rd_cnt = 0;
wr_cnt = 0;
#1;
$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)\n");
end
 
 
 
task mem_fill;
 
integer n;
begin
rd_cnt = 0;
wr_cnt = 0;
for(n=0;n<mem_size;n=n+1)
begin
rd_mem[n] = $random;
wr_mem[n] = $random;
end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 1 Word Task
//
 
task wb_wr1;
input [31:0] a;
input [3:0] s;
input [31:0] d;
 
begin
 
@(posedge clk);
#1;
adr = a;
dout = d;
cyc = 1;
stb = 1;
we=1;
sel = s;
 
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
cyc=0;
stb=0;
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
//adr = 0;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Write 4 Words Task
//
 
task wb_wr4;
input [31:0] a;
input [3:0] s;
input delay;
input [31:0] d1;
input [31:0] d2;
input [31:0] d3;
input [31:0] d4;
 
integer delay;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
sel = s;
 
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a;
dout = d1;
stb = 1;
we=1;
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
 
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
//adr = a+4;
dout = d2;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
//adr = a+8;
dout = d3;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
dout = 32'hxxxx_xxxx;
 
repeat(delay)
begin
@(posedge clk);
#1;
end
stb=1;
//adr = a+12;
dout = d4;
we=1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#1;
stb=0;
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 0;
//adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
task wb_wr_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
 
integer delay;
integer count;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
 
for(n=0;n<count;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = wr_mem[n + wr_cnt];
stb = 1;
we=1;
sel = s;
if(n!=0) @(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + count;
end
endtask
 
 
task wb_rmw;
input [31:0] a;
input [3:0] s;
input delay;
input rcount;
input wcount;
 
integer delay;
integer rcount;
integer wcount;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
for(n=0;n<rcount-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
//$display("Rd Mem[%0d]: %h", (n + rd_cnt), rd_mem[n + rd_cnt] );
#1;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + rcount;
 
//@(posedge clk);
 
 
for(n=0;n<wcount;n=n+1)
begin
repeat(delay)
begin
@(posedge clk);
#1;
end
adr = a + (n*4);
dout = wr_mem[n + wr_cnt];
stb = 1;
we=1;
sel = s;
// if(n!=0)
@(posedge clk);
while(~ack & ~err) @(posedge clk);
#2;
stb=0;
we=1'bx;
sel = 4'hx;
dout = 32'hxxxx_xxxx;
adr = 32'hxxxx_xxxx;
end
 
cyc=0;
 
adr = 32'hxxxx_xxxx;
//adr = 32'hffff_ffff;
 
wr_cnt = wr_cnt + wcount;
end
endtask
 
 
 
////////////////////////////////////////////////////////////////////
//
// Read 1 Word Task
//
 
task wb_rd1;
input [31:0] a;
input [3:0] s;
output [31:0] d;
 
begin
 
@(posedge clk);
#1;
adr = a;
cyc = 1;
stb = 1;
we = 0;
sel = s;
 
//@(posedge clk);
while(~ack & ~err) @(posedge clk);
d = din;
#1;
cyc=0;
stb=0;
//adr = 32'hxxxx_xxxx;
//adr = 0;
adr = 32'hffff_ffff;
dout = 32'hxxxx_xxxx;
we = 1'hx;
sel = 4'hx;
 
end
endtask
 
 
////////////////////////////////////////////////////////////////////
//
// Read 4 Words Task
//
 
 
task wb_rd4;
input [31:0] a;
input [3:0] s;
input delay;
output [31:0] d1;
output [31:0] d2;
output [31:0] d3;
output [31:0] d4;
 
integer delay;
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
adr = a;
stb = 1;
while(~ack & ~err) @(posedge clk);
d1 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
 
//adr = a+4;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d2 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
 
 
//adr = a+8;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d3 = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
 
//adr = a+12;
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
d4 = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
end
endtask
 
 
 
task wb_rd_mult;
input [31:0] a;
input [3:0] s;
input delay;
input count;
 
integer delay;
integer count;
integer n;
 
begin
 
@(posedge clk);
#1;
cyc = 1;
we = 0;
sel = s;
repeat(delay) @(posedge clk);
 
for(n=0;n<count-1;n=n+1)
begin
adr = a + (n*4);
stb = 1;
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
#2;
stb=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hxxxx_xxxx;
repeat(delay)
begin
@(posedge clk);
#1;
end
we = 0;
sel = s;
end
 
adr = a+(n*4);
stb = 1;
@(posedge clk);
while(~ack & ~err) @(posedge clk);
rd_mem[n + rd_cnt] = din;
#1;
stb=0;
cyc=0;
we = 1'hx;
sel = 4'hx;
adr = 32'hffff_ffff;
adr = 32'hxxxx_xxxx;
 
rd_cnt = rd_cnt + count;
end
endtask
 
endmodule
/trunk/bench/verilog/test_bench_top.v
0,0 → 1,847
/////////////////////////////////////////////////////////////////////
//// ////
//// Top Level Test Bench ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: test_bench_top.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
 
`include "ac97_defines.v"
 
module test;
 
reg clk;
reg rst;
wire [31:0] wb_data_i;
wire [31:0] wb_data_o;
wire [31:0] wb_addr_i;
wire [3:0] wb_sel_i;
wire wb_we_i;
wire wb_cyc_i;
wire wb_stb_i;
wire wb_ack_o;
wire wb_err_o;
wire int;
wire [8:0] dma_req;
reg [8:0] dma_ack;
reg susp_req;
reg resume_req;
wire suspended;
reg bit_clk;
wire sync;
wire sdata_out;
wire sdata_in;
wire ac97_reset_;
 
// Test Bench Variables
reg verbose;
integer error_cnt;
 
// DMA model
reg wb_busy;
reg oc0_dma_en;
reg oc1_dma_en;
reg oc2_dma_en;
reg oc3_dma_en;
reg oc4_dma_en;
reg oc5_dma_en;
reg ic0_dma_en;
reg ic1_dma_en;
reg ic2_dma_en;
reg [31:0] oc0_mem[0:256];
reg [31:0] oc1_mem[0:256];
reg [31:0] oc2_mem[0:256];
reg [31:0] oc3_mem[0:256];
reg [31:0] oc4_mem[0:256];
reg [31:0] oc5_mem[0:256];
reg [31:0] ic0_mem[0:256];
reg [31:0] ic1_mem[0:256];
reg [31:0] ic2_mem[0:256];
reg [31:0] reg_mem[0:256];
integer oc0_ptr;
integer oc1_ptr;
integer oc2_ptr;
integer oc3_ptr;
integer oc4_ptr;
integer oc5_ptr;
integer ic0_ptr;
integer ic1_ptr;
integer ic2_ptr;
 
reg [31:0] ints_r;
reg int_chk_en;
integer int_cnt;
 
integer n;
 
// Misc Variables
reg [31:0] data;
reg [31:0] data1;
reg [31:0] data2;
reg [31:0] tmp;
integer size, frames, m;
 
/////////////////////////////////////////////////////////////////////
//
// Defines
//
 
`define CSR 8'h00
`define OCC0 8'h04
`define OCC1 8'h08
`define ICC 8'h0c
`define CRAC 8'h10
`define INTM 8'h14
`define INTS 8'h18
 
`define OC0 8'h20
`define OC1 8'h24
`define OC2 8'h28
`define OC3 8'h2c
`define OC4 8'h30
`define OC5 8'h34
`define IC0 8'h38
`define IC1 8'h3c
`define IC2 8'h40
 
/////////////////////////////////////////////////////////////////////
//
// Simulation Initialization and Start up Section
//
 
task do_rst;
 
begin
wb_busy = 0;
oc0_dma_en = 0;
oc1_dma_en = 0;
oc2_dma_en = 0;
oc3_dma_en = 0;
oc4_dma_en = 0;
oc5_dma_en = 0;
ic0_dma_en = 0;
ic1_dma_en = 0;
ic2_dma_en = 0;
 
oc0_ptr = 0;
oc1_ptr = 0;
oc2_ptr = 0;
oc3_ptr = 0;
oc4_ptr = 0;
oc5_ptr = 0;
ic0_ptr = 0;
ic1_ptr = 0;
ic2_ptr = 0;
 
rst = 0;
repeat(48) @(posedge clk);
rst = 1;
repeat(48) @(posedge clk);
 
end
 
endtask
 
initial
begin
$display("\n\n");
$display("*****************************************************");
$display("* WISHBONE Memory Controller Simulation started ... *");
$display("*****************************************************");
$display("\n");
`ifdef WAVES
$shm_open("waves");
$shm_probe("AS",test,"AS");
$display("INFO: Signal dump enabled ...\n\n");
`endif
//wd_cnt = 0;
int_chk_en = 1;
int_cnt = 0;
error_cnt = 0;
clk = 1;
bit_clk = 0;
rst = 0;
susp_req = 0;
resume_req = 0;
verbose = 1;
dma_ack = 0;
 
wb_busy = 0;
oc0_dma_en = 0;
oc1_dma_en = 0;
oc2_dma_en = 0;
oc3_dma_en = 0;
oc4_dma_en = 0;
oc5_dma_en = 0;
ic0_dma_en = 0;
ic1_dma_en = 0;
ic2_dma_en = 0;
 
oc0_ptr = 0;
oc1_ptr = 0;
oc2_ptr = 0;
oc3_ptr = 0;
oc4_ptr = 0;
oc5_ptr = 0;
ic0_ptr = 0;
ic1_ptr = 0;
ic2_ptr = 0;
 
repeat(48) @(posedge clk);
rst = 1;
repeat(48) @(posedge clk);
 
// HERE IS WHERE THE TEST CASES GO ...
 
if(0) // Full Regression Run
begin
$display(" ......................................................");
$display(" : :");
$display(" : Regression Run ... :");
$display(" :....................................................:");
 
basic1;
 
do_rst;
 
basic2;
 
do_rst;
 
vsr1;
 
end
else
if(1) // Debug Tests
begin
$display(" ......................................................");
$display(" : :");
$display(" : Test Debug Testing ... :");
$display(" :....................................................:");
 
basic1;
 
do_rst;
 
basic2;
 
do_rst;
 
vsr1;
 
repeat(100) @(posedge clk);
$finish;
end
else
begin
 
//
// TEST DEVELOPMENT AREA
//
 
$display("\n\n");
$display("*****************************************************");
$display("*** XXX AC97 I/O Test ... ***");
$display("*****************************************************\n");
 
 
wb_busy = 1;
m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
m0.wb_wr1(`OCC0,4'hf, 32'h7272_7272);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_7272);
 
wb_busy = 0;
oc0_dma_en = 1;
oc1_dma_en = 1;
oc2_dma_en = 1;
oc3_dma_en = 1;
oc4_dma_en = 1;
oc5_dma_en = 1;
ic0_dma_en = 1;
ic1_dma_en = 1;
ic2_dma_en = 1;
 
for(n=0;n<256;n=n+1)
begin
oc0_mem[n] = $random;
oc1_mem[n] = $random;
oc2_mem[n] = $random;
oc3_mem[n] = $random;
oc4_mem[n] = $random;
oc5_mem[n] = $random;
ic0_mem[n] = $random;
ic1_mem[n] = $random;
ic2_mem[n] = $random;
end
 
u1.init(0);
frames = 139;
 
fork
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1111_1111_11, // Output slots valid bits
10'b1111_1111_11, // Input slots valid bits
20'b00_00_00_00_00_00_00_00_00_00, // Output Slots intervals
20'b00_00_00_00_00_00_00_00_00_00 // Input Slots intervals
);
 
begin // Do a register Write
repeat(2) @(posedge sync);
 
for(n=0;n<75;n=n+1)
begin
@(negedge sync);
repeat(230) @(posedge bit_clk);
 
repeat(n) @(posedge bit_clk);
 
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr1(`CRAC,4'hf, {1'b1, 8'h0, n[6:0], 16'h1234 + n[7:0]} );
wb_busy = 0;
 
while(!int) @(posedge clk);
 
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd1(`CRAC,4'hf, reg_mem[n] );
m0.wb_wr1(`CSR, 4'hf, 32'h0000_0001);
 
repeat(10) @(posedge clk);
force bit_clk = 0;
repeat(80) @(posedge clk);
 
m0.wb_wr1(`CSR, 4'hf, 32'h0000_0002);
 
repeat(300) @(posedge clk);
 
release bit_clk;
 
wb_busy = 0;
 
end
end
join
 
repeat(300) @(posedge bit_clk);
 
for(n=0;n<75;n=n+1)
begin
 
tmp = u1.is2_mem[n];
data2 = {16'h0, tmp[19:4]};
tmp = reg_mem[n];
data1 = {16'h0, tmp[15:0]};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Register Read Data %0d Mismatch Expected: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
 
end
 
size = frames - 4;
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs3_mem[n];
data = oc0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs4_mem[n];
data = oc1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs6_mem[n];
data = oc2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs7_mem[n];
data = oc3_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs8_mem[n];
data = oc4_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs9_mem[n];
data = oc5_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is3_mem[n];
data = ic0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is4_mem[n];
data = ic1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is6_mem[n];
data = ic2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
 
repeat(6000) @(posedge clk);
$finish;
 
end
 
repeat(100) @(posedge clk);
$finish;
end
 
 
task wait_sync;
 
begin
 
while(!sync) @(posedge bit_clk);
repeat(2) @(posedge bit_clk);
end
endtask
 
/////////////////////////////////////////////////////////////////////
//
// Simple Interrupt Handler
//
 
always @(posedge clk)
if(int & int_chk_en)
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd1(`INTS,4'hf, ints_r);
//$display("INFO: Got Interrupt (%0d). INTS: %h (%t)", int_cnt, ints_r, $time);
wb_busy = 0;
int_cnt = int_cnt + 1;
end
 
/////////////////////////////////////////////////////////////////////
//
// Simple DMA Engine
//
 
always @(posedge clk)
if(oc0_dma_en & dma_req[0])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC0, 4'hf, 0, oc0_mem[oc0_ptr+0],
oc0_mem[oc0_ptr+1],
oc0_mem[oc0_ptr+2],
oc0_mem[oc0_ptr+3]);
oc0_ptr = oc0_ptr + 4;
wb_busy = 0;
dma_ack[0] = 1;
@(posedge clk);
#1 dma_ack[0] = 0;
end
 
 
always @(posedge clk)
if(oc1_dma_en & dma_req[1])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC1, 4'hf, 0, oc1_mem[oc1_ptr+0],
oc1_mem[oc1_ptr+1],
oc1_mem[oc1_ptr+2],
oc1_mem[oc1_ptr+3]);
oc1_ptr = oc1_ptr + 4;
wb_busy = 0;
dma_ack[1] = 1;
@(posedge clk);
#1 dma_ack[1] = 0;
end
 
always @(posedge clk)
if(oc2_dma_en & dma_req[2])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC2, 4'hf, 0, oc2_mem[oc2_ptr+0],
oc2_mem[oc2_ptr+1],
oc2_mem[oc2_ptr+2],
oc2_mem[oc2_ptr+3]);
oc2_ptr = oc2_ptr + 4;
wb_busy = 0;
dma_ack[2] = 1;
@(posedge clk);
#1 dma_ack[2] = 0;
end
 
always @(posedge clk)
if(oc3_dma_en & dma_req[3])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC3, 4'hf, 0, oc3_mem[oc3_ptr+0],
oc3_mem[oc3_ptr+1],
oc3_mem[oc3_ptr+2],
oc3_mem[oc3_ptr+3]);
oc3_ptr = oc3_ptr + 4;
wb_busy = 0;
dma_ack[3] = 1;
@(posedge clk);
#1 dma_ack[3] = 0;
end
 
always @(posedge clk)
if(oc4_dma_en & dma_req[4])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC4, 4'hf, 0, oc4_mem[oc4_ptr+0],
oc4_mem[oc4_ptr+1],
oc4_mem[oc4_ptr+2],
oc4_mem[oc4_ptr+3]);
oc4_ptr = oc4_ptr + 4;
wb_busy = 0;
dma_ack[4] = 1;
@(posedge clk);
#1 dma_ack[4] = 0;
end
 
always @(posedge clk)
if(oc5_dma_en & dma_req[5])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr4(`OC5, 4'hf, 0, oc5_mem[oc5_ptr+0],
oc5_mem[oc5_ptr+1],
oc5_mem[oc5_ptr+2],
oc5_mem[oc5_ptr+3]);
oc5_ptr = oc5_ptr + 4;
wb_busy = 0;
dma_ack[5] = 1;
@(posedge clk);
#1 dma_ack[5] = 0;
end
 
always @(posedge clk)
if(ic0_dma_en & dma_req[6])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd4(`IC0, 4'hf, 0, ic0_mem[ic0_ptr+0],
ic0_mem[ic0_ptr+1],
ic0_mem[ic0_ptr+2],
ic0_mem[ic0_ptr+3]);
ic0_ptr = ic0_ptr + 4;
wb_busy = 0;
dma_ack[6] = 1;
@(posedge clk);
#1 dma_ack[6] = 0;
end
 
always @(posedge clk)
if(ic1_dma_en & dma_req[7])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd4(`IC1, 4'hf, 0, ic1_mem[ic1_ptr+0],
ic1_mem[ic1_ptr+1],
ic1_mem[ic1_ptr+2],
ic1_mem[ic1_ptr+3]);
ic1_ptr = ic1_ptr + 4;
wb_busy = 0;
dma_ack[7] = 1;
@(posedge clk);
#1 dma_ack[7] = 0;
end
 
always @(posedge clk)
if(ic2_dma_en & dma_req[8])
begin
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd4(`IC2, 4'hf, 0, ic2_mem[ic2_ptr+0],
ic2_mem[ic2_ptr+1],
ic2_mem[ic2_ptr+2],
ic2_mem[ic2_ptr+3]);
ic2_ptr = ic2_ptr + 4;
wb_busy = 0;
dma_ack[8] = 1;
@(posedge clk);
#1 dma_ack[8] = 0;
end
 
 
 
 
/////////////////////////////////////////////////////////////////////
//
// Clock Generation
//
 
always #2.5 clk = ~clk;
 
always #40.69 bit_clk <= ~bit_clk;
 
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE AC 97 Controller IP Core
//
 
ac97_top u0(
.clk_i( clk ),
.rst_i( rst ),
.wb_data_i( wb_data_i ),
.wb_data_o( wb_data_o ),
.wb_addr_i( wb_addr_i ),
.wb_sel_i( wb_sel_i ),
.wb_we_i( wb_we_i ),
.wb_cyc_i( wb_cyc_i ),
.wb_stb_i( wb_stb_i ),
.wb_ack_o( wb_ack_o ),
.wb_err_o( wb_err_o ),
.int_o( int ),
.dma_req_o( dma_req ),
.dma_ack_i( dma_ack ),
.suspended_o( suspended ),
.bit_clk_pad_i( bit_clk ),
.sync_pad_o( sync ),
.sdata_pad_o( sdata_out ),
.sdata_pad_i( sdata_in ),
.ac97_reset_pad_o_( ac97_reset_ )
);
 
/////////////////////////////////////////////////////////////////////
//
// WISHBONE Master Model
//
 
wb_mast m0( .clk( clk ),
.rst( rst ),
.adr( wb_addr_i ),
.din( wb_data_o ),
.dout( wb_data_i ),
.cyc( wb_cyc_i ),
.stb( wb_stb_i ),
.sel( wb_sel_i ),
.we( wb_we_i ),
.ack( wb_ack_o ),
.err( wb_err_o ),
.rty( )
);
 
/////////////////////////////////////////////////////////////////////
//
// AC 97 Codec Model
//
 
 
ac97_codec_top u1(
.clk( bit_clk ),
.rst( rst ),
.sync( sync ),
.sdata_out( sdata_in ),
.sdata_in( sdata_out )
);
 
 
 
/////////////////////////////////////////////////////////////////////
//
// Tests and libraries
//
 
 
`include "tests.v"
 
endmodule
 
 
/trunk/bench/verilog/ac97_codec_top.v
0,0 → 1,651
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Codec Top Level ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: ac97_codec_top.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
 
`include "ac97_defines.v"
 
module ac97_codec_top(clk, rst,
sync,
sdata_out,
sdata_in
);
 
input clk, rst;
 
// --------------------------------------
// AC97 Codec Interface
input sync;
output sdata_out;
input sdata_in;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
wire [15:0] out_slt0;
wire [19:0] out_slt1;
wire [19:0] out_slt2;
wire [19:0] out_slt3;
wire [19:0] out_slt4;
wire [19:0] out_slt5;
wire [19:0] out_slt6;
wire [19:0] out_slt7;
wire [19:0] out_slt8;
wire [19:0] out_slt9;
wire [19:0] out_slt10;
wire [19:0] out_slt11;
wire [19:0] out_slt12;
 
wire [15:0] in_slt0;
wire [19:0] in_slt1;
reg [19:0] in_slt2;
reg [19:0] in_slt3;
reg [19:0] in_slt4;
reg [19:0] in_slt5;
reg [19:0] in_slt6;
reg [19:0] in_slt7;
reg [19:0] in_slt8;
reg [19:0] in_slt9;
reg [19:0] in_slt10;
reg [19:0] in_slt11;
reg [19:0] in_slt12;
 
reg [19:0] smem[0:32];
reg [19:0] rmem[0:32];
 
reg [15:0] s0;
reg [19:0] s1;
 
integer rs1_ptr, rs2_ptr;
integer rs3_ptr, rs4_ptr, rs5_ptr, rs6_ptr, rs7_ptr;
integer rs8_ptr, rs9_ptr, rs10_ptr, rs11_ptr, rs12_ptr;
integer is2_ptr, is3_ptr, is4_ptr, is5_ptr, is6_ptr, is7_ptr;
integer is8_ptr, is9_ptr, is10_ptr, is11_ptr, is12_ptr;
reg [19:0] rslt0;
reg [19:0] rslt1;
reg [19:0] rslt2;
reg [19:0] rs1_mem[0:256];
reg [19:0] rs2_mem[0:256];
reg [19:0] rs3_mem[0:256];
reg [19:0] rs4_mem[0:256];
reg [19:0] rs5_mem[0:256];
reg [19:0] rs6_mem[0:256];
reg [19:0] rs7_mem[0:256];
reg [19:0] rs8_mem[0:256];
reg [19:0] rs9_mem[0:256];
reg [19:0] rs10_mem[0:256];
reg [19:0] rs11_mem[0:256];
reg [19:0] rs12_mem[0:256];
 
reg [19:0] is2_mem[0:256];
reg [19:0] is3_mem[0:256];
reg [19:0] is4_mem[0:256];
reg [19:0] is5_mem[0:256];
reg [19:0] is6_mem[0:256];
reg [19:0] is7_mem[0:256];
reg [19:0] is8_mem[0:256];
reg [19:0] is9_mem[0:256];
reg [19:0] is10_mem[0:256];
reg [19:0] is11_mem[0:256];
reg [19:0] is12_mem[0:256];
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
task init;
input mode;
 
integer mode;
begin
 
fill_mem(mode);
clr_ptrs;
 
end
endtask
 
task fill_mem;
input mode;
 
integer mode;
integer n;
 
begin
 
if(mode==0)
for(n=0;n<256;n=n+1)
begin
is2_mem[n] = { 4'h0, n[11:0], 4'h0 };
is3_mem[n] = { 4'h1, n[11:0], 4'h0 };
is4_mem[n] = { 4'h2, n[11:0], 4'h0 };
is5_mem[n] = { 4'h3, n[11:0], 4'h0 };
is6_mem[n] = { 4'h4, n[11:0], 4'h0 };
is7_mem[n] = { 4'h5, n[11:0], 4'h0 };
is8_mem[n] = { 4'h6, n[11:0], 4'h0 };
is9_mem[n] = { 4'h7, n[11:0], 4'h0 };
is10_mem[n] = { 4'h8, n[11:0], 4'h0 };
is11_mem[n] = { 4'h9, n[11:0], 4'h0 };
is12_mem[n] = { 4'ha, n[11:0], 4'h0 };
end
else
for(n=0;n<256;n=n+1)
begin
is2_mem[n] = $random;
is3_mem[n] = $random;
is4_mem[n] = $random;
is5_mem[n] = $random;
is6_mem[n] = $random;
is7_mem[n] = $random;
is8_mem[n] = $random;
is9_mem[n] = $random;
is10_mem[n] = $random;
is11_mem[n] = $random;
is12_mem[n] = $random;
end
 
end
endtask
 
always @(posedge clk)
if(!rst) s0 = 0;
 
always @(posedge clk)
if(!rst) s1 = 0;
 
assign in_slt0 = s0;
assign in_slt1 = s1;
 
 
//always @(posedge sync)
always @(rslt0 or rslt1 or s0)
if(s0[13] | (rslt0[14] & rslt1[19]) )
begin
in_slt2 = #1 is2_mem[is2_ptr];
is2_ptr = is2_ptr + 1;
end
 
always @(posedge sync)
if(s0[12])
begin
in_slt3 = #1 is3_mem[is3_ptr];
is3_ptr = is3_ptr + 1;
end
 
always @(posedge sync)
if(s0[11])
begin
in_slt4 = #1 is4_mem[is4_ptr];
is4_ptr = is4_ptr + 1;
end
 
always @(posedge sync)
if(s0[10])
begin
in_slt5 = #1 is5_mem[is5_ptr];
is5_ptr = is5_ptr + 1;
end
 
always @(posedge sync)
if(s0[9])
begin
in_slt6 = #1 is6_mem[is6_ptr];
is6_ptr = is6_ptr + 1;
end
 
always @(posedge sync)
if(s0[8])
begin
in_slt7 = #1 is7_mem[is7_ptr];
is7_ptr = is7_ptr + 1;
end
 
always @(posedge sync)
if(s0[7])
begin
in_slt8 = #1 is8_mem[is8_ptr];
is8_ptr = is8_ptr + 1;
end
 
always @(posedge sync)
if(s0[6])
begin
in_slt9 = #1 is9_mem[is9_ptr];
is9_ptr = is9_ptr + 1;
end
 
always @(posedge sync)
if(s0[5])
begin
in_slt10 = #1 is10_mem[is10_ptr];
is10_ptr = is10_ptr + 1;
end
 
always @(posedge sync)
if(s0[4])
begin
in_slt11 = #1 is11_mem[is11_ptr];
is11_ptr = is11_ptr + 1;
end
 
always @(posedge sync)
if(s0[3])
begin
in_slt12 = #1 is12_mem[is12_ptr];
is12_ptr = is12_ptr + 1;
end
 
always @(posedge sync)
begin
rslt0 <= #2 out_slt0;
rslt1 <= #2 out_slt1;
rslt2 <= #2 out_slt2;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[14])
begin
rs1_mem[rs1_ptr] = #1 out_slt1;
rs1_ptr = rs1_ptr + 1;
//$display("INFO: Codec Register Addr: %h (%t)", out_slt1, $time);
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[13])
begin
rs2_mem[rs2_ptr] = #1 out_slt2;
rs2_ptr = rs2_ptr + 1;
//$display("INFO: Codec Register Data: %h (%t)", out_slt2, $time);
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[12])
begin
rs3_mem[rs3_ptr] = #1 out_slt3;
rs3_ptr = rs3_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[11])
begin
rs4_mem[rs4_ptr] = #1 out_slt4;
rs4_ptr = rs4_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[10])
begin
rs5_mem[rs5_ptr] = #1 out_slt5;
rs5_ptr = rs5_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[9])
begin
rs6_mem[rs6_ptr] = #1 out_slt6;
rs6_ptr = rs6_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[8])
begin
rs7_mem[rs7_ptr] = #1 out_slt7;
rs7_ptr = rs7_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[7])
begin
rs8_mem[rs8_ptr] = #1 out_slt8;
rs8_ptr = rs8_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[6])
begin
rs9_mem[rs9_ptr] = #1 out_slt9;
rs9_ptr = rs9_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[5])
begin
rs10_mem[rs10_ptr] = #1 out_slt10;
rs10_ptr = rs10_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[4])
begin
rs11_mem[rs11_ptr] = #1 out_slt11;
rs11_ptr = rs11_ptr + 1;
end
 
always @(posedge sync)
if(out_slt0[15] & out_slt0[3])
begin
rs12_mem[rs12_ptr] = #1 out_slt12;
rs12_ptr = rs12_ptr + 1;
end
 
 
task clr_ptrs;
 
begin
 
rs1_ptr = 0;
rs2_ptr = 0;
rs3_ptr = 0;
rs4_ptr = 0;
rs5_ptr = 0;
rs6_ptr = 0;
rs7_ptr = 0;
rs8_ptr = 0;
rs9_ptr = 0;
rs10_ptr = 0;
rs11_ptr = 0;
rs12_ptr = 0;
 
is2_ptr = 0;
is3_ptr = 0;
is4_ptr = 0;
is5_ptr = 0;
is6_ptr = 0;
is7_ptr = 0;
is8_ptr = 0;
is9_ptr = 0;
is10_ptr = 0;
is11_ptr = 0;
is12_ptr = 0;
 
end
endtask
 
 
task set_tag;
input cr;
input [11:0] tag;
 
// s0 - 16 bits
// 15 - Codec Ready
// 14:3 - Slot 1-12 Valid bits
// 2:0 - RESERVED (stuffed with 0)
begin
s0 = {cr, tag, 3'h0};
end
endtask
 
 
task set_req;
input [9:0] req;
 
reg [6:0] idx;
begin
 
idx = out_slt1[18:12];
s1 = {1'b0, idx, ~req, 2'h0};
 
end
endtask
 
 
task tx1;
input fcnt_max; // Total number fo frames
input rdy_del; // How many frames before codec is ready
input ovalid; // Out Channels valid (Surround Sound)
input ivalid; // In Channels Valid (Mic & Line In)
input oint; // Output Intervals
input iint; // input Intervals
 
integer fcnt_max, f;
integer rdy_del;
reg [9:0] ovalid, ivalid;
reg [19:0] oint, iint;
 
reg och0_v;
reg [1:0] och0_cnt;
reg och1_v;
reg [1:0] och1_cnt;
reg och2_v;
reg [1:0] och2_cnt;
reg och3_v;
reg [1:0] och3_cnt;
reg och4_v;
reg [1:0] och4_cnt;
reg och5_v;
reg [1:0] och5_cnt;
reg och6_v;
reg [1:0] och6_cnt;
reg och7_v;
reg [1:0] och7_cnt;
reg och8_v;
reg [1:0] och8_cnt;
reg och9_v;
reg [1:0] och9_cnt;
reg ich0_v;
reg [1:0] ich0_cnt;
reg ich1_v;
reg [1:0] ich1_cnt;
reg ich2_v;
reg [1:0] ich2_cnt;
reg ich3_v;
reg [1:0] ich3_cnt;
reg ich4_v;
reg [1:0] ich4_cnt;
reg ich5_v;
reg [1:0] ich5_cnt;
reg ich6_v;
reg [1:0] ich6_cnt;
reg ich7_v;
reg [1:0] ich7_cnt;
reg ich8_v;
reg [1:0] ich8_cnt;
reg ich9_v;
reg [1:0] ich9_cnt;
 
begin
 
och0_cnt = 0;
och1_cnt = 0;
och2_cnt = 0;
och3_cnt = 0;
och4_cnt = 0;
och5_cnt = 0;
och6_cnt = 0;
och7_cnt = 0;
och8_cnt = 0;
och9_cnt = 0;
 
ich0_cnt = 0;
ich1_cnt = 0;
ich2_cnt = 0;
ich3_cnt = 0;
ich4_cnt = 0;
ich5_cnt = 0;
ich6_cnt = 0;
ich7_cnt = 0;
ich8_cnt = 0;
ich9_cnt = 0;
 
for(f=0;f<fcnt_max;f=f+1)
begin
while(!sync) @(posedge clk);
if(f>rdy_del)
begin
 
och0_v = ovalid[9] & (och0_cnt == oint[19:18]);
if(och0_v) och0_cnt = 0;
else och0_cnt = och0_cnt + 1;
och1_v = ovalid[8] & (och1_cnt == oint[17:16]);
if(och1_v) och1_cnt = 0;
else och1_cnt = och1_cnt + 1;
och2_v = ovalid[7] & (och2_cnt == oint[15:14]);
if(och2_v) och2_cnt = 0;
else och2_cnt = och2_cnt + 1;
och3_v = ovalid[6] & (och3_cnt == oint[13:12]);
if(och3_v) och3_cnt = 0;
else och3_cnt = och3_cnt + 1;
och4_v = ovalid[5] & (och4_cnt == oint[11:10]);
if(och4_v) och4_cnt = 0;
else och4_cnt = och4_cnt + 1;
och5_v = ovalid[4] & (och5_cnt == oint[9:8]);
if(och5_v) och5_cnt = 0;
else och5_cnt = och5_cnt + 1;
och6_v = ovalid[3] & (och6_cnt == oint[7:6]);
if(och6_v) och6_cnt = 0;
else och6_cnt = och6_cnt + 1;
och7_v = ovalid[2] & (och7_cnt == oint[5:4]);
if(och7_v) och7_cnt = 0;
else och7_cnt = och7_cnt + 1;
och8_v = ovalid[1] & (och8_cnt == oint[3:2]);
if(och8_v) och8_cnt = 0;
else och8_cnt = och8_cnt + 1;
och9_v = ovalid[0] & (och9_cnt == oint[1:0]);
if(och9_v) och9_cnt = 0;
else och9_cnt = och9_cnt + 1;
 
ich0_v = ivalid[9] & (ich0_cnt == iint[19:18]);
if(ich0_v) ich0_cnt = 0;
else ich0_cnt = ich0_cnt + 1;
ich1_v = ivalid[8] & (ich1_cnt == iint[17:16]);
if(ich1_v) ich1_cnt = 0;
else ich1_cnt = ich1_cnt + 1;
ich2_v = ivalid[7] & (ich2_cnt == iint[15:14]);
if(ich2_v) ich2_cnt = 0;
else ich2_cnt = ich2_cnt + 1;
ich3_v = ivalid[6] & (ich3_cnt == iint[13:12]);
if(ich3_v) ich3_cnt = 0;
else ich3_cnt = ich3_cnt + 1;
ich4_v = ivalid[5] & (ich4_cnt == iint[11:10]);
if(ich4_v) ich4_cnt = 0;
else ich4_cnt = ich4_cnt + 1;
ich5_v = ivalid[4] & (ich5_cnt == iint[9:8]);
if(ich5_v) ich5_cnt = 0;
else ich5_cnt = ich5_cnt + 1;
ich6_v = ivalid[3] & (ich6_cnt == iint[7:6]);
if(ich6_v) ich6_cnt = 0;
else ich6_cnt = ich6_cnt + 1;
ich7_v = ivalid[2] & (ich7_cnt == iint[5:4]);
if(ich7_v) ich7_cnt = 0;
else ich7_cnt = ich7_cnt + 1;
ich8_v = ivalid[1] & (ich8_cnt == iint[3:2]);
if(ich8_v) ich8_cnt = 0;
else ich8_cnt = ich8_cnt + 1;
ich9_v = ivalid[0] & (ich9_cnt == iint[1:0]);
if(ich9_v) ich9_cnt = 0;
else ich9_cnt = ich9_cnt + 1;
 
set_tag(1'b1, { 1'b0, // Slot 1
1'b0, // Slot 2
ich0_v, ich1_v, ich2_v, ich3_v, ich4_v,
ich5_v, ich6_v, ich7_v, ich8_v, ich9_v} );
 
set_req( { och0_v, och1_v, och2_v, och3_v, och4_v,
och5_v, och6_v, och7_v, och8_v, och9_v} );
 
end
while(sync) @(posedge clk);
end
end
endtask
 
////////////////////////////////////////////////////////////////////
//
// Modules
//
 
ac97_codec_sin u0(
.clk( clk ),
.rst( rst ),
.sync( sync ),
.slt0( out_slt0 ),
.slt1( out_slt1 ),
.slt2( out_slt2 ),
.slt3( out_slt3 ),
.slt4( out_slt4 ),
.slt5( out_slt5 ),
.slt6( out_slt6 ),
.slt7( out_slt7 ),
.slt8( out_slt8 ),
.slt9( out_slt9 ),
.slt10( out_slt10 ),
.slt11( out_slt11 ),
.slt12( out_slt12 ),
.sdata_in( sdata_in )
);
 
ac97_codec_sout u1(
.clk( clk ),
.rst( rst ),
.sync( sync ),
.slt0( in_slt0 ),
.slt1( in_slt1 ),
.slt2( in_slt2 ),
.slt3( in_slt3 ),
.slt4( in_slt4 ),
.slt5( in_slt5 ),
.slt6( in_slt6 ),
.slt7( in_slt7 ),
.slt8( in_slt8 ),
.slt9( in_slt9 ),
.slt10( in_slt10 ),
.slt11( in_slt11 ),
.slt12( in_slt12 ),
.sdata_out( sdata_out )
);
 
endmodule
 
 
/trunk/bench/verilog/tests.v
0,0 → 1,875
/////////////////////////////////////////////////////////////////////
//// ////
//// Tests ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: tests.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
 
 
task show_errors;
 
begin
 
$display("\n");
$display(" +--------------------+");
$display(" | Total ERRORS: %0d |", error_cnt);
$display(" +--------------------+");
 
end
endtask
 
 
task basic1;
 
reg [31:0] data;
reg [31:0] data1;
reg [31:0] data2;
integer size, frames, m;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Basic AC97 I/O Test & Reg Wr ... ***");
$display("*****************************************************\n");
 
 
wb_busy = 1;
m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
 
wb_busy = 0;
oc0_dma_en = 1;
oc1_dma_en = 1;
oc2_dma_en = 1;
oc3_dma_en = 1;
oc4_dma_en = 1;
oc5_dma_en = 1;
ic0_dma_en = 1;
ic1_dma_en = 1;
ic2_dma_en = 1;
 
for(n=0;n<256;n=n+1)
begin
oc0_mem[n] = $random;
oc1_mem[n] = $random;
oc2_mem[n] = $random;
oc3_mem[n] = $random;
oc4_mem[n] = $random;
oc5_mem[n] = $random;
ic0_mem[n] = $random;
ic1_mem[n] = $random;
ic2_mem[n] = $random;
end
 
u1.init(0);
frames = 139;
 
fork
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1111_1111_11, // Output slots valid bits
10'b1111_1111_11, // Input slots valid bits
20'b00_00_00_00_00_00_00_00_00_00, // Output Slots intervals
20'b00_00_00_00_00_00_00_00_00_00 // Input Slots intervals
);
 
begin // Do a register Write
repeat(2) @(posedge sync);
 
for(n=0;n<75;n=n+1)
begin
@(negedge sync);
repeat(230) @(posedge bit_clk);
 
repeat(n) @(posedge bit_clk);
 
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr1(`CRAC,4'hf, {9'h0, n[6:0], 16'h1234 + n[7:0]} );
wb_busy = 0;
 
while(!int) @(posedge clk);
end
end
join
 
repeat(300) @(posedge bit_clk);
 
for(n=0;n<75;n=n+1)
begin
data2 = {9'h0, n[6:0], 16'h1234 + n[7:0]};
tmp = u1.rs2_mem[n];
data1[15:0] = tmp[19:4];
 
tmp = u1.rs1_mem[n];
data1[31:16] = {9'h0, tmp[18:12]};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Register Write Data %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
 
end
 
size = frames - 4;
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs3_mem[n];
data = oc0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs4_mem[n];
data = oc1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs6_mem[n];
data = oc2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs7_mem[n];
data = oc3_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs8_mem[n];
data = oc4_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs9_mem[n];
data = oc5_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is3_mem[n];
data = ic0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is4_mem[n];
data = ic1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is6_mem[n];
data = ic2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
repeat(10) @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task basic2;
 
reg [31:0] data;
reg [31:0] data1;
reg [31:0] data2;
integer size, frames, m;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** Basic AC97 I/O Test & Reg Rd ... ***");
$display("*****************************************************\n");
 
wb_busy = 1;
m0.wb_wr1(`INTM,4'hf, 32'h0000_0003);
m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
 
wb_busy = 0;
oc0_dma_en = 1;
oc1_dma_en = 1;
oc2_dma_en = 1;
oc3_dma_en = 1;
oc4_dma_en = 1;
oc5_dma_en = 1;
ic0_dma_en = 1;
ic1_dma_en = 1;
ic2_dma_en = 1;
 
for(n=0;n<256;n=n+1)
begin
oc0_mem[n] = $random;
oc1_mem[n] = $random;
oc2_mem[n] = $random;
oc3_mem[n] = $random;
oc4_mem[n] = $random;
oc5_mem[n] = $random;
ic0_mem[n] = $random;
ic1_mem[n] = $random;
ic2_mem[n] = $random;
end
 
u1.init(0);
frames = 139;
 
fork
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1111_1111_11, // Output slots valid bits
10'b1111_1111_11, // Input slots valid bits
20'b00_00_00_00_00_00_00_00_00_00, // Output Slots intervals
20'b00_00_00_00_00_00_00_00_00_00 // Input Slots intervals
);
 
begin // Do a register Write
repeat(2) @(posedge sync);
 
for(n=0;n<75;n=n+1)
begin
@(negedge sync);
repeat(230) @(posedge bit_clk);
 
repeat(n) @(posedge bit_clk);
 
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_wr1(`CRAC,4'hf, {1'b1, 8'h0, n[6:0], 16'h1234 + n[7:0]} );
wb_busy = 0;
 
while(!int) @(posedge clk);
 
while(wb_busy) @(posedge clk);
wb_busy = 1;
m0.wb_rd1(`CRAC,4'hf, reg_mem[n] );
wb_busy = 0;
 
end
end
join
 
repeat(300) @(posedge bit_clk);
 
for(n=0;n<75;n=n+1)
begin
 
tmp = u1.is2_mem[n];
data2 = {16'h0, tmp[19:4]};
tmp = reg_mem[n];
data1 = {16'h0, tmp[15:0]};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Register Read Data %0d Mismatch Expected: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
 
end
 
size = frames - 4;
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs3_mem[n];
data = oc0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs4_mem[n];
data = oc1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs6_mem[n];
data = oc2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs7_mem[n];
data = oc3_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs8_mem[n];
data = oc4_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs9_mem[n];
data = oc5_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is3_mem[n];
data = ic0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is4_mem[n];
data = ic1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is6_mem[n];
data = ic2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
 
task vsr1;
 
reg [31:0] data;
reg [31:0] data1;
reg [31:0] data2;
integer size, frames, m;
 
begin
$display("\n\n");
$display("*****************************************************");
$display("*** VSR AC97 I/O Test ... ***");
$display("*****************************************************\n");
 
wb_busy = 1;
m0.wb_wr1(`OCC0,4'hf, 32'h7373_7373);
m0.wb_wr1(`OCC1,4'hf, 32'h0000_7373);
m0.wb_wr1(`ICC,4'hf, 32'h0073_7373);
 
wb_busy = 0;
oc0_dma_en = 1;
oc1_dma_en = 1;
oc2_dma_en = 1;
oc3_dma_en = 1;
oc4_dma_en = 1;
oc5_dma_en = 1;
ic0_dma_en = 1;
ic1_dma_en = 1;
ic2_dma_en = 1;
 
for(n=0;n<256;n=n+1)
begin
oc0_mem[n] = $random;
oc1_mem[n] = $random;
oc2_mem[n] = $random;
oc3_mem[n] = $random;
oc4_mem[n] = $random;
oc5_mem[n] = $random;
ic0_mem[n] = $random;
ic1_mem[n] = $random;
ic2_mem[n] = $random;
end
 
u1.init(0);
 
frames = 132;
 
u1.tx1( frames, // Number of frames to process
0, // How many frames before codec is ready
10'b1101_1110_00, // Output slots valid bits
10'b1101_0000_00, // Input slots valid bits
20'b01_01_00_01_01_01_01_00_00_00, // Output Slots intervals
20'b01_01_00_01_00_00_00_00_00_00 // Input Slots intervals
);
 
size = (frames - 4)/2;
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs3_mem[n];
data = oc0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs4_mem[n];
data = oc1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs6_mem[n];
data = oc2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs7_mem[n];
data = oc3_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH3 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs8_mem[n];
data = oc4_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH4 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.rs9_mem[n];
data = oc5_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: Out. CH5 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is3_mem[n];
data = ic0_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH0 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is4_mem[n];
data = ic1_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH1 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
for(n=0;n<size;n=n+1)
begin
data1 = u1.is6_mem[n];
data = ic2_mem[n[8:1]];
 
if(~n[0]) data2 = {12'h0, data[15:0], 4'h0};
else data2 = {12'h0, data[31:16], 4'h0};
 
if( (data1 !== data2) |
(^data1 === 1'hx) |
(^data2 === 1'hx)
)
begin
$display("ERROR: In. CH2 Sample %0d Mismatch Sent: %h Got: %h",
n, data2, data1);
error_cnt = error_cnt + 1;
end
end
 
repeat(10) @(posedge clk);
 
show_errors;
$display("*****************************************************");
$display("*** Test DONE ... ***");
$display("*****************************************************\n\n");
 
end
endtask
 
 
/trunk/bench/verilog/wb_model_defines.v
0,0 → 1,55
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE Model Definitions ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/mem_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: wb_model_defines.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
//
 
`timescale 1ns / 10ps
/trunk/bench/verilog/ac97_codec_sin.v
0,0 → 1,205
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Codec ////
//// Serial Input Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: ac97_codec_sin.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
 
`include "ac97_defines.v"
 
module ac97_codec_sin(clk, rst,
 
sync,
slt0, slt1, slt2, slt3, slt4, slt5,
slt6, slt7, slt8, slt9, slt10, slt11, slt12,
 
sdata_in
);
 
input clk, rst;
 
// --------------------------------------
// Misc Signals
input sync;
output [15:0] slt0;
output [19:0] slt1;
output [19:0] slt2;
output [19:0] slt3;
output [19:0] slt4;
output [19:0] slt5;
output [19:0] slt6;
output [19:0] slt7;
output [19:0] slt8;
output [19:0] slt9;
output [19:0] slt10;
output [19:0] slt11;
output [19:0] slt12;
 
// --------------------------------------
// AC97 Codec Interface
input sdata_in;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg sdata_in_r;
reg [19:0] sr;
 
reg [15:0] slt0;
reg [19:0] slt1;
reg [19:0] slt2;
reg [19:0] slt3;
reg [19:0] slt4;
reg [19:0] slt5;
reg [19:0] slt6;
reg [19:0] slt7;
reg [19:0] slt8;
reg [19:0] slt9;
reg [19:0] slt10;
reg [19:0] slt11;
reg [19:0] slt12;
 
wire [12:0] le;
 
////////////////////////////////////////////////////////////////////
//
// Latch Enable logic
//
 
// Sync Edge Detector
reg sync_r;
wire sync_e;
 
always @(posedge clk)
sync_r <= #1 sync;
 
assign sync_e = sync & !sync_r;
 
// Frame Counter
reg [7:0] cnt;
 
always @(posedge clk)
if(sync_e) cnt <= #1 0;
else cnt <= #1 cnt + 1;
 
assign le[0] = (cnt == 16);
assign le[1] = (cnt == 36);
assign le[2] = (cnt == 56);
assign le[3] = (cnt == 76);
assign le[4] = (cnt == 96);
assign le[5] = (cnt == 116);
assign le[6] = (cnt == 136);
assign le[7] = (cnt == 156);
assign le[8] = (cnt == 176);
assign le[9] = (cnt == 196);
assign le[10] = (cnt == 216);
assign le[11] = (cnt == 236);
assign le[12] = (cnt == 0);
 
////////////////////////////////////////////////////////////////////
//
// Output registers
//
 
always @(posedge clk)
if(le[0]) slt0 <= #1 sr[15:0];
 
always @(posedge clk)
if(le[1]) slt1 <= #1 sr;
 
always @(posedge clk)
if(le[2]) slt2 <= #1 sr;
 
always @(posedge clk)
if(le[3]) slt3 <= #1 sr;
 
always @(posedge clk)
if(le[4]) slt4 <= #1 sr;
 
always @(posedge clk)
if(le[5]) slt5 <= #1 sr;
 
always @(posedge clk)
if(le[6]) slt6 <= #1 sr;
 
always @(posedge clk)
if(le[7]) slt7 <= #1 sr;
 
always @(posedge clk)
if(le[8]) slt8 <= #1 sr;
 
always @(posedge clk)
if(le[9]) slt9 <= #1 sr;
 
always @(posedge clk)
if(le[10]) slt10 <= #1 sr;
 
always @(posedge clk)
if(le[11]) slt11 <= #1 sr;
 
always @(posedge clk)
if(le[12]) slt12 <= #1 sr;
 
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
 
always @(negedge clk)
sdata_in_r <= #1 sdata_in;
 
always @(posedge clk)
sr <= #1 {sr[18:0], sdata_in_r };
 
endmodule
 
 
/trunk/bench/verilog/ac97_codec_sout.v
0,0 → 1,191
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE AC 97 Codec ////
//// Serial Output Block ////
//// ////
//// ////
//// Author: Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/ac97_ctrl/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Rudolf Usselmann ////
//// rudi@asics.ws ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// CVS Log
//
// $Id: ac97_codec_sout.v,v 1.1 2002-02-13 08:22:32 rudi Exp $
//
// $Date: 2002-02-13 08:22:32 $
// $Revision: 1.1 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: not supported by cvs2svn $
//
//
//
 
`include "ac97_defines.v"
 
module ac97_codec_sout(clk, rst,
 
sync, slt0, slt1, slt2, slt3, slt4, slt5,
slt6, slt7, slt8, slt9, slt10, slt11, slt12,
 
sdata_out
);
 
input clk, rst;
 
// --------------------------------------
// Misc Signals
input sync;
input [15:0] slt0;
input [19:0] slt1;
input [19:0] slt2;
input [19:0] slt3;
input [19:0] slt4;
input [19:0] slt5;
input [19:0] slt6;
input [19:0] slt7;
input [19:0] slt8;
input [19:0] slt9;
input [19:0] slt10;
input [19:0] slt11;
input [19:0] slt12;
 
// --------------------------------------
// AC97 Codec Interface
output sdata_out;
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg sdata_out_r;
 
reg [15:0] slt0_r;
reg [19:0] slt1_r;
reg [19:0] slt2_r;
reg [19:0] slt3_r;
reg [19:0] slt4_r;
reg [19:0] slt5_r;
reg [19:0] slt6_r;
reg [19:0] slt7_r;
reg [19:0] slt8_r;
reg [19:0] slt9_r;
reg [19:0] slt10_r;
reg [19:0] slt11_r;
reg [19:0] slt12_r;
 
reg sync_r;
wire sync_e;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
// Sync Edge detector
always @(posedge clk)
sync_r <= #1 sync;
 
assign sync_e = sync & !sync_r;
 
////////////////////////////////////////////////////////////////////
//
// Serial Shift Register
//
 
/*
always @(negedge clk)
sdata_out_r <= #1 slt0_r[15];
 
//assign sdata_out = sdata_out_r;
*/
 
assign sdata_out = slt0_r[15];
 
always @(posedge clk)
if(sync_e) slt0_r <= #1 slt0;
else slt0_r <= #1 {slt0_r[14:0], slt1_r[19]};
 
always @(posedge clk)
if(sync_e) slt1_r <= #1 slt1;
else slt1_r <= #1 {slt1_r[18:0], slt2_r[19]};
 
always @(posedge clk)
if(sync_e) slt2_r <= #1 slt2;
else slt2_r <= #1 {slt2_r[18:0], slt3_r[19]};
 
always @(posedge clk)
if(sync_e) slt3_r <= #1 slt3;
else slt3_r <= #1 {slt3_r[18:0], slt4_r[19]};
 
always @(posedge clk)
if(sync_e) slt4_r <= #1 slt4;
else slt4_r <= #1 {slt4_r[18:0], slt5_r[19]};
 
always @(posedge clk)
if(sync_e) slt5_r <= #1 slt5;
else slt5_r <= #1 {slt5_r[18:0], slt6_r[19]};
 
always @(posedge clk)
if(sync_e) slt6_r <= #1 slt6;
else slt6_r <= #1 {slt6_r[18:0], slt7_r[19]};
 
always @(posedge clk)
if(sync_e) slt7_r <= #1 slt7;
else slt7_r <= #1 {slt7_r[18:0], slt8_r[19]};
 
always @(posedge clk)
if(sync_e) slt8_r <= #1 slt8;
else slt8_r <= #1 {slt8_r[18:0], slt9_r[19]};
 
always @(posedge clk)
if(sync_e) slt9_r <= #1 slt9;
else slt9_r <= #1 {slt9_r[18:0], slt10_r[19]};
 
always @(posedge clk)
if(sync_e) slt10_r <= #1 slt10;
else slt10_r <= #1 {slt10_r[18:0], slt11_r[19]};
 
always @(posedge clk)
if(sync_e) slt11_r <= #1 slt11;
else slt11_r <= #1 {slt11_r[18:0], slt12_r[19]};
 
always @(posedge clk)
if(sync_e) slt12_r <= #1 slt12;
else slt12_r <= #1 {slt12_r[18:0], 1'b0 };
 
 
endmodule
 

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