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URL https://opencores.org/ocsvn/ag_6502/ag_6502/trunk

Subversion Repositories ag_6502

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    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/ag_6502/trunk/agat7/ag_main.v
19,9 → 19,11
//
//////////////////////////////////////////////////////////////////////////////////
 
module ROM2kx8(input[10:0] adr, input cs, output[7:0] DO);
module ROM2kx8(input CLK, input[10:0] AB, input CS, output[7:0] DO);
reg[7:0] mem[0:2047];
assign DO = cs?mem[adr]:8'bZ;
reg[7:0] R;
assign DO = CS? R: 8'bZ;
always @(posedge CLK) if (CS) R <= mem[AB];
initial begin
`include "monitor7.v"
end
28,8 → 30,9
endmodule
 
module ag_main(
input clk50,
input clk50x,
input[3:0] btns,
input[3:0] switches,
output[7:0] leds,
output[3:0] controls,
output[4:0] vga_bus,
40,9 → 43,13
// assign controls = 0;
// assign vga_bus = 0;
wire clk1, clk10;
wire clk1, clk1x, clk10, clk50;
reg turbo = 0;
BUFG bg1(clk50, clk50x);
clk_div#5 cd5(clk50, clk10);
clk_div#10 cd10(clk10, clk1);
clk_div#10 cd10(clk10, clk1x);
BUFGMUX bgm1(clk1, clk1x, clk10, turbo);
// assign clk1 = turbo?clk10:clk1x;
 
wire clk_vram;
58,7 → 65,7
RAM32Kx8x16 base_ram(phi_2, AB[14:0], ram_cs, read, DI, DO,
clk_vram, AB2, 1, DI2);
ROM2kx8 rom1(AB[10:0], rom_cs, DI);
ROM2kx8 rom1(phi_2, AB[10:0], rom_cs, DI);
wire [3:0] AB_HH = AB[15:12];
wire [3:0] AB_HL = AB[11:8];
75,7 → 82,11
wire AB_C01X = AB_C0XX && (AB_LH == 4'h1);
wire AB_C02X = AB_C0XX && (AB_LH == 4'h2);
wire AB_C03X = AB_C0XX && (AB_LH == 4'h3);
wire AB_C04X = AB_C0XX && (AB_LH == 4'h4);
wire AB_C05X = AB_C0XX && (AB_LH == 4'h5);
wire AB_C7XX = AB_CXXX && (AB_HL == 4'h7);
 
reg timer_ints = 0;
assign rom_cs = AB_FXXX && AB[11]; // F800-FFFF
assign ram_cs = !AB[15];
85,12 → 96,13
wire reset;
wire WE = ~read; // write enable
supply0 IRQ; // interrupt request
supply0 NMI; // non-maskable interrupt request
wire NMI; // non-maskable interrupt request
supply1 RDY; // Ready signal. Pauses CPU when RDY=0
supply1 SO; // Set Overflow, not used.
wire SYNC;
assign NMI = timer_ints & vga_bus[0];
reg[7:0] vmode = 0;
wire[7:0] key_reg;
117,9 → 129,14
ag_keyb keyb(phi_2, ps2_bus, key_reg, key_clear, key_rus, key_rst, key_pause);
assign DI = (AB_C00X && !WE)?key_reg:8'bZ;
wire reset_all = reset | reset_auto | key_rst;
always @(posedge phi_2) begin
turbo <= switches[0];
key_clear <= AB_C01X;
if (AB_C04X) timer_ints <= 1;
else if (AB_C05X || reset_all) timer_ints <= 0;
 
if (AB_C02X) tape_out_reg <= ~tape_out_reg;
if (AB_C03X) beep_reg <= ~beep_reg;
if (AB_C7XX) vmode <= AB_L;
130,6 → 147,6
ag6502_ext_clock clk(clk50, clk1, phi_1, phi_2);
ag6502 cpu(clk1, phi_1, phi_2, AB, read, DI, DO,
RDY & ~key_pause, ~(reset | reset_auto | key_rst), ~IRQ, ~NMI, SO, SYNC);
RDY & ~key_pause, ~reset_all, ~IRQ, ~NMI, SO, SYNC);
 
endmodule
/ag_6502/trunk/agat7/chip1.ucf
6,15 → 6,14
NET "b1" PULLDOWN;
NET "b2" PULLDOWN;
 
NET "b1" CLOCK_DEDICATED_ROUTE = FALSE;
NET "b2" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rot_a" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rot_b" CLOCK_DEDICATED_ROUTE = FALSE;
NET "rot_center" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "b1" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "b2" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "rot_a" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "rot_b" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "rot_center" CLOCK_DEDICATED_ROUTE = FALSE;
 
NET "clk" LOC = C9 | IOSTANDARD = "LVCMOS33";
NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
//PIN "cpu1/cd5/DCM_SP_inst.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
//NET "clk" CLOCK_DEDICATED_ROUTE = FALSE;
NET "ROT_A" LOC = K18 | IOSTANDARD = "LVTTL" | PULLUP;
NET "ROT_B" LOC = G18 | IOSTANDARD = "LVTTL" | PULLUP;
NET "ROT_CENTER" LOC = V16 | IOSTANDARD = "LVTTL" | PULLDOWN;
60,3 → 59,8
NET "PS2_CLK" LOC = G14 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
NET "PS2_DATA" LOC = G13 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW | PULLUP;
NET "PS2_CLK" CLOCK_DEDICATED_ROUTE = FALSE;
 
NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
/ag_6502/trunk/agat7/ag_6502.v
41,7 → 41,7
`else
 
module ag6502_phase_shift(input baseclk, input phi_0, output reg phi_1);
parameter DELAY = 1; // delay in semi-waves of baseclk
parameter DELAY = 1; // delay in waves of baseclk
initial phi_1 = 0;
integer cnt = 0;
/ag_6502/trunk/agat7/chip1.v
25,6 → 25,7
input clk,
input b1,
input b2,
input[3:0] SW,
input rot_a, rot_b, rot_center,
output[7:0] led,
output vga_red,
62,6 → 63,6
// assign j4 = 0, vga_bus = 0;
wire[3:0] btns = {0, 0, b2, b1};
ag_main agate(clk, btns, led, j4, vga_bus, ps2_bus);
ag_main agate(clk, btns, SW, led, j4, vga_bus, ps2_bus);
endmodule
/ag_6502/trunk/agat7/agat7.xise
52,18 → 52,6
</file>
</files>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="states.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="monitor7.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="agathe7.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
 
<properties>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
371,4 → 359,16
 
<libraries/>
 
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
<file xil_pn:name="states.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="monitor7.v" xil_pn:type="FILE_VERILOG"/>
<file xil_pn:name="agathe7.v" xil_pn:type="FILE_VERILOG"/>
</autoManagedFiles>
 
</project>

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