OpenCores
URL https://opencores.org/ocsvn/apbtoaes128/apbtoaes128/trunk

Subversion Repositories apbtoaes128

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/apbtoaes128/trunk/rtl/sBox.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
/apbtoaes128/trunk/rtl/host_interface.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
96,7 → 96,7
output [31:0] PRDATA,
//INPUTS
input [3:0] PADDR,
input [31:0] PWDATA,
input [12:0] PWDATA,
input PWRITE,
input PENABLE,
input PSEL,
162,7 → 162,7
localparam WAIT = 3'd3;
localparam OUTPUT = 3'd4;
 
reg [31:0] bus_out;
wire [31:0] bus_out;
reg [31:0] bus_out_mux;
reg cnt_en;
reg enable_clear;
180,6 → 180,7
wire errc;
wire ccfc;
wire aes_cr_wr_en;
//wire aes_sr_wr_en;
wire wr_err_en;
wire rd_err_en;
wire write_completed;
194,10 → 195,12
reg [2:0] state, next_state;
reg [1:0] cnt;
reg dma_req;
wire enable;
 
// Write and read enable signals
assign write_en = PSEL & PENABLE & PWRITE;
assign read_en = PSEL & ~PWRITE;
assign read_en = (PSEL & ~PWRITE & (ccf_set | ccf))?1'b1:
((PSEL & ~PWRITE)&(PADDR >= AES_KEYR0 & PADDR <= AES_IVR3 ))?1'b1:1'b0;
 
// Configuration Register Logic
assign dma_out_en = aes_cr[10];
218,7 → 221,7
always @(posedge PCLK, negedge PRESETn)
begin
if(!PRESETn)
aes_cr <= AES_CR_RESET;
aes_cr <= AES_CR_RESET[10:0];
else
begin
if(enable_clear)
241,12 → 244,15
end
// Status Register Logic
assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;
//assign aes_sr_wr_en = (PADDR == AES_SR) & write_en & access_permission;
 
always @(posedge PCLK, negedge PRESETn)
begin
if(!PRESETn)
begin
{wr_err, rd_err, ccf} <= AES_SR_RESET;
 
end
else
begin
// Write Error Flag
265,7 → 271,7
 
// Computation Complete Flag
if(ccf_set)
ccf <= 1'b1;
ccf <= 1'b1;
else
if(ccfc && aes_cr_wr_en)// && access_permission)
ccf <= 1'b0;
404,7 → 410,7
always @(posedge PCLK, negedge PRESETn)
begin
if(!PRESETn)
dma_req <= 0;
dma_req <= 1'b0;
else
dma_req <= cnt[0];
end
423,18 → 429,37
AES_CR:
bus_out_mux = {{19{1'b0}}, aes_cr[10:7], 2'b00, aes_cr[6:0]};
AES_SR:
bus_out_mux = {{29{1'b0}}, wr_err, rd_err, ccf};
begin
 
bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
/*
if(~ccfc && ~aes_cr_wr_en)
begin
bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf)?1'b1:(ccfc && aes_cr_wr_en)?1'b0:1'b1};
end
else
begin
bus_out_mux = {{29{1'b0}}, wr_err, rd_err, (ccf_set | ccf)?1'b1:1'b0};
end
*/
end
AES_DINR, AES_DOUTR:
bus_out_mux = col_bus;
AES_KEYR0, AES_KEYR1, AES_KEYR2, AES_KEYR3:
bus_out_mux = key_bus;
if(!enable)
bus_out_mux = key_bus;
AES_IVR0, AES_IVR1, AES_IVR2, AES_IVR3:
if(!enable)
bus_out_mux = iv_bus;
endcase
end
 
// The output Bus is registered
 
assign bus_out =(read_en)? bus_out_mux:32'd0;
 
/*
always @(posedge PCLK, negedge PRESETn)
begin
if(!PRESETn)
443,5 → 468,6
if(read_en)
bus_out <= bus_out_mux;
end
*/
 
endmodule
/apbtoaes128/trunk/rtl/mix_columns.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
82,9 → 82,9
input [31:0] mix_in
);
 
localparam SIZE = 32;
localparam WORD_SIZE = 8;
localparam NUM_WORDS = 4;
localparam integer SIZE = 32;
localparam integer WORD_SIZE = 8;
localparam integer NUM_WORDS = 4;
 
wire [WORD_SIZE - 1 : 0] col [0 : NUM_WORDS - 1];
wire [WORD_SIZE - 1 : 0] sum_p[0 : NUM_WORDS - 1];
/apbtoaes128/trunk/rtl/key_expander.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
76,8 → 76,8
module key_expander
(
// OUTPUTS
output [127:0] key_out,
output [ 31:0] g_in,
output [127:0] key_out,
output [ 31:0] g_in,
// INPUTS
input [ 31:0] g_out,
input [127:0] key_in,
86,16 → 86,16
input enc_dec
);
 
localparam KEY_WIDTH = 32;
localparam KEY_NUM = 4;
localparam WORD = 8;
localparam ROUNDS = 10;
localparam integer KEY_WIDTH = 32;
localparam integer KEY_NUM = 4;
localparam integer WORD = 8;
localparam integer ROUNDS = 10;
 
wire [KEY_WIDTH - 1 : 0] key [0 : KEY_NUM - 1];
wire [ WORD - 1 : 0] rot_in[0 : KEY_NUM - 1];
wire [KEY_WIDTH - 1 : 0] g_func;
reg [ WORD - 1 : 0] rc_dir, rc_inv;
wire [ WORD - 1 : 0] rc;
wire [KEY_WIDTH - 1 : 0] key [0 : KEY_NUM - 1];
wire [ WORD - 1 : 0] rot_in[0 : KEY_NUM - 1];
wire [KEY_WIDTH - 1 : 0] g_func;
reg [ WORD - 1 : 0] rc_dir, rc_inv;
wire [ WORD - 1 : 0] rc;
 
//=====================================================================================
// Key Generation
103,9 → 103,9
generate
genvar i;
for(i = 0; i < KEY_NUM; i = i + 1)
begin
begin
assign key[KEY_NUM - 1 - i] = key_in[KEY_WIDTH*(i + 1) - 1 : KEY_WIDTH*i];
end
end
endgenerate
 
//=====================================================================================
/apbtoaes128/trunk/rtl/control_unit.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
88,7 → 88,7
output reg iv_cnt_en,
output reg iv_cnt_sel,
output reg key_derivation_en,
output reg end_comp,
output end_comp,
output key_init,
output key_gen,
output mode_ctr,
233,9 → 233,11
reg [3:0] rd_count;
 
reg rd_count_en;
//reg end_aes_pp1, end_aes_pp2;
wire op_key_derivation;
wire first_round;
wire [1:0] op_mode;
wire enc_dec;
 
// State Flops Definition
always @(posedge clk, negedge rst_n)
361,6 → 363,33
// Output Logic
assign end_comp = (state == READY)?ENABLE:DISABLE;
 
/*
always @(posedge clk, negedge rst_n)
begin
if(!rst_n)
begin
end_aes_pp1 <= 1'b0;
end_aes_pp2 <= 1'b0;
end_comp <= 1'b0;
end
else
if(state == READY)
begin
end_aes_pp1 <= ENABLE;
//end_aes_pp2 <= end_aes_pp1;
end_comp <= end_aes_pp1 ;
end
else
begin
end_aes_pp1 <= DISABLE;
//end_aes_pp2 <= end_aes_pp1;
end_comp <= end_aes_pp1 ;
end
 
end
*/
always @(*)
begin
sbox_sel = COL_0;
376,7 → 405,7
iv_cnt_sel = IV_BUS;
bypass_key_en = DISABLE;
key_derivation_en = DISABLE;
end_comp = DISABLE;
//end_comp = DISABLE;
case(state)
ROUND0_COL0:
begin
546,7 → 575,7
end
READY:
begin
end_comp = ENABLE;
//end_comp = ENABLE;
if(op_mode == KEY_DERIVATION)
key_derivation_en = ENABLE;
end
/apbtoaes128/trunk/rtl/aes_core.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
/apbtoaes128/trunk/rtl/aes_ip.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
110,9 → 110,11
wire write_en;
wire read_en;
wire first_block;
//wire pwdata_host_interface;
 
assign PREADY = 1'b1;
assign PSLVERR = 1'b0;
//assign pwdata_host_interface = PWDATA[12:0];
 
host_interface HOST_INTERFACE
(
135,7 → 137,7
.start_core ( start ),
.PRDATA ( PRDATA ),
.PADDR ( PADDR ),
.PWDATA ( PWDATA ),
.PWDATA ( PWDATA[12:0] ),
.PWRITE ( PWRITE ),
.PENABLE ( PENABLE ),
.PSEL ( PSEL ),
/apbtoaes128/trunk/rtl/sBox_8.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://opencores.org/ocsvn/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
302,10 → 302,10
 
 
wire [7:0] base_new_enc, base_new_dec, base_new;
wire [7:0] base_enc, base_dec;
//wire [7:0] base_enc, base_dec;
wire [3:0] out_gf_inv8_stage1;
wire [7:0] out_gf_inv8_1;
wire [7:0] out_gf_inv8_2;
//wire [7:0] out_gf_inv8_2;
 
reg [3:0] out_gf_pp;
reg [7:0] base_new_pp;
/apbtoaes128/trunk/rtl/data_swap.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
99,13 → 99,15
generate
genvar i, j;
for(i = 0; i < TYPES; i = i + 1)
begin:BLOCK
for(j = 0; j < WIDTH; j = j + 1)
begin
begin: SUB_BLOCK
if(i != 3)
assign words[i][j] = data_in[(WIDTH - (WIDTH/2**i)) - 2*(WIDTH/2**i)*(j/(WIDTH/2**i)) + j];
else
assign words[i][j] = data_in[WIDTH - 1 - j];
end
end
endgenerate
 
assign data_swap = words[swap_type];
/apbtoaes128/trunk/rtl/datapath.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
241,7 → 241,7
reg key_sel_pp1;
reg rk_out_sel_pp1, rk_out_sel_pp2;
reg last_round_pp1, last_round_pp2;
reg end_aes_pp1, end_aes_pp2;
//reg end_aes_pp2;//end_aes_pp1, end_aes_pp2;
 
assign key_bus = key_mux_out;
assign iv_bus = iv_mux_out;
302,35 → 302,40
// IV and BKP Registers
generate
genvar l;
for(l = 0; l < 4; l = l + 1)
 
for(l = 0; l < 4;l=l+1)
begin
always @(posedge clk, negedge rst_n)
begin
begin
if(!rst_n)
begin
begin
iv[l] <= {32{1'b0}};
bkp[l] <= {32{1'b0}};
bkp_1[l] <= {32{1'b0}};
end
end
else
begin
begin
if(l == 3)
begin
begin
if(iv_en[l] || iv_cnt_en)
iv[l] <= (iv_cnt_sel) ? iv[l] + 1'b1 : bus_in;
end
end
else
begin
begin
if(iv_en[l])
iv[l] <= bus_in;
end
end
 
if(bkp_en[l])
bkp[l] <= (mode_ctr) ? bus_swap : ((mode_cbc && enc_dec) ? col_in : bkp_1[l]);
//bkp[l] <= (mode_ctr) ? bus_swap : ((mode_cbc && enc_dec) ? col_in : bkp_1[l]);
bkp[l] <= (mode_ctr) ? bus_swap : ((mode_cbc && enc_dec) ? col_in[32*(l + 1) - 1 : 32*l] : bkp_1[l]);
 
if(bkp_en[l])
bkp_1[l] <= col_in;
end
bkp_1[l] <= col_in[32*(l + 1) - 1 : 32*l];
end
end
end
endgenerate
 
assign col_sel_w_bypass = (bypass_rk) ? col_sel : col_sel_pp2;
502,7 → 507,7
 
assign add_rk_out = (add_rk_sel) ? add_rd : (last_round_pp2 ? sbox_pp2 : mix_out_dec);
 
assign end_aes = end_aes_pp2;
assign end_aes = end_comp;//end_aes_pp2;
 
// Pipeline Registers for Control Signals
always @(posedge clk, negedge rst_n)
509,8 → 514,8
begin
if(!rst_n)
begin
end_aes_pp1 <= DISABLE;
end_aes_pp2 <= DISABLE;
//end_aes_pp1 <= DISABLE;
//end_aes_pp2 <= DISABLE;
 
col_sel_pp1 <= INPUT;
col_sel_pp2 <= INPUT;
565,8 → 570,8
last_round_pp1 <= last_round;
last_round_pp2 <= last_round_pp1;
 
end_aes_pp1 <= end_comp;
end_aes_pp2 <= end_aes_pp1;
//end_aes_pp1 <= end_comp;
//end_aes_pp2 <= end_comp;
end
end
endmodule
/apbtoaes128/trunk/rtl/shift_rows.v
5,9 → 5,9
////
////
////
//// This file is part of the APB to AES128 project
//// This file is part of the APB to I2C project
////
//// http://www.opencores.org/cores/apbtoaes128/
//// http://www.opencores.org/cores/apbi2c/
////
////
////
82,10 → 82,10
input [127 : 0] data_in // Input Bus
);
 
localparam BUS_WIDTH = 128; // Bus Width
localparam ST_WORD = 8; // Data Size of word in State MAtrix
localparam ST_LINE = 4; // Number of Lines of State Matrix
localparam ST_COL = 4; // Number of Columns of State Matrix
localparam integer BUS_WIDTH = 128; // Bus Width
localparam integer ST_WORD = 8; // Data Size of word in State MAtrix
localparam integer ST_LINE = 4; // Number of Lines of State Matrix
localparam integer ST_COL = 4; // Number of Columns of State Matrix
 
wire [ST_WORD - 1 : 0] state[0 : ST_LINE - 1][0 : ST_COL - 1];
wire [ST_WORD - 1 : 0] state_sft_l[0 : ST_LINE - 1][0 : ST_COL - 1];

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.