URL
https://opencores.org/ocsvn/ata/ata/trunk
Subversion Repositories ata
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- from Rev 6 to Rev 7
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Rev 6 → Rev 7
/trunk/verilog/ocidec-1/revision_history.txt
0,0 → 1,30
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Revision: 1.0 |
Date: June 28th, 2001 |
Author: Richard Herveille |
- Initial Verilog release (beta) |
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Revision: 1.1 |
Date: June 18th, 2001 |
Author: Richard Herveille |
- Fixed some incomplete port lists and some Verilog related issues. |
Design now completely compiles |
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Revision: 1.1a |
Date: July 3rd, 2001 |
Author: Richard Herveille |
- Rewrote some sections (controller.v, ata.v). Minor Verilog coding styles issues. |
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Revision: 1.2 |
Date: July 9th, 2001 |
Author: Richard Herveille |
- added 'timescale to all files |
- fixed error where control registers latched data on all rising clock edges, instead of |
when addressed. |
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