OpenCores
URL https://opencores.org/ocsvn/bluespec-h264/bluespec-h264/trunk

Subversion Repositories bluespec-h264

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/trunk/src_fpga/build/BRAM.v
0,0 → 1,102
//////////////////////////////////////////////////////////////////////
//
// BRAM.v
// Copyright (C) 2005 Carnegie Mellon University
//
// Description:
// Dual-ported BRAM Verilog model
//
// Revision History
// File created
// 5-18-2006, Eric Chung
//
//
// Triple read port, single write port synchronous Block RAM (synthesizable onto Xilinx block rams)
// Created on 5-17-2006
// Eric S. Chung
//
 
 
module BRAM(CLK, RST_N,
RD_ADDR, RD_RDY, RD_EN,
DOUT, DOUT_RDY, DOUT_EN,
WR_ADDR, WR_VAL, WR_EN);
 
// synopsys template
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input CLK;
input RST_N;
 
// Read Port
// req
input [addr_width - 1 : 0] RD_ADDR;
input RD_EN;
output RD_RDY;
// resp
output [data_width - 1 : 0] DOUT;
output DOUT_RDY;
input DOUT_EN;
 
// Write Port
// req
input [addr_width - 1 : 0] WR_ADDR;
input [data_width - 1 : 0] WR_VAL;
input WR_EN;
 
reg [data_width - 1 : 0] arr[lo:hi]; /*synthesis syn_ramstyle = "block_ram"*/
reg RD_REQ_MADE;
reg [data_width - 1 : 0] RAM_OUT;
reg [1:0] CTR;
FIFOL2#(.width(data_width)) q(.RST_N(RST_N),
.CLK(CLK),
.D_IN(RAM_OUT),
.ENQ(RD_REQ_MADE),
.DEQ(DOUT_EN),
.CLR(1'b0),
.D_OUT(DOUT),
.FULL_N(),
.EMPTY_N(DOUT_RDY));
 
assign RD_RDY = (CTR > 0) || DOUT_EN;
integer x;
 
always@(posedge CLK)
begin
 
if (!RST_N)
begin //Make simulation behavior consistent with Xilinx synthesis
// synopsys translate_off
for (x = lo; x < hi; x = x + 1)
begin
arr[x] <= 0;
end
// synopsys translate_on
CTR <= 2;
end
else
begin
RD_REQ_MADE <= RD_EN;
if (WR_EN)
arr[WR_ADDR] <= WR_VAL;
CTR <= (RD_EN) ?
(DOUT_EN) ? CTR : CTR - 1 :
(DOUT_EN) ? CTR + 1 : CTR;
RAM_OUT <= arr[RD_ADDR];
end
end // always@ (posedge CLK)
 
endmodule
/trunk/src_fpga/build/SRAM.v
0,0 → 1,157
/*
Notes -> We target a ZTB SRAM. It data is presented 2 cycles after the address data is presented.
 
cyc action
1 assign addr.
2 latch addr.
3 assign data.
4 latch data.
 
*/
 
//`include "FIFOL2.v"
 
`define NOP 0
`define RD_REQ 1
`define WR_REQ 2
 
module SRAM(CLK, RST_N,
// Bluespec method wires
RD_ADDR, RD_RDY, RD_EN,
DOUT, DOUT_RDY, DOUT_EN,
WR_ADDR, WR_VAL, WR_EN,
// Physical SRAM wires
DATA_BUS_O, DATA_BUS_I, DATA_BUS_T,
ADDR_O, WE_BYTES_N_O, WE_N_O, CE_N_O,
OE_N_O, CEN_N_O, ADV_LD_N_O, DUMMY_EN
);
 
// synopsys template
parameter addr_width = 1;
parameter data_width = 1;
parameter lo = 0;
parameter hi = 1;
input CLK;
input RST_N;
 
// Read Port
// req
input [addr_width - 1 : 0] RD_ADDR;
input RD_EN;
output RD_RDY;
// resp
output [data_width - 1 : 0] DOUT;
output DOUT_RDY;
input DOUT_EN;
 
// Write Port
// req
input [addr_width - 1 : 0] WR_ADDR;
input [data_width - 1 : 0] WR_VAL;
input WR_EN;
 
//Physical SRAM Wires
output [31 : 0] DATA_BUS_O;
input [31 : 0] DATA_BUS_I;
output DATA_BUS_T;
output [17 : 0] ADDR_O;
output [3 : 0] WE_BYTES_N_O;
output WE_N_O;
output CE_N_O;
output OE_N_O;
output CEN_N_O;
output ADV_LD_N_O;
input DUMMY_EN; // this signal is a dummy enable to
// make bluespec happy.
 
wire RD_REQ_MADE;
reg [1:0] CTR;
// Regs to pipeline incoming commands
reg [1:0] op_command_pipelined;
reg [1:0] op_command_active;
 
reg [data_width - 1:0] write_data_pipelined;
reg [data_width - 1:0] write_data_active;
 
FIFOL2#(.width(data_width)) q(.RST_N(RST_N),
.CLK(CLK),
.D_IN(DATA_BUS_I[data_width-1:0]),
.ENQ(RD_REQ_MADE),
.DEQ(DOUT_EN),
.CLR(1'b0),
.D_OUT(DOUT),
.FULL_N(),
.EMPTY_N(DOUT_RDY));
 
 
 
 
assign RD_RDY = (CTR > 0) || DOUT_EN;
// Some lines that enable the SRAM.
assign ADV_LD_N_O = 0;
assign CE_N_O = 0;
assign OE_N_O = 0;
assign CEN_N_O = 0;
 
// Tie the WE_N lines to the WR_EN.
assign WE_N_O = ~WR_EN;
assign WE_BYTES_N_O = {~WR_EN, ~WR_EN, ~WR_EN, ~WR_EN};
 
 
 
assign ADDR_O = (WR_EN)?(18'h0 | WR_ADDR): (18'h0 | RD_ADDR);
assign DATA_BUS_O = (op_command_active != `WR_REQ)?32'bzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz: (32'h0 | write_data_active);
assign DATA_BUS_T = (op_command_active != `WR_REQ); // deasserting data_bus_T will allow
// data_bus_O to drive the bus, which
// need only occur if write requests
// have been made.
// This line enqueues data into the data fifo.
assign RD_REQ_MADE = (op_command_active == `RD_REQ);
 
always@(posedge CLK)
begin
if(RD_REQ_MADE)
begin
$display("SRAM.v: Enqueuing %d", DATA_BUS_I);
end
if (!RST_N)
begin //Make simulation behavior consistent with Xilinx synthesis
op_command_pipelined <= `NOP;
op_command_active <= `NOP;
write_data_pipelined <= 0;
write_data_active <= 0;
CTR <= 2;
end
else
begin
write_data_pipelined <= WR_VAL;
write_data_active <= write_data_pipelined;
 
op_command_active <= op_command_pipelined;
if(RD_EN)
begin
op_command_pipelined <= `RD_REQ;
end
else if(WR_EN)
begin
op_command_pipelined <= `WR_REQ;
end
else
begin
op_command_pipelined <= `NOP;
end
CTR <= (RD_EN) ?
(DOUT_EN) ? CTR : CTR - 1 :
(DOUT_EN) ? CTR + 1 : CTR;
end
end // always@ (posedge CLK)
 
endmodule
/trunk/src_fpga/build/Makefile
1,7 → 1,7
#=======================================================================
# 6.375 Makefile for bsc-compile
#-----------------------------------------------------------------------
# $Id: Makefile,v 1.1 2008-06-26 17:48:16 jamey.hicks Exp $
# $Id: Makefile,v 1.2 2008-06-26 17:52:25 jamey.hicks Exp $
#
 
default : all
64,6 → 64,7
$(srcdir)/mkMemClient.bsv \
$(srcdir)/mkBRAMMemController.bsv \
$(srcdir)/mkRoundRobinMemScheduler.bsv \
$(srcdir)/mkReadFirstRoundRobinMemScheduler.bsv \
$(srcdir)/mkPriorityRoundRobinMemScheduler.bsv \
$(srcdir)/BRAM.bsv \
$(srcdir)/FIFO_2.bsv \
88,7 → 89,7
#BSC_OPTS = -u -show-module-use - -keep-fires -aggressive-conditions \
# -relax-method-earliness -relax-method-urgency -v
 
BSC_OPTS = -u -v -sim -aggressive-conditions
BSC_OPTS = +RTS -K40000k --RTS -u -v -verilog -aggressive-conditions
# Copy over the bluespec source
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.