OpenCores
URL https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk

Subversion Repositories debouncer_vhdl

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/debouncer_vhdl/trunk/bench/debounce_atlys_top_bit.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/debouncer_vhdl/trunk/bench/debounce_atlys_top_map.psr
29,9 → 29,9
* Optimizations *
=========================================================================
---- Statistics
Number of LUTs removed by SmartOpt Trimming | 105
Number of LUTs removed by SmartOpt Trimming | 97
 
Overall change in number of design objects | -105
Overall change in number of design objects | -97
 
 
---- Details
53,28 → 53,21
][82_9 | SmartOpt Trimming
][89_10 | SmartOpt Trimming
][96_11 | SmartOpt Trimming
][const_100_109 | SmartOpt Trimming
][const_101_110 | SmartOpt Trimming
][const_103_112 | SmartOpt Trimming
][const_104_113 | SmartOpt Trimming
][const_106_115 | SmartOpt Trimming
][const_107_116 | SmartOpt Trimming
][const_109_118 | SmartOpt Trimming
][const_100_108 | SmartOpt Trimming
][const_102_110 | SmartOpt Trimming
][const_103_111 | SmartOpt Trimming
][const_105_113 | SmartOpt Trimming
][const_106_114 | SmartOpt Trimming
][const_108_116 | SmartOpt Trimming
][const_109_117 | SmartOpt Trimming
][const_10_15 | SmartOpt Trimming
][const_110_119 | SmartOpt Trimming
][const_112_121 | SmartOpt Trimming
][const_113_122 | SmartOpt Trimming
][const_115_124 | SmartOpt Trimming
][const_116_125 | SmartOpt Trimming
][const_118_127 | SmartOpt Trimming
][const_119_128 | SmartOpt Trimming
][const_111_119 | SmartOpt Trimming
][const_112_120 | SmartOpt Trimming
][const_114_122 | SmartOpt Trimming
][const_115_123 | SmartOpt Trimming
][const_117_125 | SmartOpt Trimming
][const_118_126 | SmartOpt Trimming
][const_11_16 | SmartOpt Trimming
][const_121_130 | SmartOpt Trimming
][const_122_131 | SmartOpt Trimming
][const_124_133 | SmartOpt Trimming
][const_125_134 | SmartOpt Trimming
][const_127_136 | SmartOpt Trimming
][const_128_137 | SmartOpt Trimming
][const_12_17 | SmartOpt Trimming
][const_13_18 | SmartOpt Trimming
][const_14_19 | SmartOpt Trimming
85,65 → 78,64
][const_19_24 | SmartOpt Trimming
][const_20_25 | SmartOpt Trimming
][const_21_26 | SmartOpt Trimming
][const_22_27 | SmartOpt Trimming
][const_23_28 | SmartOpt Trimming
][const_24_31 | SmartOpt Trimming
][const_25_32 | SmartOpt Trimming
][const_26_35 | SmartOpt Trimming
][const_27_36 | SmartOpt Trimming
][const_28_38 | SmartOpt Trimming
][const_29_39 | SmartOpt Trimming
][const_30_41 | SmartOpt Trimming
][const_31_42 | SmartOpt Trimming
][const_32_44 | SmartOpt Trimming
][const_33_45 | SmartOpt Trimming
][const_34_47 | SmartOpt Trimming
][const_35_48 | SmartOpt Trimming
][const_22_29 | SmartOpt Trimming
][const_23_30 | SmartOpt Trimming
][const_24_33 | SmartOpt Trimming
][const_25_34 | SmartOpt Trimming
][const_26_36 | SmartOpt Trimming
][const_27_37 | SmartOpt Trimming
][const_28_39 | SmartOpt Trimming
][const_29_40 | SmartOpt Trimming
][const_30_42 | SmartOpt Trimming
][const_31_43 | SmartOpt Trimming
][const_32_45 | SmartOpt Trimming
][const_33_46 | SmartOpt Trimming
][const_34_48 | SmartOpt Trimming
][const_35_49 | SmartOpt Trimming
][const_36_50 | SmartOpt Trimming
][const_37_51 | SmartOpt Trimming
][const_38_53 | SmartOpt Trimming
][const_39_54 | SmartOpt Trimming
][const_40_55 | SmartOpt Trimming
][const_41_56 | SmartOpt Trimming
][const_43_57 | SmartOpt Trimming
][const_44_58 | SmartOpt Trimming
][const_46_59 | SmartOpt Trimming
][const_47_60 | SmartOpt Trimming
][const_49_61 | SmartOpt Trimming
][const_50_62 | SmartOpt Trimming
][const_52_63 | SmartOpt Trimming
][const_53_64 | SmartOpt Trimming
][const_55_65 | SmartOpt Trimming
][const_56_66 | SmartOpt Trimming
][const_58_67 | SmartOpt Trimming
][const_59_68 | SmartOpt Trimming
][const_61_69 | SmartOpt Trimming
][const_62_70 | SmartOpt Trimming
][const_64_75 | SmartOpt Trimming
][const_65_76 | SmartOpt Trimming
][const_67_77 | SmartOpt Trimming
][const_68_78 | SmartOpt Trimming
][const_70_79 | SmartOpt Trimming
][const_71_80 | SmartOpt Trimming
][const_73_81 | SmartOpt Trimming
][const_74_82 | SmartOpt Trimming
][const_76_83 | SmartOpt Trimming
][const_77_84 | SmartOpt Trimming
][const_79_85 | SmartOpt Trimming
][const_80_86 | SmartOpt Trimming
][const_82_87 | SmartOpt Trimming
][const_83_88 | SmartOpt Trimming
][const_85_89 | SmartOpt Trimming
][const_86_90 | SmartOpt Trimming
][const_88_91 | SmartOpt Trimming
][const_89_92 | SmartOpt Trimming
][const_39_52 | SmartOpt Trimming
][const_40_53 | SmartOpt Trimming
][const_42_54 | SmartOpt Trimming
][const_43_55 | SmartOpt Trimming
][const_45_56 | SmartOpt Trimming
][const_46_57 | SmartOpt Trimming
][const_48_58 | SmartOpt Trimming
][const_49_59 | SmartOpt Trimming
][const_51_60 | SmartOpt Trimming
][const_52_61 | SmartOpt Trimming
][const_54_62 | SmartOpt Trimming
][const_55_63 | SmartOpt Trimming
][const_57_68 | SmartOpt Trimming
][const_58_69 | SmartOpt Trimming
][const_60_70 | SmartOpt Trimming
][const_61_71 | SmartOpt Trimming
][const_63_72 | SmartOpt Trimming
][const_64_73 | SmartOpt Trimming
][const_66_74 | SmartOpt Trimming
][const_67_75 | SmartOpt Trimming
][const_69_76 | SmartOpt Trimming
][const_70_77 | SmartOpt Trimming
][const_72_78 | SmartOpt Trimming
][const_73_79 | SmartOpt Trimming
][const_75_80 | SmartOpt Trimming
][const_76_81 | SmartOpt Trimming
][const_78_82 | SmartOpt Trimming
][const_79_83 | SmartOpt Trimming
][const_81_89 | SmartOpt Trimming
][const_82_90 | SmartOpt Trimming
][const_84_92 | SmartOpt Trimming
][const_85_93 | SmartOpt Trimming
][const_87_95 | SmartOpt Trimming
][const_88_96 | SmartOpt Trimming
][const_8_13 | SmartOpt Trimming
][const_91_100 | SmartOpt Trimming
][const_92_101 | SmartOpt Trimming
][const_94_103 | SmartOpt Trimming
][const_95_104 | SmartOpt Trimming
][const_97_106 | SmartOpt Trimming
][const_98_107 | SmartOpt Trimming
][const_90_98 | SmartOpt Trimming
][const_91_99 | SmartOpt Trimming
][const_93_101 | SmartOpt Trimming
][const_94_102 | SmartOpt Trimming
][const_96_104 | SmartOpt Trimming
][const_97_105 | SmartOpt Trimming
][const_99_107 | SmartOpt Trimming
][const_9_14 | SmartOpt Trimming
 
 
/debouncer_vhdl/trunk/bench/par_usage_statistics.html
1,26 → 1,26
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>83</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>212</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>212</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>179</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>76</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>180</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>180</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>151</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>5.9 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>23.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>10.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>7.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>8.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>20.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>7.3</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>9.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>2.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>7.8</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
27,6 → 27,6
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0075</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0041</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
/debouncer_vhdl/trunk/bench/debounce_vhdl_bench.gise
104,12 → 104,11
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1313032021" xil_pn:in_ck="-726592440621834462" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-3901394755573216894" xil_pn:start_ts="1313032016">
<transform xil_pn:end_ts="1313109035" xil_pn:in_ck="-726592440621834462" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-3901394755573216894" xil_pn:start_ts="1313109027">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="debounce_atlys_top.lso"/>
123,14 → 122,13
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1313030836" xil_pn:in_ck="-7617925053698354275" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3041675604745481488" xil_pn:start_ts="1313030836">
<transform xil_pn:end_ts="1313109084" xil_pn:in_ck="-7617925053698354275" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3041675604745481488" xil_pn:start_ts="1313109084">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1313032025" xil_pn:in_ck="1959554578214568806" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7550009954124855948" xil_pn:start_ts="1313032021">
<transform xil_pn:end_ts="1313109087" xil_pn:in_ck="1959554578214568806" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7550009954124855948" xil_pn:start_ts="1313109084">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="debounce_atlys_top.bld"/>
137,10 → 135,9
<outfile xil_pn:name="debounce_atlys_top.ngd"/>
<outfile xil_pn:name="debounce_atlys_top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1313032038" xil_pn:in_ck="1959554578214568807" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313032025">
<transform xil_pn:end_ts="1313109105" xil_pn:in_ck="1959554578214568807" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313109087">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
154,11 → 151,10
<outfile xil_pn:name="debounce_atlys_top_summary.xml"/>
<outfile xil_pn:name="debounce_atlys_top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1313032054" xil_pn:in_ck="-6999964895445881344" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313032038">
<transform xil_pn:end_ts="1313109122" xil_pn:in_ck="-6999964895445881344" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313109105">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="debounce_atlys_top.ncd"/>
<outfile xil_pn:name="debounce_atlys_top.pad"/>
170,10 → 166,9
<outfile xil_pn:name="debounce_atlys_top_pad.txt"/>
<outfile xil_pn:name="debounce_atlys_top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1313032067" xil_pn:in_ck="-1280993813019831418" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313032054">
<transform xil_pn:end_ts="1313109138" xil_pn:in_ck="-1280993813019831418" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313109122">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="debounce_atlys_top.bgn"/>
<outfile xil_pn:name="debounce_atlys_top.bit"/>
183,10 → 178,9
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1313032054" xil_pn:in_ck="1959554578214568675" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313032048">
<transform xil_pn:end_ts="1313109122" xil_pn:in_ck="1959554578214568675" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313109115">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="debounce_atlys_top.twr"/>
<outfile xil_pn:name="debounce_atlys_top.twx"/>
/debouncer_vhdl/trunk/bench/debounce_atlys_top_map.map
11,7 → 11,7
Target Package : csg324
Target Speed : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Aug 11 00:07:05 2011
Mapped Date : Thu Aug 11 21:31:29 2011
 
Running global optimization...
Mapping design into LUTs...
21,54 → 21,54
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 7 secs
Total REAL time at the beginning of Placer: 9 secs
Total CPU time at the beginning of Placer: 7 secs
 
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:74f3dbc5) REAL time: 8 secs
Phase 1.1 Initial Placement Analysis (Checksum:ed93dd56) REAL time: 10 secs
 
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:74f3dbc5) REAL time: 8 secs
Phase 2.7 Design Feasibility Check (Checksum:ed93dd56) REAL time: 10 secs
 
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:74f3dbc5) REAL time: 8 secs
Phase 3.31 Local Placement Optimization (Checksum:ed93dd56) REAL time: 10 secs
 
Phase 4.2 Initial Placement for Architecture Specific Features
 
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:d6fae235) REAL time: 10 secs
(Checksum:feb5d5d6) REAL time: 12 secs
 
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
Phase 5.36 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 12 secs
 
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:d6fae235) REAL time: 10 secs
Phase 6.30 Global Clock Region Assignment (Checksum:feb5d5d6) REAL time: 12 secs
 
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
Phase 7.3 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 12 secs
 
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:d6fae235) REAL time: 10 secs
Phase 8.5 Local Placement Optimization (Checksum:feb5d5d6) REAL time: 12 secs
 
Phase 9.8 Global Placement
...
..
Phase 9.8 Global Placement (Checksum:2b00d50b) REAL time: 10 secs
Phase 9.8 Global Placement (Checksum:6e34e131) REAL time: 12 secs
 
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:2b00d50b) REAL time: 10 secs
Phase 10.5 Local Placement Optimization (Checksum:6e34e131) REAL time: 12 secs
 
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs
Phase 11.18 Placement Optimization (Checksum:ddc79b4e) REAL time: 12 secs
 
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:1f5fecef) REAL time: 11 secs
Phase 12.5 Local Placement Optimization (Checksum:ddc79b4e) REAL time: 12 secs
 
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:1bfd6a39) REAL time: 11 secs
Phase 13.34 Placement Validation (Checksum:d90e05db) REAL time: 12 secs
 
Total REAL time to Placer completion: 11 secs
Total CPU time to Placer completion: 11 secs
Total REAL time to Placer completion: 12 secs
Total CPU time to Placer completion: 10 secs
Running post-placement packing...
Writing output files...
 
79,32 → 79,32
Number of errors: 0
Number of warnings: 0
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54,576 1%
Number used as Flip Flops: 46
Number of Slice Registers: 42 out of 54,576 1%
Number used as Flip Flops: 42
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 43 out of 27,288 1%
Number used as logic: 38 out of 27,288 1%
Number of Slice LUTs: 37 out of 27,288 1%
Number used as logic: 36 out of 27,288 1%
Number using O6 output only: 18
Number using O5 output only: 12
Number using O5 and O6: 8
Number using O5 output only: 11
Number using O5 and O6: 7
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 5
Number with same-slice register load: 4
Number used exclusively as route-thrus: 1
Number with same-slice register load: 0
Number with same-slice carry load: 1
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 17 out of 6,822 1%
Number of LUT Flip Flop pairs used: 57
Number with an unused Flip Flop: 21 out of 57 36%
Number with an unused LUT: 14 out of 57 24%
Number of fully used LUT-FF pairs: 22 out of 57 38%
Number of occupied Slices: 19 out of 6,822 1%
Number of LUT Flip Flop pairs used: 56
Number with an unused Flip Flop: 20 out of 56 35%
Number with an unused LUT: 19 out of 56 33%
Number of fully used LUT-FF pairs: 17 out of 56 30%
Number of unique control sets: 3
Number of slice register sites lost
to control set restrictions: 2 out of 54,576 1%
to control set restrictions: 6 out of 54,576 1%
 
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
113,8 → 113,8
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 34 out of 218 15%
Number of LOCed IOBs: 34 out of 34 100%
Number of bonded IOBs: 31 out of 218 14%
Number of LOCed IOBs: 31 out of 31 100%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
141,10 → 141,10
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
 
Average Fanout of Non-Clock Nets: 2.57
Average Fanout of Non-Clock Nets: 2.37
 
Peak Memory Usage: 299 MB
Total REAL time to MAP completion: 11 secs
Peak Memory Usage: 295 MB
Total REAL time to MAP completion: 14 secs
Total CPU time to MAP completion (all processors): 11 secs
 
Mapping completed.
/debouncer_vhdl/trunk/bench/debounce_atlys_top.twr
36,14 → 36,13
|Max Setup to| Process |Max Hold to | Process | | Clock |
Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
------------+------------+------------+------------+------------+------------------+--------+
sw_i<0> | 5.038(R)| SLOW | -2.761(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<1> | 5.576(R)| SLOW | -3.098(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<2> | 5.317(R)| SLOW | -2.953(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<3> | 4.491(R)| SLOW | -2.388(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<4> | 2.742(R)| SLOW | -1.466(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<5> | 4.819(R)| SLOW | -2.715(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<6> | 4.336(R)| SLOW | -2.454(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<7> | 5.893(R)| SLOW | -3.333(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<0> | 4.897(R)| SLOW | -2.640(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<1> | 5.976(R)| SLOW | -3.369(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<2> | 6.081(R)| SLOW | -3.407(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<3> | 5.313(R)| SLOW | -2.891(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<4> | 2.578(R)| SLOW | -1.340(R)| SLOW |gclk_i_BUFGP | 0.000|
sw_i<5> | 3.922(R)| SLOW | -2.152(R)| FAST |gclk_i_BUFGP | 0.000|
sw_i<6> | 3.293(R)| SLOW | -1.813(R)| FAST |gclk_i_BUFGP | 0.000|
------------+------------+------------+------------+------------+------------------+--------+
 
Clock gclk_i to Pad
51,23 → 50,21
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
dbg_o<8> | 11.232(R)| SLOW | 4.814(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<9> | 11.480(R)| SLOW | 4.979(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<10> | 11.254(R)| SLOW | 4.861(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<11> | 11.049(R)| SLOW | 4.732(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<12> | 11.559(R)| SLOW | 5.013(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<13> | 11.939(R)| SLOW | 5.209(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<14> | 12.377(R)| SLOW | 5.519(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<15> | 12.060(R)| SLOW | 5.330(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<0> | 9.814(R)| SLOW | 4.065(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<1> | 9.656(R)| SLOW | 3.955(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<2> | 9.469(R)| SLOW | 3.865(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<3> | 9.929(R)| SLOW | 4.132(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<4> | 9.577(R)| SLOW | 3.889(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<5> | 17.272(R)| SLOW | 8.413(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<6> | 11.323(R)| SLOW | 4.861(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<7> | 10.605(R)| SLOW | 4.453(R)| FAST |gclk_i_BUFGP | 0.000|
strb_o | 13.397(R)| SLOW | 6.237(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<7> | 11.316(R)| SLOW | 4.892(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<8> | 11.472(R)| SLOW | 4.944(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<9> | 11.204(R)| SLOW | 4.794(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<10> | 11.504(R)| SLOW | 4.993(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<11> | 11.865(R)| SLOW | 5.220(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<12> | 12.635(R)| SLOW | 5.653(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<13> | 12.428(R)| SLOW | 5.522(R)| FAST |gclk_i_BUFGP | 0.000|
dbg_o<14> | 13.576(R)| SLOW | 6.221(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<0> | 9.204(R)| SLOW | 3.688(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<1> | 9.148(R)| SLOW | 3.672(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<2> | 9.367(R)| SLOW | 3.814(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<3> | 9.812(R)| SLOW | 4.033(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<4> | 10.245(R)| SLOW | 4.270(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<5> | 16.830(R)| SLOW | 8.118(R)| FAST |gclk_i_BUFGP | 0.000|
led_o<6> | 11.879(R)| SLOW | 5.161(R)| FAST |gclk_i_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
 
Clock to Setup on destination clock gclk_i
75,7 → 72,7
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i | 4.464| | | |
gclk_i | 4.423| | | |
---------------+---------+---------+---------+---------+
 
Pad to Pad
82,18 → 79,17
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
sw_i<0> |dbg_o<0> | 16.209|
sw_i<1> |dbg_o<1> | 16.941|
sw_i<2> |dbg_o<2> | 16.803|
sw_i<0> |dbg_o<0> | 15.462|
sw_i<1> |dbg_o<1> | 16.552|
sw_i<2> |dbg_o<2> | 16.755|
sw_i<3> |dbg_o<3> | 9.229|
sw_i<4> |dbg_o<4> | 7.980|
sw_i<5> |dbg_o<5> | 8.917|
sw_i<6> |dbg_o<6> | 9.026|
sw_i<7> |dbg_o<7> | 15.558|
sw_i<4> |dbg_o<4> | 7.978|
sw_i<5> |dbg_o<5> | 8.889|
sw_i<6> |dbg_o<6> | 9.058|
---------------+---------------+---------+
 
 
Analysis completed Thu Aug 11 00:07:33 2011
Analysis completed Thu Aug 11 21:32:01 2011
--------------------------------------------------------------------------------
 
Trace Settings:
100,7 → 96,7
-------------------------
Trace Settings
 
Peak Memory Usage: 178 MB
Peak Memory Usage: 175 MB
 
 
 
/debouncer_vhdl/trunk/bench/debounce_atlys_top.syr
118,6 → 118,7
Elaborating entity <debounce_atlys_top> (architecture <rtl>) from library <work>.
 
Elaborating entity <grp_debouncer> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\dropbox\Dropbox\VHDL_training\OpenCores\debouncer_vhdl\debouncer_vhdl\trunk\bench\debounce_atlys_top.vhd" Line 71: Net <dbg[15]> does not have a driver.
 
=========================================================================
* HDL Synthesis *
125,26 → 126,27
 
Synthesizing Unit <debounce_atlys_top>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd".
Found 8-bit register for signal <led_o>.
WARNING:Xst:2935 - Signal 'dbg<15>', unconnected in block 'debounce_atlys_top', is tied to its initial value (0).
Found 7-bit register for signal <led_o>.
Summary:
inferred 8 D-type flip-flop(s).
inferred 7 D-type flip-flop(s).
Unit <debounce_atlys_top> synthesized.
 
Synthesizing Unit <grp_debouncer>.
Related source file is "c:/dropbox/dropbox/vhdl_training/opencores/debouncer_vhdl/debouncer_vhdl/trunk/bench/grp_debouncer.vhd".
N = 8
N = 7
CNT_VAL = 5000
Found 8-bit register for signal <reg_A>.
Found 8-bit register for signal <reg_B>.
Found 7-bit register for signal <reg_A>.
Found 7-bit register for signal <reg_B>.
Found 1-bit register for signal <strb_reg>.
Found 8-bit register for signal <reg_out>.
Found 7-bit register for signal <reg_out>.
Found 13-bit register for signal <cnt_reg>.
Found 14-bit adder for signal <n0026> created at line 167.
Found 8-bit comparator not equal for signal <n0009> created at line 192
Found 8-bit comparator not equal for signal <n0011> created at line 194
Found 7-bit comparator not equal for signal <n0009> created at line 192
Found 7-bit comparator not equal for signal <n0011> created at line 194
Summary:
inferred 1 Adder/Subtractor(s).
inferred 38 D-type flip-flop(s).
inferred 35 D-type flip-flop(s).
inferred 2 Comparator(s).
Unit <grp_debouncer> synthesized.
 
157,9 → 159,9
# Registers : 6
1-bit register : 1
13-bit register : 1
8-bit register : 4
7-bit register : 4
# Comparators : 2
8-bit comparator not equal : 2
7-bit comparator not equal : 2
 
=========================================================================
 
178,10 → 180,10
Macro Statistics
# Counters : 1
13-bit up counter : 1
# Registers : 33
Flip-Flops : 33
# Registers : 29
Flip-Flops : 29
# Comparators : 2
8-bit comparator not equal : 2
7-bit comparator not equal : 2
 
=========================================================================
 
203,8 → 205,8
Final Register Report
 
Macro Statistics
# Registers : 46
Flip-Flops : 46
# Registers : 42
Flip-Flops : 42
 
=========================================================================
 
227,24 → 229,24
 
Primitive and Black Box Usage:
------------------------------
# BELS : 75
# BELS : 73
# GND : 1
# INV : 1
# LUT1 : 12
# LUT3 : 2
# LUT4 : 8
# LUT6 : 25
# LUT3 : 1
# LUT4 : 9
# LUT6 : 23
# MUXCY : 12
# VCC : 1
# XORCY : 13
# FlipFlops/Latches : 46
# FD : 30
# FDE : 16
# FlipFlops/Latches : 42
# FD : 28
# FDE : 14
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 33
# IBUF : 8
# OBUF : 25
# IO Buffers : 30
# IBUF : 7
# OBUF : 23
 
Device utilization summary:
---------------------------
253,20 → 255,20
 
 
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54576 0%
Number of Slice LUTs: 48 out of 27288 0%
Number used as Logic: 48 out of 27288 0%
Number of Slice Registers: 42 out of 54576 0%
Number of Slice LUTs: 46 out of 27288 0%
Number used as Logic: 46 out of 27288 0%
 
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 72
Number with an unused Flip Flop: 26 out of 72 36%
Number with an unused LUT: 24 out of 72 33%
Number of fully used LUT-FF pairs: 22 out of 72 30%
Number of LUT Flip Flop pairs used: 67
Number with an unused Flip Flop: 25 out of 67 37%
Number with an unused LUT: 21 out of 67 31%
Number of fully used LUT-FF pairs: 21 out of 67 31%
Number of unique control sets: 3
 
IO Utilization:
Number of IOs: 34
Number of bonded IOBs: 34 out of 218 15%
Number of IOs: 31
Number of bonded IOBs: 31 out of 218 14%
 
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 16 6%
292,7 → 294,7
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
gclk_i | BUFGP | 46 |
gclk_i | BUFGP | 42 |
-----------------------------------+------------------------+-------+
 
Asynchronous Control Signals Information:
303,9 → 305,9
---------------
Speed Grade: -2
 
Minimum period: 4.749ns (Maximum Frequency: 210.571MHz)
Minimum period: 4.717ns (Maximum Frequency: 211.999MHz)
Minimum input arrival time before clock: 2.127ns
Maximum output required time after clock: 4.412ns
Maximum output required time after clock: 4.380ns
Maximum combinational path delay: 4.965ns
 
Timing Details:
314,10 → 316,10
 
=========================================================================
Timing constraint: Default period analysis for Clock 'gclk_i'
Clock period: 4.749ns (frequency: 210.571MHz)
Total number of paths / destination ports: 761 / 54
Clock period: 4.717ns (frequency: 211.999MHz)
Total number of paths / destination ports: 713 / 49
-------------------------------------------------------------------------
Delay: 4.749ns (Levels of Logic = 3)
Delay: 4.717ns (Levels of Logic = 3)
Source: Inst_sw_debouncer/cnt_reg_0 (FF)
Destination: Inst_sw_debouncer/strb_reg (FF)
Source Clock: gclk_i rising
328,29 → 330,29
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 2 0.525 1.181 Inst_sw_debouncer/cnt_reg_0 (Inst_sw_debouncer/cnt_reg_0)
LUT6:I0->O 9 0.254 1.084 Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
LUT6:I0->O 8 0.254 1.052 Inst_sw_debouncer/dat_strb<12>1 (Inst_sw_debouncer/dat_strb<12>)
LUT3:I1->O 14 0.250 1.127 Inst_sw_debouncer/dat_strb<12>3 (Inst_sw_debouncer/dat_strb)
LUT6:I5->O 1 0.254 0.000 Inst_sw_debouncer/strb_next7 (Inst_sw_debouncer/strb_next)
LUT6:I5->O 1 0.254 0.000 Inst_sw_debouncer/strb_next6 (Inst_sw_debouncer/strb_next)
FD:D 0.074 Inst_sw_debouncer/strb_reg
----------------------------------------
Total 4.749ns (1.357ns logic, 3.392ns route)
(28.6% logic, 71.4% route)
Total 4.717ns (1.357ns logic, 3.360ns route)
(28.8% logic, 71.2% route)
 
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'gclk_i'
Total number of paths / destination ports: 8 / 8
Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Offset: 2.127ns (Levels of Logic = 1)
Source: sw_i<7> (PAD)
Destination: Inst_sw_debouncer/reg_A_7 (FF)
Source: sw_i<6> (PAD)
Destination: Inst_sw_debouncer/reg_A_6 (FF)
Destination Clock: gclk_i rising
 
Data Path: sw_i<7> to Inst_sw_debouncer/reg_A_7
Data Path: sw_i<6> to Inst_sw_debouncer/reg_A_6
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.328 0.725 sw_i_7_IBUF (dbg_o_7_OBUF)
FD:D 0.074 Inst_sw_debouncer/reg_A_7
IBUF:I->O 2 1.328 0.725 sw_i_6_IBUF (dbg_o_6_OBUF)
FD:D 0.074 Inst_sw_debouncer/reg_A_6
----------------------------------------
Total 2.127ns (1.402ns logic, 0.725ns route)
(65.9% logic, 34.1% route)
357,37 → 359,37
 
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'gclk_i'
Total number of paths / destination ports: 17 / 17
Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Offset: 4.412ns (Levels of Logic = 1)
Offset: 4.380ns (Levels of Logic = 1)
Source: Inst_sw_debouncer/strb_reg (FF)
Destination: strb_o (PAD)
Destination: dbg_o<14> (PAD)
Source Clock: gclk_i rising
 
Data Path: Inst_sw_debouncer/strb_reg to strb_o
Data Path: Inst_sw_debouncer/strb_reg to dbg_o<14>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 9 0.525 0.975 Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
OBUF:I->O 2.912 strb_o_OBUF (strb_o)
FD:C->Q 8 0.525 0.943 Inst_sw_debouncer/strb_reg (Inst_sw_debouncer/strb_reg)
OBUF:I->O 2.912 dbg_o_14_OBUF (dbg_o<14>)
----------------------------------------
Total 4.412ns (3.437ns logic, 0.975ns route)
(77.9% logic, 22.1% route)
Total 4.380ns (3.437ns logic, 0.943ns route)
(78.5% logic, 21.5% route)
 
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 8 / 8
Total number of paths / destination ports: 7 / 7
-------------------------------------------------------------------------
Delay: 4.965ns (Levels of Logic = 2)
Source: sw_i<7> (PAD)
Destination: dbg_o<7> (PAD)
Source: sw_i<6> (PAD)
Destination: dbg_o<6> (PAD)
 
Data Path: sw_i<7> to dbg_o<7>
Data Path: sw_i<6> to dbg_o<6>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.328 0.725 sw_i_7_IBUF (dbg_o_7_OBUF)
OBUF:I->O 2.912 dbg_o_7_OBUF (dbg_o<7>)
IBUF:I->O 2 1.328 0.725 sw_i_6_IBUF (dbg_o_6_OBUF)
OBUF:I->O 2.912 dbg_o_6_OBUF (dbg_o<6>)
----------------------------------------
Total 4.965ns (4.240ns logic, 0.725ns route)
(85.4% logic, 14.6% route)
402,7 → 404,7
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
gclk_i | 4.749| | | |
gclk_i | 4.717| | | |
---------------+---------+---------+---------+---------+
 
=========================================================================
409,13 → 411,13
 
 
Total REAL time to Xst completion: 4.00 secs
Total CPU time to Xst completion: 3.87 secs
Total CPU time to Xst completion: 4.57 secs
-->
 
Total memory usage is 188424 kilobytes
Total memory usage is 185320 kilobytes
 
Number of errors : 0 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of warnings : 2 ( 0 filtered)
Number of infos : 0 ( 0 filtered)
 
/debouncer_vhdl/trunk/bench/debounce_atlys_top.vhd
30,6 → 30,7
-- 2011/07/29 v1.12.0105 [JD] spi_master.vhd and spi_slave_vhd changed to fix CPHA='1' bug.
-- 2011/08/02 v1.13.0110 [JD] testbed for continuous transfer in FPGA hardware.
-- 2011/08/10 v1.01.0025 [JD] changed to test the grp_debouncer.vhd module alone.
-- 2011/08/11 v1.01.0026 [JD] reduced switch inputs to 7, to save digital pins to the strobe signal.
--
--
----------------------------------------------------------------------------------
41,11 → 42,10
Port (
gclk_i : in std_logic := 'X'; -- board clock input 100MHz
--- input slide switches ---
sw_i : in std_logic_vector (7 downto 0); -- 8 input slide switches
sw_i : in std_logic_vector (6 downto 0); -- 7 input slide switches
--- output LEDs ----
led_o : out std_logic_vector (7 downto 0); -- output leds
led_o : out std_logic_vector (6 downto 0); -- 7 output leds
--- debug outputs ---
strb_o : out std_logic; -- core strobe output
dbg_o : out std_logic_vector (15 downto 0) -- 16 generic debug pins
);
end debounce_atlys_top;
56,7 → 56,7
-- Constants
--=============================================================================================
-- debounce generics
constant N : integer := 8; -- 8 bits (8 switch inputs)
constant N : integer := 7; -- 7 bits (7 switch inputs)
constant CNT_VAL : integer := 5000; -- debounce period = 1000 * 10 ns (50 us)
--=============================================================================================
63,11 → 63,11
-- Signals for internal operation
--=============================================================================================
--- switch debouncer signals ---
signal sw_data : std_logic_vector (7 downto 0) := (others => '0'); -- debounced switch data
signal sw_reg : std_logic_vector (7 downto 0) := (others => '0'); -- registered switch data
signal sw_data : std_logic_vector (6 downto 0) := (others => '0'); -- debounced switch data
signal sw_reg : std_logic_vector (6 downto 0) := (others => '0'); -- registered switch data
signal sw_new : std_logic := '0';
-- debug output signals
signal leds_reg : std_logic_vector (7 downto 0) := (others => '0');
signal leds_reg : std_logic_vector (6 downto 0) := (others => '0');
signal dbg : std_logic_vector (15 downto 0) := (others => '0');
begin
 
105,8 → 105,9
leds_reg_proc: leds_reg <= sw_reg; -- leds register is a copy of the updated switch register
 
-- update debug register
dbg_lo_proc: dbg(7 downto 0) <= sw_i; -- lower debug port has direct switch connections
dbg_hi_proc: dbg(15 downto 8) <= sw_data; -- upper debug port has debounced switch data
dbg_in_proc: dbg(6 downto 0) <= sw_i; -- lower debug port has direct switch connections
dbg_out_proc: dbg(13 downto 7) <= sw_data; -- upper debug port has debounced switch data
dbg_strb_proc: dbg(14) <= sw_new; -- monitor new data strobe
 
--=============================================================================================
119,7 → 120,6
-- DEBUG LOGIC PROCESSES
--=============================================================================================
-- connect the debug vector outputs
strb_o_proc: strb_o <= sw_new; -- connect strobe debug out
dbg_o_proc: dbg_o <= dbg; -- drive the logic analyzer port
end rtl;
/debouncer_vhdl/trunk/bench/debounce_atlys_top_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/11/2011 - 00:07:47)</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/11/2011 - 21:32:18)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>debounce_vhdl_bench.xise</TD>
25,7 → 25,7
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/*.xmsgs?&DataKey=Warning'>3 Warnings (3 new)</A></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
60,13 → 60,13
<TD ALIGN=LEFT><B>Slice Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
<TD ALIGN=RIGHT>46</TD>
<TD ALIGN=RIGHT>42</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>46</TD>
<TD ALIGN=RIGHT>42</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
90,13 → 90,13
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
<TD ALIGN=RIGHT>43</TD>
<TD ALIGN=RIGHT>37</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>38</TD>
<TD ALIGN=RIGHT>36</TD>
<TD ALIGN=RIGHT>27,288</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
108,13 → 108,13
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 output only</TD>
<TD ALIGN=RIGHT>12</TD>
<TD ALIGN=RIGHT>11</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number using O5 and O6</TD>
<TD ALIGN=RIGHT>8</TD>
<TD ALIGN=RIGHT>7</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
132,13 → 132,13
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used exclusively as route-thrus</TD>
<TD ALIGN=RIGHT>5</TD>
<TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Number with same-slice register load</TD>
<TD ALIGN=RIGHT>4</TD>
<TD ALIGN=RIGHT>0</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
156,33 → 156,33
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>19</TD>
<TD ALIGN=RIGHT>6,822</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of LUT Flip Flop pairs used</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>56</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused Flip Flop</TD>
<TD ALIGN=RIGHT>21</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>36%</TD>
<TD ALIGN=RIGHT>20</TD>
<TD ALIGN=RIGHT>56</TD>
<TD ALIGN=RIGHT>35%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number with an unused LUT</TD>
<TD ALIGN=RIGHT>14</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>24%</TD>
<TD ALIGN=RIGHT>19</TD>
<TD ALIGN=RIGHT>56</TD>
<TD ALIGN=RIGHT>33%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of fully used LUT-FF pairs</TD>
<TD ALIGN=RIGHT>22</TD>
<TD ALIGN=RIGHT>57</TD>
<TD ALIGN=RIGHT>38%</TD>
<TD ALIGN=RIGHT>17</TD>
<TD ALIGN=RIGHT>56</TD>
<TD ALIGN=RIGHT>30%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of unique control sets</TD>
192,20 → 192,20
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of slice register sites lost<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;to control set restrictions</TD>
<TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>6</TD>
<TD ALIGN=RIGHT>54,576</TD>
<TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>218</TD>
<TD ALIGN=RIGHT>15%</TD>
<TD ALIGN=RIGHT>14%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of LOCed IOBs</TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>34</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>31</TD>
<TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
348,7 → 348,7
<TD COLSPAN='2'>&nbsp;</TD>
</TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>2.57</TD>
<TD ALIGN=RIGHT>2.37</TD>
<TD>&nbsp;</TD>
<TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD>
385,22 → 385,22
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:00 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:03 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:17 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:27 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:30:34 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:31:26 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:31:44 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (9 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:31:54 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:33 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Aug 11 00:07:43 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:32:01 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Aug 11 21:32:12 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 00:07:17 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 00:07:43 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 00:07:47 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Thu Aug 11 21:31:43 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Aug 11 21:32:12 2011</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Aug 11 21:32:18 2011</TD></TR>
</TABLE>
 
 
<br><center><b>Date Generated:</b> 08/11/2011 - 00:09:45</center>
<br><center><b>Date Generated:</b> 08/11/2011 - 21:32:18</center>
</BODY></HTML>
/debouncer_vhdl/trunk/bench/debounce_atlys_top.par
1,7 → 1,7
Release 13.1 par O.40d (nt)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
 
DEVELOP-W7:: Thu Aug 11 00:07:18 2011
DEVELOP-W7:: Thu Aug 11 21:31:46 2011
 
par -w -intstyle ise -ol high -xe n -mt 4 debounce_atlys_top_map.ncd
debounce_atlys_top.ncd debounce_atlys_top.pcf
27,29 → 27,29
Device Utilization Summary:
 
Slice Logic Utilization:
Number of Slice Registers: 46 out of 54,576 1%
Number used as Flip Flops: 46
Number of Slice Registers: 42 out of 54,576 1%
Number used as Flip Flops: 42
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 43 out of 27,288 1%
Number used as logic: 38 out of 27,288 1%
Number of Slice LUTs: 37 out of 27,288 1%
Number used as logic: 36 out of 27,288 1%
Number using O6 output only: 18
Number using O5 output only: 12
Number using O5 and O6: 8
Number using O5 output only: 11
Number using O5 and O6: 7
Number used as ROM: 0
Number used as Memory: 0 out of 6,408 0%
Number used exclusively as route-thrus: 5
Number with same-slice register load: 4
Number used exclusively as route-thrus: 1
Number with same-slice register load: 0
Number with same-slice carry load: 1
Number with other load: 0
 
Slice Logic Distribution:
Number of occupied Slices: 17 out of 6,822 1%
Number of LUT Flip Flop pairs used: 57
Number with an unused Flip Flop: 21 out of 57 36%
Number with an unused LUT: 14 out of 57 24%
Number of fully used LUT-FF pairs: 22 out of 57 38%
Number of occupied Slices: 19 out of 6,822 1%
Number of LUT Flip Flop pairs used: 56
Number with an unused Flip Flop: 20 out of 56 35%
Number with an unused LUT: 19 out of 56 33%
Number of fully used LUT-FF pairs: 17 out of 56 30%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
 
60,8 → 60,8
over-mapped for a non-slice resource or if Placement fails.
 
IO Utilization:
Number of bonded IOBs: 34 out of 218 15%
Number of LOCed IOBs: 34 out of 34 100%
Number of bonded IOBs: 31 out of 218 14%
Number of LOCed IOBs: 31 out of 31 100%
 
Specific Feature Utilization:
Number of RAMB16BWERs: 0 out of 116 0%
100,13 → 100,13
Starting Router
 
 
Phase 1 : 231 unrouted; REAL time: 5 secs
Phase 1 : 199 unrouted; REAL time: 5 secs
 
Phase 2 : 199 unrouted; REAL time: 5 secs
Phase 2 : 168 unrouted; REAL time: 5 secs
 
Phase 3 : 51 unrouted; REAL time: 6 secs
Phase 3 : 46 unrouted; REAL time: 6 secs
 
Phase 4 : 51 unrouted; (Par is working to improve performance) REAL time: 7 secs
Phase 4 : 46 unrouted; (Par is working to improve performance) REAL time: 7 secs
 
Updating file: debounce_atlys_top.ncd with current fully routed design.
 
142,8 → 142,8
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net gcl | SETUP | N/A| 4.464ns| N/A| 0
k_i_BUFGP | HOLD | 0.388ns| | 0| 0
Autotimespec constraint for clock net gcl | SETUP | N/A| 4.423ns| N/A| 0
k_i_BUFGP | HOLD | 0.424ns| | 0| 0
----------------------------------------------------------------------------------------------------------
 
 
162,7 → 162,7
Total REAL time to PAR completion: 8 secs
Total CPU time to PAR completion: 8 secs
 
Peak Memory Usage: 262 MB
Peak Memory Usage: 259 MB
 
Placer: Placement generated during map.
Routing: Completed - No errors found.
/debouncer_vhdl/trunk/bench/scope_photos.zip Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/debouncer_vhdl/trunk/bench/scope_photos.zip
debouncer_vhdl/trunk/bench/scope_photos.zip Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: debouncer_vhdl/trunk/bench/debounce_atlys_top_map.mrp =================================================================== --- debouncer_vhdl/trunk/bench/debounce_atlys_top_map.mrp (revision 6) +++ debouncer_vhdl/trunk/bench/debounce_atlys_top_map.mrp (revision 7) @@ -11,7 +11,7 @@ Target Package : csg324 Target Speed : -2 Mapper Version : spartan6 -- $Revision: 1.55 $ -Mapped Date : Thu Aug 11 00:07:05 2011 +Mapped Date : Thu Aug 11 21:31:29 2011 Design Summary -------------- @@ -18,32 +18,32 @@ Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: - Number of Slice Registers: 46 out of 54,576 1% - Number used as Flip Flops: 46 + Number of Slice Registers: 42 out of 54,576 1% + Number used as Flip Flops: 42 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 - Number of Slice LUTs: 43 out of 27,288 1% - Number used as logic: 38 out of 27,288 1% + Number of Slice LUTs: 37 out of 27,288 1% + Number used as logic: 36 out of 27,288 1% Number using O6 output only: 18 - Number using O5 output only: 12 - Number using O5 and O6: 8 + Number using O5 output only: 11 + Number using O5 and O6: 7 Number used as ROM: 0 Number used as Memory: 0 out of 6,408 0% - Number used exclusively as route-thrus: 5 - Number with same-slice register load: 4 + Number used exclusively as route-thrus: 1 + Number with same-slice register load: 0 Number with same-slice carry load: 1 Number with other load: 0 Slice Logic Distribution: - Number of occupied Slices: 17 out of 6,822 1% - Number of LUT Flip Flop pairs used: 57 - Number with an unused Flip Flop: 21 out of 57 36% - Number with an unused LUT: 14 out of 57 24% - Number of fully used LUT-FF pairs: 22 out of 57 38% + Number of occupied Slices: 19 out of 6,822 1% + Number of LUT Flip Flop pairs used: 56 + Number with an unused Flip Flop: 20 out of 56 35% + Number with an unused LUT: 19 out of 56 33% + Number of fully used LUT-FF pairs: 17 out of 56 30% Number of unique control sets: 3 Number of slice register sites lost - to control set restrictions: 2 out of 54,576 1% + to control set restrictions: 6 out of 54,576 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of @@ -52,8 +52,8 @@ over-mapped for a non-slice resource or if Placement fails. IO Utilization: - Number of bonded IOBs: 34 out of 218 15% - Number of LOCed IOBs: 34 out of 34 100% + Number of bonded IOBs: 31 out of 218 14% + Number of LOCed IOBs: 31 out of 31 100% Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 116 0% @@ -80,10 +80,10 @@ Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% -Average Fanout of Non-Clock Nets: 2.57 +Average Fanout of Non-Clock Nets: 2.37 -Peak Memory Usage: 299 MB -Total REAL time to MAP completion: 11 secs +Peak Memory Usage: 295 MB +Total REAL time to MAP completion: 14 secs Total CPU time to MAP completion (all processors): 11 secs Table of Contents @@ -203,8 +203,6 @@ | led_o<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | led_o<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | led_o<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| led_o<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | -| strb_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | sw_i<0> | IOB | INPUT | LVCMOS25 | | | | | | | | sw_i<1> | IOB | INPUT | LVCMOS25 | | | | | | | | sw_i<2> | IOB | INPUT | LVCMOS25 | | | | | | | @@ -212,7 +210,6 @@ | sw_i<4> | IOB | INPUT | LVCMOS25 | | | | | | | | sw_i<5> | IOB | INPUT | LVCMOS25 | | | | | | | | sw_i<6> | IOB | INPUT | LVCMOS25 | | | | | | | -| sw_i<7> | IOB | INPUT | LVCMOS25 | | | | | | | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs @@ -259,9 +256,9 @@ +-----------------------------------------------------------------------------------------------------------+ | Clock Signal | Reset Signal | Set Signal | Enable Signal | Slice Load Count | Bel Load Count | +-----------------------------------------------------------------------------------------------------------+ -| gclk_i_BUFGP | | | | 7 | 30 | -| gclk_i_BUFGP | | | Inst_sw_debouncer/strb_reg | 2 | 8 | -| gclk_i_BUFGP | | | lut119_33 | 3 | 8 | +| gclk_i_BUFGP | | | | 8 | 28 | +| gclk_i_BUFGP | | | Inst_sw_debouncer/strb_reg | 2 | 7 | +| gclk_i_BUFGP | | | lut107_31 | 2 | 7 | +-----------------------------------------------------------------------------------------------------------+ Section 13 - Utilization by Hierarchy @@ -269,8 +266,8 @@ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48A1 | BUFG | BUFIO | BUFR | DCM | PLL_ADV | Full Hierarchical Name | +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -| debounce_atlys_top/ | | 12/26 | 8/46 | 26/27 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top | -| +Inst_sw_debouncer | | 14/14 | 38/38 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top/Inst_sw_debouncer | +| debounce_atlys_top/ | | 14/28 | 7/42 | 24/25 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top | +| +Inst_sw_debouncer | | 14/14 | 35/35 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | debounce_atlys_top/Inst_sw_debouncer | +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ * Slices can be packed with basic elements from multiple hierarchies.
/debouncer_vhdl/trunk/bench/debounce_atlys.ucf
47,7 → 47,7
NET "led_o<4>" LOC = "M13"; # Bank = 1, Pin name = IO_L61N, Sch name = LD4
NET "led_o<5>" LOC = "D4"; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
NET "led_o<6>" LOC = "P16"; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
NET "led_o<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
# NET "led_o<7>" LOC = "N12"; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
# onBoard PUSH BUTTONS
# NET "btn_i<0>" LOC = "T15"; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
65,7 → 65,7
NET "sw_i<4>" LOC = "P12"; # Bank = 2, Pin name = IO_L13N_D10, Sch name = SW4
NET "sw_i<5>" LOC = "R5"; # Bank = 2, Pin name = IO_L48P_D7, Sch name = SW5
NET "sw_i<6>" LOC = "T5"; # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2, Sch name = SW6
NET "sw_i<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
# NET "sw_i<7>" LOC = "E4"; # Bank = 3, Pin name = IO_L54P_M3RESET, Sch name = SW7
 
# TEMAC Ethernet MAC
# NET "phyrst" LOC = "G13"; # Bank = 1, Pin name = IO_L32N_A16_M1A9, Sch name = E-RESET
206,7 → 206,7
# NET "AUDRST" LOC = "T17"; # Bank = 1, Pin name = IO_L51P_M1DQ12, Sch name = AUD-RESET
# PMOD Connector
NET "strb_o" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_N
# NET "m_state_o<0>" LOC = "T3"; # Bank = 2, Pin name = IO_L62N_D6, PMOD JB<1>, Sch name = JA-D0_N
# NET "m_state_o<1>" LOC = "R3"; # Bank = 2, Pin name = IO_L62P_D5, PMOD JB<2>, Sch name = JA-D0_P
# NET "m_state_o<2>" LOC = "P6"; # Bank = 2, Pin name = IO_L64N_D9, PMOD JB<3>, Sch name = JA-D2_N
# NET "m_state_o<3>" LOC = "N5"; # Bank = 2, Pin name = IO_L64P_D8, PMOD JB<4>, Sch name = JA-D2_P

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