URL
https://opencores.org/ocsvn/distributed_intelligence/distributed_intelligence/trunk
Subversion Repositories distributed_intelligence
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- This comparison shows the changes necessary to convert path
/
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/distributed_intelligence/trunk/SRC/bus_access_x16.vhd
28,24 → 28,21
--use UNISIM.VComponents.all; |
|
entity bus_access_x16 is |
Port ( clk : in STD_LOGIC; |
en : in STD_LOGIC; |
Port ( en : in STD_LOGIC; |
dataRead : in STD_LOGIC_VECTOR (15 downto 0); |
dataWrite : out STD_LOGIC_VECTOR (15 downto 0)); |
end bus_access_x16; |
|
architecture Behavioral of bus_access_x16 is |
|
begin |
process(clk, en, dataRead) |
begin |
|
process(en, dataRead) |
begin |
if clk'event and clk = '1' then |
if en = '1' then |
dataWrite <= dataRead; |
else |
dataWrite <= (others => 'Z'); |
end if; |
end if; |
end process; |
end Behavioral; |
|
/distributed_intelligence/trunk/SRC/bus_register_x16.vhd
0,0 → 1,65
---------------------------------------------------------------------------------- |
-- Company: |
-- Engineer: |
-- |
-- Create Date: 21:30:09 11/08/2009 |
-- Design Name: |
-- Module Name: bus_register_x16 - Behavioral |
-- Project Name: |
-- Target Devices: |
-- Tool versions: |
-- Description: |
-- |
-- Dependencies: |
-- |
-- Revision: |
-- Revision 0.01 - File Created |
-- Additional Comments: |
-- |
---------------------------------------------------------------------------------- |
library IEEE; |
use IEEE.STD_LOGIC_1164.ALL; |
use IEEE.STD_LOGIC_ARITH.ALL; |
use IEEE.STD_LOGIC_UNSIGNED.ALL; |
|
---- Uncomment the following library declaration if instantiating |
---- any Xilinx primitives in this code. |
--library UNISIM; |
--use UNISIM.VComponents.all; |
|
entity bus_register_x16 is |
Port ( clk : in STD_LOGIC; |
reset : in STD_LOGIC; |
re : in STD_LOGIC; |
we : in STD_LOGIC; |
dataIn : in STD_LOGIC_VECTOR (15 downto 0); |
dataOut : out STD_LOGIC_VECTOR (15 downto 0)); |
end bus_register_x16; |
|
architecture Behavioral of bus_register_x16 is |
signal data: std_logic_vector(15 downto 0); |
|
component bus_access_x16 |
Port ( en : in STD_LOGIC; |
dataRead : in STD_LOGIC_VECTOR (15 downto 0); |
dataWrite : out STD_LOGIC_VECTOR (15 downto 0)); |
end component; |
begin |
|
ba: bus_access_x16 |
port map( en => we, |
dataRead=>data, |
dataWrite=>dataOut); |
|
|
readData: process(clk) is |
begin |
if clk'event and clk = '1' then |
if re = '1' then |
data <= dataIn; |
end if; |
end if; |
end process; |
|
end Behavioral; |
|
/distributed_intelligence/trunk/SRC/mini_uP_x16.vhd
104,8 → 104,7
end component; |
|
component bus_access_x16 |
port ( clk: in std_logic; |
en : in std_logic; |
port ( en : in std_logic; |
dataWrite: out std_logic_vector(15 downto 0); |
dataRead : in std_logic_vector(15 downto 0)); |
end component; |
145,14 → 144,12
|
-- The watchdog and its access to the main databus |
watchdog_re: bus_access_x16 |
port map ( clk => clk, |
en => watchdog_control(1), |
port map ( en => watchdog_control(1), |
dataRead => mainDataBus, |
dataWrite => watchdog_rst_value); |
|
watchdog_we: bus_access_x16 |
port map ( clk => clk, |
en => watchdog_control(0), |
port map ( en => watchdog_control(0), |
dataRead => watchdog_left, |
dataWrite => mainDataBus); |
|
205,7 → 202,7
dataport=> mainDataBus); |
|
-- The ALU |
the_alu : ALU |
arith_logic_unit : ALU |
port map( data1 => dataBus1, |
data2 => dataBus2, |
dataA => accumulator, |