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URL https://opencores.org/ocsvn/double_fpu/double_fpu/trunk

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/trunk/pipeline/Readme_pipeline.txt
0,0 → 1,110
The verilog files, fpu_addsub.v and fpu_mul.v, are pipelined versions of
floating point operators. Rounding is not supported by these operators, and
denormalized numbers are treated as 0. If infinity or NaN is on either of the inputs,
then infinity will be the output. Both operators, addsub and mul, have a latency
of 18 clock cycles, and then an output is available on each clock cycle after the latency.
 
For addition and subtraction, fpu_addsub.v was synthesized with an estimated
frequency of 276 MHz for a Virtex5 device. The synthesis results are below.
The file, fpu_addsub_TB.v, is the testbench used to simulate fpu_addsub.v.
 
For multiplication, fpu_mul.v was synthesized with an estimated
frequency of 426 MHz for a Virtex5 device. The synthesis results are below.
The file, fpu_mul_TB.v, is the testbench used to simulate fpu_mul.v.
 
Please email me any questions.
 
David Lundgren
davidklun@gmail.com
 
addsub synthesis results:
 
---------------------------------------
Resource Usage Report for fpu
 
Mapping to part: xc5vsx95tff1136-2
Cell usage:
FDE 16 uses
FDR 6 uses
FDRE 2350 uses
GND 1 use
MUXCY 7 uses
MUXCY_L 183 uses
VCC 1 use
XORCY 130 uses
XORCY_L 4 uses
LUT1 14 uses
LUT2 386 uses
LUT3 448 uses
LUT4 133 uses
LUT5 103 uses
LUT6 496 uses
 
I/O ports: 197
I/O primitives: 196
IBUF 131 uses
OBUF 65 uses
 
BUFGP 1 use
 
SRL primitives:
SRL16E 16 uses
 
I/O Register bits: 0
Register bits not including I/Os: 2372 (4%)
 
Global Clock Buffers: 1 of 32 (3%)
 
Total load per clock:
fpu|clk: 2388
 
Mapping Summary:
Total LUTs: 1596 (2%)
 
------------------------------
 
multiply synthesis results:
 
---------------------------------------
Resource Usage Report for fpu_mul
 
Mapping to part: xc5vsx95tff1136-2
Cell usage:
DSP48E 9 uses
FDE 80 uses
FDRE 1221 uses
FDRSE 11 uses
GND 1 use
MUXCY 4 uses
MUXCY_L 82 uses
VCC 1 use
XORCY 75 uses
XORCY_L 3 uses
LUT1 25 uses
LUT2 203 uses
LUT3 57 uses
LUT4 30 uses
LUT5 7 uses
LUT6 14 uses
 
I/O ports: 196
I/O primitives: 195
IBUF 130 uses
OBUF 65 uses
 
BUFGP 1 use
 
SRL primitives:
SRLC32E 1 use
SRL16E 27 uses
 
I/O Register bits: 0
Register bits not including I/Os: 1312 (2%)
 
Global Clock Buffers: 1 of 32 (3%)
 
Total load per clock:
fpu_mul|clk: 1349
 
Mapping Summary:
Total LUTs: 364 (0%)
/trunk/pipeline/fpu_addsub.v
0,0 → 1,305
/////////////////////////////////////////////////////////////////////
//// ////
//// FPU ////
//// Floating Point Unit (Double precision) ////
//// ////
//// Author: David Lundgren ////
//// davidklun@gmail.com ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// davidklun@gmail.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
// fpu_op, add = 0, subtract = 1
 
`timescale 1ns / 100ps
 
module fpu( clk, rst, enable, fpu_op, opa, opb, out, ready );
input clk;
input rst;
input enable;
input fpu_op;
input [63:0] opa, opb;
output [63:0] out;
output ready;
 
 
reg [63:0] outfp, outfp_2, out;
reg sign, sign_a, sign_b, fpu_op_1, fpu_op_2, fpu_op_3, fpu_op_4, fpu_op_final;
reg fpuf_2, fpuf_3, fpuf_4, fpuf_5, fpuf_6, fpuf_7, fpuf_8, fpuf_9, fpuf_10;
reg fpuf_11, fpuf_12, fpuf_13, fpuf_14, fpuf_15;
reg sign_a2, sign_a3, sign_b2, sign_b3, sign_2, sign_3, sign_4, sign_5, sign_6;
reg sign_7, sign_8, sign_9, sign_10, sign_11, sign_12;
reg [10:0] exponent_a, exponent_b, expa_2, expb_2, expa_3, expb_3;
reg [51:0] mantissa_a, mantissa_b, mana_2, mana_3, manb_2, manb_3;
reg expa_et_inf, expb_et_inf, input_is_inf, in_inf2, in_inf3, in_inf4, in_inf5;
reg in_inf6, in_inf7, in_inf8, in_inf9, in_inf10, in_inf11, in_inf12, in_inf13;
reg in_inf14, in_inf15, expa_gt_expb, expa_et_expb, mana_gtet_manb, a_gtet_b;
reg [10:0] exponent_small, exponent_large, expl_1, expl_2, expl_3, expl_4;
reg [10:0] expl_5, expl_6, expl_7, expl_8, expl_9, expl_10, expl_11;
reg [51:0] mantissa_small, mantissa_large;
reg [51:0] mantissa_small_2, mantissa_large_2;
reg [51:0] mantissa_small_3, mantissa_large_3;
reg exp_small_et0, exp_large_et0, exp_small_et0_2, exp_large_et0_2;
reg [10:0] exponent_diff, exponent_diff_2, exponent_diff_3, exponent_diff_4;
reg [53:0] large_add, large_add_2, large_add_3, small_add;
reg [53:0] small_shift, small_shift_2, small_shift_3, small_shift_4;
reg [53:0] large_add_4, large_add_5;
reg small_shift_nonzero;
reg small_is_nonzero, small_is_nonzero_2, small_is_nonzero_3;
reg small_fraction_enable;
wire [53:0] small_shift_LSB = { 53'b0, 1'b1 };
reg [53:0] sum, sum_2, sum_3, sum_4;
reg sum_overflow;
reg [10:0] exponent_add, exp_add2, exponent_sub, exponent_sub_2;
reg [52:0] minuend, minuend_2, minuend_3, minuend_4, minuend_5, subtrahend;
reg [52:0] subtra_shift, subtra_shift_2, subtra_shift_3, subtra_shift_4;
reg subtra_shift_nonzero;
reg subtra_fraction_enable;
wire [52:0] subtra_shift_LSB = { 52'b0, 1'b1 };
reg [5:0] diff_shift, diff_shift_2;
reg [52:0] diff, diff_2, diff_3, diff_4, diff_5;
reg diffshift_gt_exponent, diffshift_et_53;
reg ready, count_ready, count_ready_0;
reg [4:0] count;
 
always @(posedge clk)
begin
if (rst) begin
sign <= 0; fpu_op_1 <= 0; fpu_op_final <= 0; fpu_op_2 <= 0;
fpu_op_3 <= 0; fpu_op_4 <= 0; fpuf_2 <= 0; fpuf_3 <= 0; fpuf_4 <= 0;
fpuf_5 <= 0; fpuf_6 <= 0; fpuf_7 <= 0; fpuf_8 <= 0; fpuf_9 <= 0;
fpuf_10 <= 0; fpuf_11 <= 0; fpuf_12 <= 0; fpuf_13 <= 0; fpuf_14 <= 0;
fpuf_15 <= 0; sign_a <= 0; sign_b <= 0;
sign_a2 <= 0; sign_b2 <= 0; sign_a3 <= 0; sign_b3 <= 0;
exponent_a <= 0; exponent_b <= 0; expa_2 <= 0; expa_3 <= 0;
expb_2 <= 0; expb_3 <= 0; mantissa_a <= 0; mantissa_b <= 0; mana_2 <= 0; mana_3 <= 0;
manb_2 <= 0; manb_3 <= 0; expa_et_inf <= 0; expb_et_inf <= 0;
input_is_inf <= 0; in_inf2 <= 0; in_inf3 <= 0; in_inf4 <= 0; in_inf5 <= 0;
in_inf6 <= 0; in_inf7 <= 0; in_inf8 <= 0; in_inf9 <= 0; in_inf10 <= 0;
in_inf11 <= 0; in_inf12 <= 0; in_inf13 <= 0; in_inf14 <= 0; in_inf15 <= 0;
expa_gt_expb <= 0; expa_et_expb <= 0; mana_gtet_manb <= 0;
a_gtet_b <= 0; sign <= 0; sign_2 <= 0; sign_3 <= 0; sign_4 <= 0; sign_5 <= 0;
sign_6 <= 0; sign_7 <= 0; sign_8 <= 0; sign_9 <= 0;
sign_10 <= 0; sign_11 <= 0; sign_12 <= 0;
exponent_small <= 0; exponent_large <= 0; expl_1 <= 0; expl_2 <= 0;
expl_3 <= 0; expl_4 <= 0; expl_5 <= 0; expl_6 <= 0; expl_7 <= 0;
expl_8 <= 0; expl_9 <= 0; expl_10 <= 0; expl_11 <= 0;
exp_small_et0 <= 0; exp_large_et0 <= 0;
exp_small_et0_2 <= 0; exp_large_et0_2 <= 0;
mantissa_small <= 0; mantissa_large <= 0;
mantissa_small_2 <= 0; mantissa_large_2 <= 0;
mantissa_small_3 <= 0; mantissa_large_3 <= 0;
exponent_diff <= 0; exponent_diff_2 <= 0; exponent_diff_3 <= 0;
exponent_diff_4 <= 0; large_add <= 0; large_add_2 <= 0;
large_add_3 <= 0; large_add_4 <= 0; large_add_5 <= 0; small_add <= 0;
small_shift <= 0; small_shift_2 <= 0; small_shift_3 <= 0;
small_shift_4 <= 0; small_shift_nonzero <= 0;
small_is_nonzero <= 0; small_is_nonzero_2 <= 0; small_is_nonzero_3 <= 0;
small_fraction_enable <= 0;
sum <= 0; sum_2 <= 0; sum_overflow <= 0; sum_3 <= 0; sum_4 <= 0;
exponent_add <= 0; exp_add2 <= 0;
minuend <= 0; minuend_2 <= 0; minuend_3 <= 0;
minuend_4 <= 0; minuend_5 <= 0; subtrahend <= 0;
subtra_shift <= 0; subtra_shift_2 <= 0; subtra_shift_3 <= 0;
subtra_shift_4 <= 0; subtra_shift_nonzero <= 0;
subtra_fraction_enable <= 0; diff_shift_2 <= 0; diff <= 0;
diffshift_gt_exponent <= 0; diffshift_et_53 <= 0; diff_2 <= 0;
diff_3 <= 0; diff_4 <= 0; diff_5 <= 0; exponent_sub <= 0;
exponent_sub_2 <= 0; outfp <= 0; outfp_2 <= 0; out <= 0;
end
else if (enable) begin
fpu_op_1 <= fpu_op; fpu_op_final <= fpu_op_1 ^ (sign_a ^ sign_b);
fpuf_2 <= fpu_op_final; fpuf_3 <= fpuf_2; fpuf_4 <= fpuf_3;
fpuf_5 <= fpuf_4; fpuf_6 <= fpuf_5; fpuf_7 <= fpuf_6; fpuf_8 <= fpuf_7;
fpuf_9 <= fpuf_8; fpuf_10 <= fpuf_9; fpuf_11 <= fpuf_10; fpuf_12 <= fpuf_11;
fpuf_13 <= fpuf_12; fpuf_14 <= fpuf_13; fpuf_15 <= fpuf_14;
fpu_op_2 <= fpu_op_1; fpu_op_3 <= fpu_op_2; fpu_op_4 <= fpu_op_3;
sign_a <= opa[63]; sign_b <= opb[63]; sign_a2 <= sign_a;
sign_b2 <= sign_b; sign_a3 <= sign_a2; sign_b3 <= sign_b2;
exponent_a <= opa[62:52]; expa_2 <= exponent_a; expa_3 <= expa_2;
exponent_b <= opb[62:52]; expb_2 <= exponent_b; expb_3 <= expb_2;
mantissa_a <= opa[51:0]; mana_2 <= mantissa_a; mana_3 <= mana_2;
mantissa_b <= opb[51:0]; manb_2 <= mantissa_b; manb_3 <= manb_2;
expa_et_inf <= exponent_a == 2047;
expb_et_inf <= exponent_b == 2047;
input_is_inf <= expa_et_inf | expb_et_inf; in_inf2 <= input_is_inf;
in_inf3 <= in_inf2; in_inf4 <= in_inf3; in_inf5 <= in_inf4; in_inf6 <= in_inf5;
in_inf7 <= in_inf6; in_inf8 <= in_inf7; in_inf9 <= in_inf8; in_inf10 <= in_inf9;
in_inf11 <= in_inf10; in_inf12 <= in_inf11; in_inf13 <= in_inf12;
in_inf14 <= in_inf13; in_inf15 <= in_inf14;
expa_gt_expb <= exponent_a > exponent_b;
expa_et_expb <= exponent_a == exponent_b;
mana_gtet_manb <= mantissa_a >= mantissa_b;
a_gtet_b <= expa_gt_expb | (expa_et_expb & mana_gtet_manb);
sign <= a_gtet_b ? sign_a3 :!sign_b3 ^ (fpu_op_3 == 0);
sign_2 <= sign; sign_3 <= sign_2; sign_4 <= sign_3; sign_5 <= sign_4;
sign_6 <= sign_5; sign_7 <= sign_6; sign_8 <= sign_7; sign_9 <= sign_8;
sign_10 <= sign_9; sign_11 <= sign_10; sign_12 <= sign_11;
exponent_small <= a_gtet_b ? expb_3 : expa_3;
exponent_large <= a_gtet_b ? expa_3 : expb_3;
expl_2 <= exponent_large; expl_3 <= expl_2; expl_4 <= expl_3;
expl_5 <= expl_4; expl_6 <= expl_5; expl_7 <= expl_6; expl_8 <= expl_7;
expl_9 <= expl_8; expl_10 <= expl_9; expl_11 <= expl_10;
exp_small_et0 <= exponent_small == 0;
exp_large_et0 <= exponent_large == 0;
exp_small_et0_2 <= exp_small_et0;
exp_large_et0_2 <= exp_large_et0;
mantissa_small <= a_gtet_b ? manb_3 : mana_3;
mantissa_large <= a_gtet_b ? mana_3 : manb_3;
mantissa_small_2 <= mantissa_small;
mantissa_large_2 <= mantissa_large;
mantissa_small_3 <= exp_small_et0 ? 0 : mantissa_small_2;
mantissa_large_3 <= exp_large_et0 ? 0 : mantissa_large_2;
exponent_diff <= exponent_large - exponent_small;
exponent_diff_2 <= exponent_diff;
exponent_diff_3 <= exponent_diff_2;
exponent_diff_4 <= exponent_diff_3;
large_add <= { 1'b0, !exp_large_et0_2, mantissa_large_3};
large_add_2 <= large_add; large_add_3 <= large_add_2;
large_add_4 <= large_add_3; large_add_5 <= large_add_4;
small_add <= { 1'b0, !exp_small_et0_2, mantissa_small_3};
small_shift <= small_add >> exponent_diff_3;
small_shift_2 <= small_shift; small_shift_3 <= small_shift_2;
small_fraction_enable <= small_is_nonzero_3 & !small_shift_nonzero;
small_shift_4 <= small_fraction_enable ? small_shift_LSB : small_shift_3;
small_shift_nonzero <= |small_shift[53:0];
small_is_nonzero <= !exp_small_et0_2;
small_is_nonzero_2 <= small_is_nonzero; small_is_nonzero_3 <= small_is_nonzero_2;
sum <= large_add_5 + small_shift_4;
sum_overflow <= sum[53];
sum_2 <= sum;
sum_3 <= sum_overflow ? sum_2 >> 1 : sum_2;
sum_4 <= sum_3;
exponent_add <= sum_overflow ? expl_10 + 1: expl_10;
exp_add2 <= exponent_add;
minuend <= { !exp_large_et0_2, mantissa_large_3};
minuend_2 <= minuend; minuend_3 <= minuend_2;
minuend_4 <= minuend_3; minuend_5 <= minuend_4;
subtrahend <= { !exp_small_et0_2, mantissa_small_3};
subtra_shift <= subtrahend >> exponent_diff_3;
subtra_shift_2 <= subtra_shift;
subtra_shift_3 <= subtra_shift_2;
subtra_shift_nonzero <= |subtra_shift[52:0];
subtra_fraction_enable <= small_is_nonzero_3 & !subtra_shift_nonzero;
subtra_shift_4 <= subtra_fraction_enable ? subtra_shift_LSB : subtra_shift_3;
diff_shift_2 <= diff_shift;
diff <= minuend_5 - subtra_shift_4; diff_2 <= diff; diff_3 <= diff_2;
diffshift_gt_exponent <= diff_shift > expl_10;
diffshift_et_53 <= diff_shift_2 == 53;
diff_4 <= diffshift_gt_exponent ? diff_3 << expl_11 : diff_3 << diff_shift_2;
diff_5 <= diff_4;
exponent_sub <= diffshift_gt_exponent ? 0 : (expl_11 - diff_shift_2);
exponent_sub_2 <= diffshift_et_53 ? 0 : exponent_sub;
outfp <= {sign_12, exp_add2, sum_4[51:0]};
outfp_2 <= fpuf_15 ? {outfp[63], exponent_sub_2, diff_5[51:0]} : outfp;
out <= in_inf15 ? { outfp_2[63], 11'b11111111111, 52'b0 } : outfp_2;
end
end
 
 
always @(posedge clk)
casex(diff)
53'b1????????????????????????????????????????????????????: diff_shift <= 0;
53'b01???????????????????????????????????????????????????: diff_shift <= 1;
53'b001??????????????????????????????????????????????????: diff_shift <= 2;
53'b0001?????????????????????????????????????????????????: diff_shift <= 3;
53'b00001????????????????????????????????????????????????: diff_shift <= 4;
53'b000001???????????????????????????????????????????????: diff_shift <= 5;
53'b0000001??????????????????????????????????????????????: diff_shift <= 6;
53'b00000001?????????????????????????????????????????????: diff_shift <= 7;
53'b000000001????????????????????????????????????????????: diff_shift <= 8;
53'b0000000001???????????????????????????????????????????: diff_shift <= 9;
53'b00000000001??????????????????????????????????????????: diff_shift <= 10;
53'b000000000001?????????????????????????????????????????: diff_shift <= 11;
53'b0000000000001????????????????????????????????????????: diff_shift <= 12;
53'b00000000000001???????????????????????????????????????: diff_shift <= 13;
53'b000000000000001??????????????????????????????????????: diff_shift <= 14;
53'b0000000000000001?????????????????????????????????????: diff_shift <= 15;
53'b00000000000000001????????????????????????????????????: diff_shift <= 16;
53'b000000000000000001???????????????????????????????????: diff_shift <= 17;
53'b0000000000000000001??????????????????????????????????: diff_shift <= 18;
53'b00000000000000000001?????????????????????????????????: diff_shift <= 19;
53'b000000000000000000001????????????????????????????????: diff_shift <= 20;
53'b0000000000000000000001???????????????????????????????: diff_shift <= 21;
53'b00000000000000000000001??????????????????????????????: diff_shift <= 22;
53'b000000000000000000000001?????????????????????????????: diff_shift <= 23;
53'b0000000000000000000000001????????????????????????????: diff_shift <= 24;
53'b00000000000000000000000001???????????????????????????: diff_shift <= 25;
53'b000000000000000000000000001??????????????????????????: diff_shift <= 26;
53'b0000000000000000000000000001?????????????????????????: diff_shift <= 27;
53'b00000000000000000000000000001????????????????????????: diff_shift <= 28;
53'b000000000000000000000000000001???????????????????????: diff_shift <= 29;
53'b0000000000000000000000000000001??????????????????????: diff_shift <= 30;
53'b00000000000000000000000000000001?????????????????????: diff_shift <= 31;
53'b000000000000000000000000000000001????????????????????: diff_shift <= 32;
53'b0000000000000000000000000000000001???????????????????: diff_shift <= 33;
53'b00000000000000000000000000000000001??????????????????: diff_shift <= 34;
53'b000000000000000000000000000000000001?????????????????: diff_shift <= 35;
53'b0000000000000000000000000000000000001????????????????: diff_shift <= 36;
53'b00000000000000000000000000000000000001???????????????: diff_shift <= 37;
53'b000000000000000000000000000000000000001??????????????: diff_shift <= 38;
53'b0000000000000000000000000000000000000001?????????????: diff_shift <= 39;
53'b00000000000000000000000000000000000000001????????????: diff_shift <= 40;
53'b000000000000000000000000000000000000000001???????????: diff_shift <= 41;
53'b0000000000000000000000000000000000000000001??????????: diff_shift <= 42;
53'b00000000000000000000000000000000000000000001?????????: diff_shift <= 43;
53'b000000000000000000000000000000000000000000001????????: diff_shift <= 44;
53'b0000000000000000000000000000000000000000000001???????: diff_shift <= 45;
53'b00000000000000000000000000000000000000000000001??????: diff_shift <= 46;
53'b000000000000000000000000000000000000000000000001?????: diff_shift <= 47;
53'b0000000000000000000000000000000000000000000000001????: diff_shift <= 48;
53'b00000000000000000000000000000000000000000000000001???: diff_shift <= 49;
53'b000000000000000000000000000000000000000000000000001??: diff_shift <= 50;
53'b0000000000000000000000000000000000000000000000000001?: diff_shift <= 51;
53'b00000000000000000000000000000000000000000000000000001: diff_shift <= 52;
53'b00000000000000000000000000000000000000000000000000000: diff_shift <= 53;
endcase
 
always @(posedge clk)
begin
if (rst) begin
ready <= 0;
count_ready_0 <= 0;
count_ready <= 0;
end
else if (enable) begin
ready <= count_ready;
count_ready_0 <= count == 15;
count_ready <= count == 16;
end
end
 
always @(posedge clk)
begin
if (rst)
count <= 0;
else if (enable & !count_ready_0 & !count_ready)
count <= count + 1;
end
 
endmodule
/trunk/pipeline/fpu_mul_TB.v
0,0 → 1,145
 
`timescale 1ps / 1ps
module fpu_mul_tb;
 
reg clk;
reg rst;
reg enable;
reg [63:0]opa;
reg [63:0]opb;
wire ready;
wire [63:0] outfp;
 
 
 
 
fpu_mul UUT (
.clk(clk),
.rst(rst),
.enable(enable),
.opa(opa),
.opb(opb),
.ready(ready),
.outfp(outfp));
 
initial
begin : STIMUL
#0
rst = 1'b1;
enable = 1'b0;
#10000;
rst = 1'b0;
enable = 1'b1;
//inputA:5.6700000000e+001
//inputB:2.9900000000e+000
opa = 64'b0100000001001100010110011001100110011001100110011001100110011010;
opb = 64'b0100000000000111111010111000010100011110101110000101000111101100;
#10000;
//inputA:3.6600000000e-003
//inputB:9.9700000000e-008
opa = 64'b0011111101101101111110111001001110001001101101010010000000001000;
opb = 64'b0011111001111010110000110101010011110010110110010100110101111010;
#10000;
//inputA:4.5000000000e+048
//inputB:2.0000000000e+067
opa = 64'b0100101000001000101000011101011111010100101101100000000110000001;
opb = 64'b0100110111100111101111010010100111010001110010000111101000011001;
#10000;
//inputA:2.9999997039e-317
//inputB:4.0000000000e+067
opa = 64'b0000000000000000000000000000000000000000010111001010011100000011;
opb = 64'b0100110111110111101111010010100111010001110010000111101000011001;
#10000;
//inputA:-4.6990000000e+000
//inputB:6.0000000000e+089
opa = 64'b1100000000010010110010111100011010100111111011111001110110110010;
opb = 64'b0101001010010010110110011101010111010010010011000000001010101011;
#10000;
//inputA:3.0000000000e-200
//inputB:4.0000000000e-077
opa = 64'b0001011010000010010111101110110110001111111110110011100111000001;
opb = 64'b0011000000010010100001101101100000001110110000011001000011011100;
#10000;
//inputA:5.0000000000e-250
//inputB:4.0000000000e-100
opa = 64'b0000110000101100101000111000111100110101000010110010001011011111;
opb = 64'b0010101101001011111111110010111011100100100011100000010100110000;
#10000;
//inputA:1.#INF000000e+000
//inputB:2.0000000000e-200
opa = 64'b0111111111110000000000000000000000000000000000000000000000000000;
opb = 64'b0001011001111000011111101001001000010101010011101111011110101100;
#10000;
//inputA:8.9999000000e+004
//inputB:1.6000000000e+001
opa = 64'b0100000011110101111110001111000000000000000000000000000000000000;
opb = 64'b0100000000110000000000000000000000000000000000000000000000000000;
//Output:1.695330000000000e+002
#100000;
if (outfp==64'h4065310E56041894)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:3.649020000000000e-010
if (outfp==64'h3DF9136C82DFC196)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:8.999999999999999e+115
if (outfp==64'h580245EF347B07BD)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:1.199999881578528e-249
if (outfp==64'h0000000000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:-2.819400000000000e+090
if (outfp==64'hD2B625266303A947)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:1.200000000000000e-276
if (outfp==64'h06A5459E5A08DFFE)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:0.000000000000000e+000
if (outfp==64'h0000000000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:3.595386269724632e+108
if (outfp==64'h7FF0000000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#10000; //0
//Output:1.439984000000000e+006
if (outfp==64'h4135F8F000000000)
$display($time,"ps Answer is correct %h", outfp);
else
$display($time,"ps Error! out is incorrect %h", outfp);
#130000;
$finish;
end
always
begin : CLOCK_clk
 
clk = 1'b0;
#5000;
clk = 1'b1;
#5000;
end
 
 
endmodule
/trunk/pipeline/fpu_addsub_TB.v
0,0 → 1,274
 
`timescale 1ps / 1ps
module fpu_tb;
 
 
//Internal signals declarations:
reg clk;
reg rst;
reg enable;
reg fpu_op;
reg [63:0]opa;
reg [63:0]opb;
wire [63:0]out;
wire ready;
 
 
fpu UUT (
.clk(clk),
.rst(rst),
.enable(enable),
.fpu_op(fpu_op),
.opa(opa),
.opb(opb),
.out(out),
.ready(ready));
 
initial
begin : STIMUL
#0
enable = 1'b0;
rst = 1'b1;
fpu_op = 1'b1;
#10000; //0
enable = 1'b1;
rst = 1'b0;
//inputA:-8.7700000000e+000
//inputB:4.9600000000e+000
opa = 64'b1100000000100001100010100011110101110000101000111101011100001010;
opb = 64'b0100000000010011110101110000101000111101011100001010001111010111;
fpu_op = 1'b0;
#10000;
 
//inputA:5.6668000000e+004
//inputB:2.3300000000e+002
opa = 64'b0100000011101011101010111000000000000000000000000000000000000000;
opb = 64'b0100000001101101001000000000000000000000000000000000000000000000;
fpu_op = 1'b1;
#10000;
//inputA:4.8999000000e+004
//inputB:3.4700000000e+001
opa = 64'b0100000011100111111011001110000000000000000000000000000000000000;
opb = 64'b0100000001000001010110011001100110011001100110011001100110011010;
fpu_op = 1'b0;
#10000;
 
//inputA:1.0000000000e-200
//inputB:4.0000000000e-198
opa = 64'b0001011001101000011111101001001000010101010011101111011110101100;
opb = 64'b0001011011110011001000101110001000100000101001011011000101111110;
fpu_op = 1'b1;
 
#10000;
//inputA:8.9990000000e+003
//inputB:2.0000000000e-002
opa = 64'b0100000011000001100100111000000000000000000000000000000000000000;
opb = 64'b0011111110010100011110101110000101000111101011100001010001111011;
fpu_op = 1'b1;
 
#10000;
//inputA:4.4500000000e+002
//inputB:4.4437000000e+002
opa = 64'b0100000001111011110100000000000000000000000000000000000000000000;
opb = 64'b0100000001111011110001011110101110000101000111101011100001010010;
fpu_op = 1'b1;
 
#10000;
//inputA:4.9342000000e+001
//inputB:2.3000000000e-002
opa = 64'b0100000001001000101010111100011010100111111011111001110110110010;
opb = 64'b0011111110010111100011010100111111011111001110110110010001011010;
fpu_op = 1'b0;
 
 
#10000;
//inputA:6.9100000000e+001
//inputB:6.8770000000e+001
opa = 64'b0100000001010001010001100110011001100110011001100110011001100110;
opb = 64'b0100000001010001001100010100011110101110000101000111101011100001;
fpu_op = 1'b0;
 
#10000;
//inputA:-8.9990000000e+003
//inputB:-9.5666000000e+004
opa = 64'b1100000011000001100100111000000000000000000000000000000000000000;
opb = 64'b1100000011110111010110110010000000000000000000000000000000000000;
fpu_op = 1'b0;
 
#10000;
//inputA:9.8300000000e+001
//inputB:-9.5666700000e+004
opa = 64'b0100000001011000100100110011001100110011001100110011001100110011;
opb = 64'b1100000011110111010110110010101100110011001100110011001100110011;
fpu_op = 1'b1;
 
#10000;
//inputA:6.8700000000e+001
//inputB:-9.5511000000e+002
opa = 64'b0100000001010001001011001100110011001100110011001100110011001101;
opb = 64'b1100000010001101110110001110000101000111101011100001010001111011;
fpu_op = 1'b0;
 
#10000;
//inputA:-9.5400000000e+001
//inputB:9.8100000000e+001
opa = 64'b1100000001010111110110011001100110011001100110011001100110011010;
opb = 64'b0100000001011000100001100110011001100110011001100110011001100110;
fpu_op = 1'b1;
 
#10000;
//inputA:-9.6300000000e+001
//inputB:9.8300000000e+001
opa = 64'b1100000001011000000100110011001100110011001100110011001100110011;
opb = 64'b0100000001011000100100110011001100110011001100110011001100110011;
fpu_op = 1'b0;
 
#10000;
//inputA:-4.5600000000e+001
//inputB:-9.8660000000e+001
opa = 64'b1100000001000110110011001100110011001100110011001100110011001101;
opb = 64'b1100000001011000101010100011110101110000101000111101011100001010;
fpu_op = 1'b1;
 
#10000;
//inputA:2.0000000000e-308
//inputB:4.0000000000e-300
opa = 64'b0000000000001110011000011010110011110000001100111101000110100100;
opb = 64'b0000000111000101011011100001111111000010111110001111001101011001;
fpu_op = 1'b0;
 
#10000;
//inputA:1.#INF000000e+000
//inputB:3.0000000000e+100
opa = 64'b0111111111110000000000000000000000000000000000000000000000000000;
opb = 64'b0101010011001011011011101000001110111000010111110010010100111011;
fpu_op = 1'b1;
 
#30000;
//Output:-3.810000000000000e+000
if (out==64'hC00E7AE147AE147C)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! C00E7AE147AE147C out is %h", out);
//Output:5.643500000000000e+004
#10000;
if (out==64'h40EB8E6000000000)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 40EB8E6000000000 out is %h", out);
#10000;
//Output:4.903370000000000e+004
if (out==64'h40E7F13666666666)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 40E7F13666666666 out is %h", out);
#10000;
//Output:-3.990000000000000e-198
if (out==64'h96F316A2D79B0A03)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 96F316A2D79B0A03 out is %h", out);
#10000;
//Output:8.998980000000000e+003
if (out==64'h40C1937D70A3D70B)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 40C1937D70A3D70B out is %h", out);
 
#10000;
//Output:6.299999999999955e-001
if (out==64'h3FE428F5C28F5C00)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 3FE428F5C28F5C00 out is %h", out);
 
 
#10000;
//Output:4.936500000000000e+001
if (out==64'h4048AEB851EB851E)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 4048AEB851EB851E out is %h", out);
 
#10000;
//Output:1.378700000000000e+002
if (out==64'h40613BD70A3D70A3)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 40613BD70A3D70A3 out is %h", out);
 
 
#10000;
//Output:-1.046650000000000e+005
if (out==64'hC0F98D9000000000)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! C0F98D9000000000 out is %h", out);
 
#10000;
//Output:9.576500000000000e+004
if (out==64'h40F7614FFFFFFFFF)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 40F7614FFFFFFFFF out is %h", out);
 
#10000;
//Output:-8.864100000000001e+002
if (out==64'hC08BB347AE147AE2)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! C08BB347AE147AE2 out is %h", out);
 
#10000;
//Output:-1.935000000000000e+002
if (out==64'hC068300000000000)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! C068300000000000 out is %h", out);
 
#10000;
//Output:2.000000000000000e+000
if (out==64'h4000000000000000)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 4000000000000000 out is %h", out);
 
#10000;
//Output:5.306000000000000e+001
if (out==64'h404A87AE147AE148)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 404A87AE147AE148 out is %h", out);
 
#10000;
//Output:4.000000000000000e-300
if (out==64'h01C56E1FC2F8F359)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 01C56E1FC2F8F359 out is %h", out);
 
#10000;
//Output:1.#INF00000000000e+000
if (out==64'h7FF0000000000000)
$display($time,"ps Answer is correct %h", out);
else
$display($time,"ps Error! 7FF0000000000000 out is %h", out);
 
#290000;
$finish;
end
always
begin : CLOCK_clk
clk = 1'b0;
#5000;
clk = 1'b1;
#5000;
end
 
 
endmodule
/trunk/pipeline/fpu_mul.v
0,0 → 1,261
/////////////////////////////////////////////////////////////////////
//// ////
//// FPU ////
//// Floating Point Unit (Double precision) ////
//// ////
//// Author: David Lundgren ////
//// davidklun@gmail.com ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// davidklun@gmail.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
 
`timescale 1ns / 100ps
 
module fpu_mul( clk, rst, enable, opa, opb, ready, outfp);
input clk;
input rst;
input enable;
input [63:0] opa, opb;
output ready;
output [63:0] outfp;
 
 
 
reg product_shift;
reg sign, sign_1, sign_2, sign_3, sign_4, sign_5, sign_6, sign_7, sign_8;
reg sign_9, sign_10, sign_11, sign_12, sign_13, sign_14, sign_15, sign_16, sign_17;
reg [51:0] mantissa_a1, mantissa_a2;
reg [51:0] mantissa_b1, mantissa_b2;
reg [10:0] exponent_a;
reg [10:0] exponent_b;
reg ready, count_ready, count_ready_0;
reg [4:0] count;
reg a_is_zero, b_is_zero, a_is_inf, b_is_inf, in_inf_1, in_inf_2;
reg in_zero_1;
reg [11:0] exponent_terms_1, exponent_terms_2, exponent_terms_3, exponent_terms_4;
reg [11:0] exponent_terms_5, exponent_terms_6, exponent_terms_7;
reg [11:0] exponent_terms_8, exponent_terms_9;
reg exponent_gt_expoffset;
reg [11:0] exponent_1;
wire [11:0] exponent = 0;
reg [11:0] exponent_2, exponent_2_0, exponent_2_1;
reg exponent_gt_prodshift, exponent_is_infinity, exponent_is_infinity_2;
reg [11:0] exponent_3;
reg [11:0] exponent_4;
reg set_mantissa_zero;
reg [52:0] mul_a, mul_a1, mul_a2, mul_a3, mul_a4, mul_a5, mul_a6, mul_a7, mul_a8;
reg [52:0] mul_b, mul_b1, mul_b2, mul_b3, mul_b4, mul_b5, mul_b6, mul_b7, mul_b8;
reg [40:0] product_a;
reg [16:0] product_a_2, product_a_3, product_a_4, product_a_5, product_a_6;
reg [16:0] product_a_7, product_a_8, product_a_9, product_a_10;
reg [40:0] product_b;
reg [40:0] product_c;
reg [25:0] product_d;
reg [33:0] product_e;
reg [33:0] product_f;
reg [35:0] product_g;
reg [28:0] product_h;
reg [28:0] product_i;
reg [30:0] product_j;
reg [41:0] sum_0;
reg [6:0] sum_0_2, sum_0_3, sum_0_4, sum_0_5, sum_0_6, sum_0_7, sum_0_8, sum_0_9;
reg [35:0] sum_1;
reg [9:0] sum_1_2, sum_1_3, sum_1_4, sum_1_5, sum_1_6, sum_1_7, sum_1_8;
reg [41:0] sum_2;
reg [6:0] sum_2_2, sum_2_3, sum_2_4, sum_2_5, sum_2_6, sum_2_7;
reg [35:0] sum_3;
reg [36:0] sum_4;
reg [9:0] sum_4_2, sum_4_3, sum_4_4, sum_4_5;
reg [27:0] sum_5;
reg [6:0] sum_5_2, sum_5_3, sum_5_4;
reg [29:0] sum_6;
reg [36:0] sum_7;
reg [16:0] sum_7_2;
reg [30:0] sum_8;
reg [105:0] product;
reg [105:0] product_1;
reg [105:0] product_2, product_3;
reg product_lsb; // if there are any 1's in the remainder
reg [55:0] product_4;
reg [11:0] exponent_5, exponent_6;
wire [63:0] outfp = { sign, exponent_6[10:0], product_4[53:2]};
 
always @(posedge clk)
begin
if (rst) begin
sign <= 0; sign_1 <= 0; sign_2 <= 0; sign_3 <= 0; sign_4 <= 0;
sign_5 <= 0; sign_6 <= 0; sign_7 <= 0; sign_8 <= 0; sign_9 <= 0;
sign_10 <= 0; sign_11 <= 0; sign_12 <= 0; sign_13 <= 0;
sign_14 <= 0; sign_15 <= 0; sign_16 <= 0; sign_17 <= 0;
mantissa_a1 <= 0;
mantissa_b1 <= 0;
mantissa_a2 <= 0;
mantissa_b2 <= 0;
exponent_a <= 0;
exponent_b <= 0;
a_is_zero <= 0; b_is_zero <= 0;
a_is_inf <= 0; b_is_inf <= 0; in_inf_1 <= 0; in_inf_2 <= 0;
in_zero_1 <= 0;
exponent_terms_1 <= 0; exponent_terms_2 <= 0; exponent_terms_3 <= 0;
exponent_terms_4 <= 0; exponent_terms_5 <= 0; exponent_terms_6 <= 0;
exponent_terms_7 <= 0; exponent_terms_8 <= 0; exponent_terms_9 <= 0;
exponent_gt_expoffset <= 0;
exponent_1 <= 0;
exponent_2_0 <= 0; exponent_2_1 <= 0; exponent_2 <= 0; exponent_gt_prodshift <= 0;
exponent_is_infinity <= 0; exponent_is_infinity_2 <= 0;
exponent_3 <= 0;
exponent_4 <= 0;
set_mantissa_zero <= 0;
mul_a <= 0; mul_b <= 0; mul_a1 <= 0; mul_b1 <= 0; mul_a2 <= 0; mul_b2 <= 0;
mul_a3 <= 0; mul_b3 <= 0; mul_a4 <= 0; mul_b4 <= 0; mul_a5 <= 0; mul_b5 <= 0;
mul_a6 <= 0; mul_b6 <= 0; mul_a7 <= 0; mul_b7 <= 0; mul_a8 <= 0; mul_b8 <= 0;
product_a <= 0; product_a_2 <= 0; product_a_3 <= 0; product_a_4 <= 0; product_a_5 <= 0;
product_a_6 <= 0; product_a_7 <= 0; product_a_8 <= 0; product_a_9 <= 0; product_a_10 <= 0;
product_b <= 0; product_c <= 0; product_d <= 0; product_e <= 0; product_f <= 0;
product_g <= 0; product_h <= 0; product_i <= 0; product_j <= 0;
sum_0 <= 0; sum_0_2 <= 0; sum_0_3 <= 0; sum_0_4 <= 0; sum_0_5 <= 0; sum_0_6 <= 0;
sum_0_7 <= 0; sum_0_8 <= 0; sum_0_9 <= 0;
sum_1 <= 0; sum_1_2 <= 0; sum_1_3 <= 0; sum_1_4 <= 0; sum_1_5 <= 0; sum_1_6 <= 0;
sum_1_7 <= 0; sum_1_8 <= 0;
sum_2 <= 0; sum_2_2 <= 0; sum_2_3 <= 0; sum_2_4 <= 0; sum_2_5 <= 0; sum_2_6 <= 0; sum_2_7 <= 0;
sum_3 <= 0; sum_4 <= 0; sum_4_2 <= 0; sum_4_3 <= 0; sum_4_4 <= 0; sum_4_5 <= 0;
sum_5 <= 0; sum_5_2 <= 0; sum_5_3 <= 0; sum_5_4 <= 0;
sum_6 <= 0; sum_7 <= 0; sum_7_2 <= 0; sum_8 <= 0;
product <= 0;
product_1 <= 0;
product_2 <= 0; product_3 <= 0;
product_lsb <= 0;
exponent_5 <= 0; exponent_6 <= 0;
product_shift <= 0;
end
else if (enable) begin
sign_1 <= opa[63] ^ opb[63]; sign_2 <= sign_1; sign_3 <= sign_2; sign_4 <= sign_3;
sign_5 <= sign_4; sign_6 <= sign_5; sign_7 <= sign_6; sign_8 <= sign_7; sign_9 <= sign_8;
sign_10 <= sign_9; sign_11 <= sign_10; sign_12 <= sign_11; sign_13 <= sign_12;
sign_14 <= sign_13; sign_15 <= sign_14; sign_16 <= sign_15; sign_17 <= sign_16; sign <= sign_17;
mantissa_a1 <= opa[51:0];
mantissa_b1 <= opb[51:0];
mantissa_a2 <= mantissa_a1;
mantissa_b2 <= mantissa_b1;
exponent_a <= opa[62:52];
exponent_b <= opb[62:52];
a_is_zero <= !(|exponent_a);
b_is_zero <= !(|exponent_b);
a_is_inf <= exponent_a == 2047;
b_is_inf <= exponent_b == 2047;
in_inf_1 <= a_is_inf | b_is_inf;
in_inf_2 <= in_inf_1;
in_zero_1 <= a_is_zero | b_is_zero;
exponent_terms_1 <= exponent_a + exponent_b;
exponent_terms_2 <= exponent_terms_1;
exponent_terms_3 <= in_zero_1 ? 12'b0 : exponent_terms_2;
exponent_terms_4 <= in_inf_2 ? 12'b110000000000 : exponent_terms_3;
exponent_terms_5 <= exponent_terms_4;
exponent_terms_6 <= exponent_terms_5;
exponent_terms_7 <= exponent_terms_6;
exponent_terms_8 <= exponent_terms_7;
exponent_terms_9 <= exponent_terms_8;
exponent_gt_expoffset <= exponent_terms_9 > 1022;
exponent_1 <= exponent_terms_9 - 1022;
exponent_2_0 <= exponent_gt_expoffset ? exponent_1 : exponent;
exponent_2_1 <= exponent_2_0;
exponent_2 <= exponent_2_1;
exponent_is_infinity <= exponent_2 > 2046;
exponent_is_infinity_2 <= exponent_is_infinity;
exponent_3 <= exponent_2 - product_shift;
exponent_gt_prodshift <= exponent_2 >= product_shift;
exponent_4 <= exponent_gt_prodshift ? exponent_3 : exponent;
exponent_5 <= exponent_is_infinity_2 ? 12'b011111111111 : exponent_4;
set_mantissa_zero <= exponent_4 == 0 | exponent_is_infinity_2;
exponent_6 <= exponent_5;
mul_a <= { !a_is_zero, mantissa_a2 };
mul_b <= { !b_is_zero, mantissa_b2 };
mul_a1 <= mul_a; mul_b1 <= mul_b;
mul_a2 <= mul_a1; mul_b2 <= mul_b1; mul_a3 <= mul_a2; mul_b3 <= mul_b2;
mul_a4 <= mul_a3; mul_b4 <= mul_b3; mul_a5 <= mul_a4; mul_b5 <= mul_b4;
mul_a6 <= mul_a5; mul_b6 <= mul_b5; mul_a7 <= mul_a6; mul_b7 <= mul_b6;
mul_a8 <= mul_a7; mul_b8 <= mul_b7;
product_a <= mul_a[23:0] * mul_b[16:0]; product_a_2 <= product_a[16:0];
product_a_3 <= product_a_2; product_a_4 <= product_a_3; product_a_5 <= product_a_4;
product_a_6 <= product_a_5; product_a_7 <= product_a_6; product_a_8 <= product_a_7;
product_a_9 <= product_a_8; product_a_10 <= product_a_9;
product_b <= mul_a[23:0] * mul_b[33:17];
product_c <= mul_a2[23:0] * mul_b2[50:34];
product_d <= mul_a5[23:0] * mul_b5[52:51];
product_e <= mul_a1[40:24] * mul_b1[16:0];
product_f <= mul_a4[40:24] * mul_b4[33:17];
product_g <= mul_a7[40:24] * mul_b7[52:34];
product_h <= mul_a3[52:41] * mul_b3[16:0];
product_i <= mul_a6[52:41] * mul_b6[33:17];
product_j <= mul_a8[52:41] * mul_b8[52:34];
sum_0 <= product_a[40:17] + product_b; sum_0_2 <= sum_0[6:0]; sum_0_3 <= sum_0_2;
sum_0_4 <= sum_0_3; sum_0_5 <= sum_0_4; sum_0_6 <= sum_0_5; sum_0_7 <= sum_0_6;
sum_0_8 <= sum_0_7; sum_0_9 <= sum_0_8;
sum_1 <= sum_0[41:7] + product_e; sum_1_2 <= sum_1[9:0]; sum_1_3 <= sum_1_2;
sum_1_4 <= sum_1_3; sum_1_5 <= sum_1_4; sum_1_6 <= sum_1_5; sum_1_7 <= sum_1_6;
sum_1_8 <= sum_1_7;
sum_2 <= sum_1[35:10] + product_c; sum_2_2 <= sum_2[6:0]; sum_2_3 <= sum_2_2;
sum_2_4 <= sum_2_3; sum_2_5 <= sum_2_4; sum_2_6 <= sum_2_5; sum_2_7 <= sum_2_6;
sum_3 <= sum_2[41:7] + product_h;
sum_4 <= sum_3 + product_f; sum_4_2 <= sum_4[9:0]; sum_4_3 <= sum_4_2;
sum_4_4 <= sum_4_3; sum_4_5 <= sum_4_4;
sum_5 <= sum_4[36:10] + product_d; sum_5_2 <= sum_5[6:0];
sum_5_3 <= sum_5_2; sum_5_4 <= sum_5_3;
sum_6 <= sum_5[27:7] + product_i;
sum_7 <= sum_6 + product_g; sum_7_2 <= sum_7[16:0];
sum_8 <= sum_7[36:17] + product_j;
product <= { sum_8, sum_7_2[16:0], sum_5_4[6:0], sum_4_5[9:0], sum_2_7[6:0],
sum_1_8[9:0], sum_0_9[6:0], product_a_10[16:0] };
product_1 <= product << product_shift;
product_2 <= product_1; product_3 <= product_2;
product_4 <= set_mantissa_zero ? 56'b0 : { 1'b0, product_3[105:52] , |product_3[51:0]};
product_shift <= !sum_8[30];
end
end
 
always @(posedge clk)
begin
if (rst) begin
ready <= 0;
count_ready_0 <= 0;
count_ready <= 0;
end
else if (enable) begin
ready <= count_ready;
count_ready_0 <= count == 15;
count_ready <= count == 16;
end
end
 
always @(posedge clk)
begin
if (rst)
count <= 0;
else if (enable & !count_ready_0 & !count_ready)
count <= count + 1;
end
 
endmodule

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