URL
https://opencores.org/ocsvn/ha1588/ha1588/trunk
Subversion Repositories ha1588
Compare Revisions
- This comparison shows the changes necessary to convert path
/
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/ha1588/trunk/rtl/tsu/ptp_parser.v
7,10 → 7,10
input ptp_sop, |
input ptp_eop, |
input [ 1:0] ptp_mod, |
input [79:0] ptp_time, |
input [29:0] ptp_time, |
|
output reg ptp_found, |
output reg [91:0] ptp_infor |
output reg [41:0] ptp_infor |
); |
|
reg [31:0] ptp_data_d1; |
58,6 → 58,7
ptp_udp <= 1'b0; |
ptp_port <= 1'b0; |
ptp_event <= 1'b0; |
ptp_msgid <= 4'd0; |
ptp_seqid <= 8'd0; |
end |
else if (ptp_valid_d1 && ptp_sop_d1) begin |
66,11 → 67,14
ptp_udp <= 1'b0; |
ptp_port <= 1'b0; |
ptp_event <= 1'b0; |
ptp_msgid <= 4'd0; |
ptp_seqid <= 8'd0; |
end |
else begin |
if (ptp_valid_d1 && ptp_cnt==10'd4) // ether_type == vlan |
ptp_vlan <= ( ptp_data_d1[31:16]==16'h8100); |
else |
ptp_vlan <= 1'b0; |
if (ptp_valid_d1 && ptp_cnt==10'd4) // ether_type == ip |
ptp_ip <= ( ptp_data_d1[31:16]==16'h0800); |
if (ptp_valid_d1 && ptp_cnt==10'd6) // ip_type == udp |
90,11 → 94,11
always @(posedge rst or posedge clk) begin |
if (rst) begin |
ptp_found <= 1'b0; |
ptp_infor <= 91'd0; |
ptp_infor <= 42'd0; |
end |
else if (ptp_valid_d1 && ptp_sop_d1) begin |
ptp_found <= 1'b0; |
ptp_infor <= 91'd0; |
ptp_infor <= 42'd0; |
end |
else if (ptp_valid_d1 && ptp_eop_d1) begin |
ptp_found <= ptp_event; |
102,7 → 106,7
end |
else begin |
ptp_found <= 1'b0; |
ptp_infor <= 91'd0; |
ptp_infor <= 42'd0; |
end |
end |
|
/ha1588/trunk/rtl/tsu/tsu_queue.v
8,13 → 8,13
input [7:0] gmii_data, |
|
input rtc_timer_clk, |
input [79:0] rtc_timer_in, |
input [29:0] rtc_timer_in, |
|
input q_rst, |
input q_rd_clk, |
input q_rd_en, |
output [ 7:0] q_rd_stat, |
output [91:0] q_rd_data |
output [47:0] q_rd_data |
); |
|
// buffer gmii input |
60,10 → 60,10
ts_req_d3 <= ts_req_d2; |
end |
end |
reg [79:0] rtc_time_stamp; |
reg [29:0] rtc_time_stamp; |
always @(posedge rst or posedge rtc_timer_clk) begin |
if (rst) |
rtc_time_stamp <= 80'd0; |
rtc_time_stamp <= 30'd0; |
else |
if (ts_req_d2 & !ts_req_d3) |
rtc_time_stamp <= rtc_timer_in; |
90,10 → 90,10
ts_ack_d3 <= ts_ack_d2; |
end |
end |
reg [79:0] gmii_time_stamp; |
reg [29:0] gmii_time_stamp; |
always @(posedge rst or posedge gmii_clk) begin |
if (rst) begin |
gmii_time_stamp <= 80'd0; |
gmii_time_stamp <= 30'd0; |
ts_ack_clr <= 1'b0; |
end |
else begin |
162,7 → 162,7
// ptp packet parser here |
// works at 1/4 gmii_clk frequency, needs multicycle timing constraint |
wire ptp_found; |
wire [91:0] ptp_infor; |
wire [41:0] ptp_infor; |
ptp_parser parser( |
.clk(gmii_clk), |
.rst(rst), |
179,15 → 179,15
// ptp time stamp dcfifo |
wire q_wr_clk = gmii_clk; |
wire q_wr_en = ptp_found; |
wire [95:0] q_wr_data = {4'd0, ptp_infor}; |
wire [2:0] q_wrusedw; |
wire [2:0] q_rdusedw; |
wire [47:0] q_wr_data = {6'd0, ptp_infor}; |
wire [3:0] q_wrusedw; |
wire [3:0] q_rdusedw; |
|
ptp_queue queue( |
.aclr(q_rst), |
|
.wrclk(q_wr_clk), |
.wrreq(q_wr_en && q_wrusedw<=5), |
.wrreq(q_wr_en && q_wrusedw<=15), |
.data(q_wr_data), |
.wrusedw(q_wrusedw), |
|
197,6 → 197,6
.rdusedw(q_rdusedw) |
); |
|
assign q_rd_stat = {5'd0, q_rdusedw}; |
assign q_rd_stat = {4'd0, q_rdusedw}; |
|
endmodule |
/ha1588/trunk/rtl/tsu/ptp_queue.v
48,14 → 48,14
wrusedw); |
|
input aclr; |
input [95:0] data; |
input [47:0] data; |
input rdclk; |
input rdreq; |
input wrclk; |
input wrreq; |
output [95:0] q; |
output [2:0] rdusedw; |
output [2:0] wrusedw; |
output [47:0] q; |
output [3:0] rdusedw; |
output [3:0] wrusedw; |
`ifndef ALTERA_RESERVED_QIS |
// synopsys translate_off |
`endif |
64,12 → 64,12
// synopsys translate_on |
`endif |
|
wire [95:0] sub_wire0; |
wire [2:0] sub_wire1; |
wire [2:0] sub_wire2; |
wire [95:0] q = sub_wire0[95:0]; |
wire [2:0] wrusedw = sub_wire1[2:0]; |
wire [2:0] rdusedw = sub_wire2[2:0]; |
wire [47:0] sub_wire0; |
wire [3:0] sub_wire1; |
wire [3:0] sub_wire2; |
wire [47:0] q = sub_wire0[47:0]; |
wire [3:0] wrusedw = sub_wire1[3:0]; |
wire [3:0] rdusedw = sub_wire2[3:0]; |
|
dcfifo dcfifo_component ( |
.rdclk (rdclk), |
87,11 → 87,11
.wrfull ()); |
defparam |
dcfifo_component.intended_device_family = "Cyclone III", |
dcfifo_component.lpm_numwords = 8, |
dcfifo_component.lpm_numwords = 16, |
dcfifo_component.lpm_showahead = "OFF", |
dcfifo_component.lpm_type = "dcfifo", |
dcfifo_component.lpm_width = 96, |
dcfifo_component.lpm_widthu = 3, |
dcfifo_component.lpm_width = 48, |
dcfifo_component.lpm_widthu = 4, |
dcfifo_component.overflow_checking = "ON", |
dcfifo_component.rdsync_delaypipe = 4, |
dcfifo_component.underflow_checking = "ON", |
111,7 → 111,7
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" |
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" |
// Retrieval info: PRIVATE: Clock NUMERIC "4" |
// Retrieval info: PRIVATE: Depth NUMERIC "8" |
// Retrieval info: PRIVATE: Depth NUMERIC "16" |
// Retrieval info: PRIVATE: Empty NUMERIC "1" |
// Retrieval info: PRIVATE: Full NUMERIC "1" |
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
124,11 → 124,11
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" |
// Retrieval info: PRIVATE: UsedW NUMERIC "1" |
// Retrieval info: PRIVATE: Width NUMERIC "96" |
// Retrieval info: PRIVATE: Width NUMERIC "48" |
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1" |
// Retrieval info: PRIVATE: diff_widths NUMERIC "0" |
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0" |
// Retrieval info: PRIVATE: output_width NUMERIC "96" |
// Retrieval info: PRIVATE: output_width NUMERIC "48" |
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0" |
// Retrieval info: PRIVATE: rsFull NUMERIC "0" |
// Retrieval info: PRIVATE: rsUsedW NUMERIC "1" |
139,11 → 139,11
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1" |
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all |
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" |
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "8" |
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" |
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" |
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" |
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "96" |
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "3" |
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "48" |
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" |
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" |
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" |
151,27 → 151,27
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" |
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4" |
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr" |
// Retrieval info: USED_PORT: data 0 0 96 0 INPUT NODEFVAL "data[95..0]" |
// Retrieval info: USED_PORT: q 0 0 96 0 OUTPUT NODEFVAL "q[95..0]" |
// Retrieval info: USED_PORT: data 0 0 48 0 INPUT NODEFVAL "data[47..0]" |
// Retrieval info: USED_PORT: q 0 0 48 0 OUTPUT NODEFVAL "q[47..0]" |
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk" |
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" |
// Retrieval info: USED_PORT: rdusedw 0 0 3 0 OUTPUT NODEFVAL "rdusedw[2..0]" |
// Retrieval info: USED_PORT: rdusedw 0 0 4 0 OUTPUT NODEFVAL "rdusedw[3..0]" |
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk" |
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" |
// Retrieval info: USED_PORT: wrusedw 0 0 3 0 OUTPUT NODEFVAL "wrusedw[2..0]" |
// Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL "wrusedw[3..0]" |
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 |
// Retrieval info: CONNECT: @data 0 0 96 0 data 0 0 96 0 |
// Retrieval info: CONNECT: @data 0 0 48 0 data 0 0 48 0 |
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 |
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 |
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 |
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 |
// Retrieval info: CONNECT: q 0 0 96 0 @q 0 0 96 0 |
// Retrieval info: CONNECT: rdusedw 0 0 3 0 @rdusedw 0 0 3 0 |
// Retrieval info: CONNECT: wrusedw 0 0 3 0 @wrusedw 0 0 3 0 |
// Retrieval info: CONNECT: q 0 0 48 0 @q 0 0 48 0 |
// Retrieval info: CONNECT: rdusedw 0 0 4 0 @rdusedw 0 0 4 0 |
// Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.inc FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_bb.v TRUE |
// Retrieval info: GEN_FILE: TYPE_NORMAL ptp_queue_bb.v FALSE |
// Retrieval info: LIB_FILE: altera_mf |
/ha1588/trunk/sim/tsu/tsu_queue_tb.v
14,7 → 14,7
reg q_rd_clk; |
reg q_rd_en; |
wire [ 7:0] q_rd_stat; |
wire [91:0] q_rd_data; |
wire [47:0] q_rd_data; |
|
initial begin |
DUT_RX.ts_ack = 1'b0; |
48,7 → 48,7
.gmii_data(gmii_rxdata), |
|
.rtc_timer_clk(rtc_timer_clk), |
.rtc_timer_in(rtc_timer_in), |
.rtc_timer_in(rtc_timer_in[29:0]), |
|
.q_rst(rst), |
.q_rd_clk(q_rd_clk), |
73,7 → 73,7
.gmii_data(gmii_txdata), |
|
.rtc_timer_clk(rtc_timer_clk), |
.rtc_timer_in(rtc_timer_in), |
.rtc_timer_in(rtc_timer_in[29:0]), |
|
.q_rst(rst), |
.q_rd_clk(q_rd_clk), |