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Rev 6 → Rev 7

/i650/trunk/rtl/defines.v
31,16 → 31,16
// Bi-quinary binary codes
//-----------------------------------------------------------------------------
`define biq_blank 7'b00_00000
`define biq_0 7'b01_00001
`define biq_1 7'b01_00010
`define biq_2 7'b01_00100
`define biq_3 7'b01_01000
`define biq_4 7'b01_10000
`define biq_5 7'b10_00001
`define biq_6 7'b10_00010
`define biq_7 7'b10_00100
`define biq_8 7'b10_01000
`define biq_9 7'b10_10000
`define biq_0 7'b01_00001
`define biq_1 7'b01_00010
`define biq_2 7'b01_00100
`define biq_3 7'b01_01000
`define biq_4 7'b01_10000
`define biq_5 7'b10_00001
`define biq_6 7'b10_00010
`define biq_7 7'b10_00100
`define biq_8 7'b10_01000
`define biq_9 7'b10_10000
`define biq_plus 7'b10_10000
`define biq_minus 7'b10_01000
 
59,14 → 59,62
// 2 of 5 drum recording codes
//-----------------------------------------------------------------------------
`define drum2of5_blank 5'b00000
`define drum2of5_0 5'b01100
`define drum2of5_1 5'b11000
`define drum2of5_2 5'b10100
`define drum2of5_3 5'b10010
`define drum2of5_4 5'b01010
`define drum2of5_5 5'b00110
`define drum2of5_6 5'b10001
`define drum2of5_7 5'b01001
`define drum2of5_8 5'b00101
`define drum2of5_9 5'b00011
`define drum2of5_0 5'b01100
`define drum2of5_1 5'b11000
`define drum2of5_2 5'b10100
`define drum2of5_3 5'b10010
`define drum2of5_4 5'b01010
`define drum2of5_5 5'b00110
`define drum2of5_6 5'b10001
`define drum2of5_7 5'b01001
`define drum2of5_8 5'b00101
`define drum2of5_9 5'b00011
 
//-----------------------------------------------------------------------------
// Console control commands
//-----------------------------------------------------------------------------
`define cmd_none 6'd0
// set switch position
`define cmd_pgm_sw_stop 6'd1
`define cmd_pgm_sw_run 6'd2
`define cmd_half_cycle_sw_run 6'd3
`define cmd_half_cycle_sw_half 6'd4
`define cmd_ctl_sw_addr_stop 6'd5
`define cmd_ctl_sw_run 6'd6
`define cmd_ctl_sw_manual 6'd7
`define cmd_disp_sw_lacc 6'd8
`define cmd_disp_sw_uacc 6'd9
`define cmd_disp_sw_dist 6'd10
`define cmd_disp_sw_prog 6'd11
`define cmd_disp_sw_ri 6'd12
`define cmd_disp_sw_ro 6'd13
`define cmd_ovflw_sw_stop 6'd14
`define cmd_ovflw_sw_sense 6'd15
`define cmd_err_sw_stop 6'd16
`define cmd_err_sw_sense 6'd17
// press key
`define cmd_xfer_key 6'd18
`define cmd_pgm_start_key 6'd19
`define cmd_pgm_stop_key 6'd20
`define cmd_pgm_reset_key 6'd21
`define cmd_comp_reset_key 6'd22
`define cmd_acc_reset_key 6'd23
`define cmd_err_reset_key 6'd24
`define cmd_err_sense_reset_key 6'd25
// set address select and storage entry switches
`define cmd_storage_entry_sw 6'd26
`define cmd_addr_sel_sw 6'd27
// read/write general storage
`define cmd_read_gs 6'd28
`define cmd_write_gs 6'd29
// read machine registers
`define cmd_read_acc 6'd30
`define cmd_read_dist 6'd31
`define cmd_read_prog 6'd32
// general storage (drum)
`define cmd_clear_gs 6'd33
`define cmd_load_gs 6'd34
`define cmd_dump_gs 6'd35
// resets
`define cmd_power_on_reset 6'd36
`define cmd_reset_console 6'd37
/i650/trunk/rtl/operator_ctl.v
0,0 → 1,616
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: Operator console and external control interface.
//
// Additional Comments: See US 2959351, Fig. 75, 76, 76 and 77. Also implements
// a simple command-based control interface.
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module operator_ctl (
input rst,
input ap, dp,
input dx, d0, d1, d2, d3, d4, d5, d6, d10,
input wu, hp,
input [0:3] early_idx, ontime_idx,
input [0:6] cmd_digit_in, io_buffer_in,
input [0:5] command,
output reg[0:6] data_out, addr_out,
output reg console_to_addr,
output reg[0:14] gs_ram_addr,
output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
output run_control, half_or_pgm_stop, ri_storage, ro_storage,
storage_control,
output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
output reg[0:6] cmd_digit_out,
output reg busy, digit_ready,
output reg punch_card, read_card, card_digit_ready
);
//-----------------------------------------------------------------------------
// Operator console switch settings
//-----------------------------------------------------------------------------
reg pgm_sw_stop, pgm_sw_run,
half_cycle_sw_run, half_cycle_sw_half,
ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,
disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,
disp_sw_ri, disp_sw_ro,
ovflw_sw_stop, ovflw_sw_sense, err_sw_stop, err_sw_sense;
reg [0:6] storage_entry_sw [0:15];
reg [0:6] addr_sel_sw [0:3];
assign run_control = disp_sw_lacc | disp_sw_uacc | disp_sw_dist | disp_sw_pgm;
assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
assign ri_storage = disp_sw_ri;
assign ro_storage = disp_sw_ro;
assign storage_control = run_control | disp_sw_ro;
reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
do_pgm_reset, do_acc_reset;
reg [0:5] state;
reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
wire [0:14] gs_band_addr, gs_word_offset;
ram_band_addr rba(gs_addr_th[`biq_q1], gs_addr_h, gs_addr_t[`biq_b5],
gs_band_addr);
ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
 
`define state_idle 6'd0
`define state_reset_console_1 6'd1
`define state_reset_console_2 6'd2
`define state_pgm_reset_1 6'd3
`define state_pgm_reset_2 6'd4
`define state_acc_reset_1 6'd5
`define state_acc_reset_2 6'd6
`define state_err_reset_1 6'd7
`define state_err_reset_2 6'd8
`define state_err_sense_reset_1 6'd9
`define state_err_sense_reset_2 6'd10
 
`define state_storage_entry_sw_1 6'd11
`define state_storage_entry_sw_2 6'd12
`define state_addr_sel_sw_1 6'd13
`define state_addr_sel_sw_2 6'd14
`define state_xfer_key_1 6'd15
`define state_xfer_key_2 6'd16
`define state_pgm_start_key_1 6'd17
`define state_pgm_start_key_2 6'd18
`define state_pgm_stop_key_1 6'd19
`define state_pgm_stop_key_2 6'd20
`define state_read_gs_1 6'd31
`define state_read_gs_2 6'd32
`define state_read_gs_3 6'd33
`define state_read_gs_4 6'd34
//-----------------------------------------------------------------------------
// Operator console state machine
//-----------------------------------------------------------------------------
always @(posedge rst, posedge dp) begin
if (rst) begin
console_to_addr <= 0;
pgm_start <= 0;
pgm_stop <= 0;
err_reset <= 0;
err_sense_reset <= 0;
man_pgm_reset <= 0;
man_acc_reset <= 0;
set_8000 <= 0;
reset_8000 <= 0;
// reset console switches
pgm_sw_stop <= 0;
pgm_sw_run <= 1;
ctl_sw_addr_stop <= 0;
ctl_sw_run <= 1;
ctl_sw_manual <= 0;
disp_sw_lacc <= 0;
disp_sw_uacc <= 0;
disp_sw_dist <= 1;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
ovflw_sw_stop <= 1;
ovflw_sw_sense <= 0;
err_sw_stop <= 1;
err_sw_sense <= 0;
state <= `state_idle;
busy <= 1;
digit_ready <= 0;
cmd_digit_out <= `biq_blank;
do_power_on_reset <= 1;
do_reset_console <= 0;
do_err_reset <= 0;
do_err_sense_reset <= 0;
do_pgm_reset <= 0;
do_acc_reset <= 0;
gs_ram_addr <= 15'd0;
end else begin
case (state)
`state_idle: begin
case (command)
`cmd_none: begin
if (do_power_on_reset) begin
do_power_on_reset <= 0;
do_reset_console <= 1;
do_pgm_reset <= 1;
do_acc_reset <= 1;
do_err_reset <= 1;
do_err_sense_reset <= 1;
end else if (do_reset_console) begin
do_reset_console <= 0;
state <= `state_reset_console_1;
end else if (do_pgm_reset) begin
do_pgm_reset <= 0;
state <= `state_pgm_reset_1;
end else if (do_acc_reset) begin
do_acc_reset <= 0;
man_acc_reset <= 1;
state <= `state_acc_reset_1;
end else if (do_err_reset) begin
do_err_reset <= 0;
err_reset <= 1;
state <= `state_err_reset_1;
end else if (do_err_sense_reset) begin
do_err_sense_reset <= 0;
err_sense_reset <= 1;
state <= `state_err_sense_reset_1;
end else begin
busy <= 0;
digit_ready <= 0;
end
end
`cmd_pgm_sw_stop: begin
busy <= 1;
pgm_sw_stop <= 1;
pgm_sw_run <= 0;
end
`cmd_pgm_sw_run: begin
busy <= 1;
pgm_sw_stop <= 0;
pgm_sw_run <= 1;
end
`cmd_half_cycle_sw_run: begin
busy <= 1;
half_cycle_sw_run <= 1;
half_cycle_sw_half <= 0;
end
`cmd_half_cycle_sw_half: begin
busy <= 1;
half_cycle_sw_run <= 0;
half_cycle_sw_half <= 1;
end
`cmd_ctl_sw_addr_stop: begin
busy <= 1;
ctl_sw_addr_stop <= 1;
ctl_sw_run <= 0;
ctl_sw_manual <= 0;
end
`cmd_ctl_sw_run: begin
busy <= 1;
ctl_sw_addr_stop <= 0;
ctl_sw_run <= 1;
ctl_sw_manual <= 0;
end
`cmd_ctl_sw_manual: begin
busy <= 1;
ctl_sw_addr_stop <= 0;
ctl_sw_run <= 0;
ctl_sw_manual <= 1;
end
`cmd_disp_sw_lacc: begin
busy <= 1;
disp_sw_lacc <= 1;
disp_sw_uacc <= 0;
disp_sw_dist <= 0;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
end
`cmd_disp_sw_uacc: begin
busy <= 1;
disp_sw_lacc <= 0;
disp_sw_uacc <= 1;
disp_sw_dist <= 0;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
end
`cmd_disp_sw_dist: begin
busy <= 1;
disp_sw_lacc <= 0;
disp_sw_uacc <= 0;
disp_sw_dist <= 1;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
end
`cmd_disp_sw_prog: begin
busy <= 1;
disp_sw_lacc <= 0;
disp_sw_uacc <= 0;
disp_sw_dist <= 0;
disp_sw_pgm <= 1;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
end
`cmd_disp_sw_ri: begin
busy <= 1;
disp_sw_lacc <= 0;
disp_sw_uacc <= 0;
disp_sw_dist <= 0;
disp_sw_pgm <= 0;
disp_sw_ri <= 1;
disp_sw_ro <= 0;
end
`cmd_disp_sw_ro: begin
busy <= 1;
disp_sw_lacc <= 0;
disp_sw_uacc <= 0;
disp_sw_dist <= 0;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 1;
end
`cmd_ovflw_sw_stop: begin
busy <= 1;
ovflw_sw_stop <= 1;
ovflw_sw_sense <= 0;
end
`cmd_ovflw_sw_sense: begin
busy <= 1;
ovflw_sw_stop <= 0;
ovflw_sw_sense <= 1;
end
`cmd_err_sw_stop: begin
busy <= 1;
err_sw_stop <= 1;
err_sw_sense <= 0;
end
`cmd_err_sw_sense: begin
busy <= 1;
err_sw_stop <= 0;
err_sw_sense <= 1;
end
`cmd_storage_entry_sw: begin
busy <= 1;
state <= `state_storage_entry_sw_1;
end
`cmd_addr_sel_sw: begin
busy <= 1;
state <= `state_addr_sel_sw_1;
end
`cmd_xfer_key: begin
if (ctl_sw_manual) begin
busy <= 1;
state <= `state_xfer_key_1;
end
end
`cmd_pgm_start_key: begin
busy <= 1;
state <= `state_pgm_start_key_1;
end
`cmd_pgm_stop_key: begin
busy <= 1;
pgm_stop <= 1;
state <= `state_pgm_stop_key_1;
end
`cmd_pgm_reset_key: begin
do_pgm_reset <= 1;
do_err_reset <= 1;
end
 
`cmd_comp_reset_key: begin
do_pgm_reset <= 1;
do_acc_reset <= 1;
do_err_reset <= 1;
end
`cmd_acc_reset_key: begin
do_acc_reset <= 1;
do_err_reset <= 1;
end
`cmd_err_reset_key: begin
do_err_reset <= 1;
end
`cmd_err_sense_reset_key: begin
do_err_sense_reset <= 1;
end
//--------------------------------------------------------------
// Read from general storage:
// --> 4 digits address, little-endian
// <-- 1 digit sign, 10 digits, little-endian
// 0 : Ignore if CPU not stopped
// Accept low-order address digit
// 1 : Accept remaining address digits
// 2 : Calculate word origin in gs RAM
// Validate address
// console_read_gs <= 1;
// 3 : Send gs-early digit to out
// digit_ready <= 1;
// 4 : digit_ready <= 0;
//--------------------------------------------------------------
`cmd_read_gs: begin
if (ctl_sw_manual) begin
busy <= 1;
state <= `state_read_gs_1;
end
end
`ifdef 0
`cmd_write_gs:
`cmd_read_acc:
`cmd_read_dist:
`cmd_read_prog:
`cmd_clear_gs:
`cmd_load_gs:
`cmd_dump_gs:
`cmd_power_on_reset:
`cmd_reset_console:
`endif
endcase;
end
// Reset console
`state_reset_console_1: begin
if (d10) state <= `state_reset_console_2;
end
`state_reset_console_2: begin
storage_entry_sw[ontime_idx] <= d0? `biq_plus : `biq_0;
addr_sel_sw[ontime_idx[2:3]] <= `biq_0;
if (d10) state <= `state_idle;
end
// Program reset key press
`state_pgm_reset_1: begin
if (wu & d10) begin
man_pgm_reset <= 1;
state <= `state_pgm_reset_2;
end
end
`state_pgm_reset_2: begin
if (wu & d10) begin
man_pgm_reset <= 0;
state <= `state_idle;
end
end
// Accumulator reset key press
`state_acc_reset_1: begin
if (wu & d10) begin
man_acc_reset <= 1;
state <= `state_acc_reset_2;
end
end
`state_acc_reset_2: begin
if (wu & d10) begin
man_acc_reset <= 0;
state <= `state_idle;
end
end
// Error reset key press
`state_err_reset_1: begin
if (wu & d10) begin
err_reset <= 1;
state <= `state_err_reset_2;
end
end
`state_err_reset_2: begin
if (wu & d10) begin
err_reset <= 0;
state <= `state_idle;
end
end
// Error sense reset key press
`state_err_sense_reset_1: begin
if (wu & d10) begin
err_sense_reset <= 1;
state <= `state_err_sense_reset_2;
end
end
`state_err_sense_reset_2: begin
if (wu & d10) begin
err_sense_reset <= 0;
state <= `state_idle;
end
end
// Set storage entry switches
`state_storage_entry_sw_1: begin
if (d0) begin
state <= `state_storage_entry_sw_2;
digit_ready <= 1;
storage_entry_sw[ontime_idx] <= cmd_digit_in;
end
end
`state_storage_entry_sw_2: begin
storage_entry_sw[ontime_idx] <= cmd_digit_in;
if (d10) begin
state <= `state_idle;
digit_ready <= 0;
end
end
// Set address selection switches
`state_addr_sel_sw_1: begin
if (dx) begin
state <= `state_addr_sel_sw_2;
digit_ready <= 1;
addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
end
end
`state_addr_sel_sw_2: begin
addr_sel_sw[ontime_idx[2:3]] <= cmd_digit_in;
if (d2) begin
state <= `state_idle;
digit_ready <= 0;
end
end
// Transfer key press
`state_xfer_key_1: begin
if (d10) begin
console_to_addr <= 1;
state <= `state_xfer_key_2;
end
end
`state_xfer_key_2: begin
if (d10) begin
console_to_addr <= 0;
state <= `state_idle;
end
end
// Start key press
`state_pgm_start_key_1: begin
if (wu & d10) begin
pgm_start <= 1;
state <= `state_pgm_start_key_2;
end
end
`state_pgm_start_key_2: begin
if (wu & d10) begin
pgm_start <= 0;
state <= `state_idle;
end
end
// Stop key press
`state_pgm_stop_key_1: begin
if (hp) state <= `state_pgm_stop_key_2;
end
`state_pgm_stop_key_2: begin
if (hp) begin
pgm_stop <= 0;
state <= `state_idle;
end
end
// Read word from general storage
// --> 4 digits address, little-endian
// <-- 1 digit sign, 10 digits, little-endian
// 0 : Ignore if CPU not stopped
// Accept low-order address digit
// 1 : Accept remaining address digits
// 2 : Calculate word origin in gs RAM
// Validate address
// console_read_gs <= 1;
// 3 : Send gs-early digit to out
// digit_ready <= 1;
// 4 : digit_ready <= 0;
`state_read_gs_1: begin
if (dx) begin
state <= `state_read_gs_2;
digit_ready <= 1;
gs_addr_u <= cmd_digit_in;
end
end
`state_read_gs_2: begin
if (d0) gs_addr_t <= cmd_digit_in;
else if (d1) gs_addr_h <= cmd_digit_in;
else if (d2) begin
gs_addr_th <= cmd_digit_in;
state <= `state_read_gs_3;
digit_ready <= 0;
end
end
`state_read_gs_3: begin
gs_ram_addr <= gs_word_addr;
state <= `state_read_gs_4;
end
endcase;
end
end;
always @(posedge rst, posedge ap) begin
if (rst) begin
data_out <= `biq_blank;
addr_out <= `biq_blank;
end else begin
data_out <= d10? `biq_blank : storage_entry_sw[early_idx];
addr_out <= (d3 | d4 | d5 | d6)? addr_sel_sw[early_idx[2:3]] : `biq_blank;
end
end;
always @(posedge rst, posedge ap) begin
if (rst) begin
punch_card <= 0;
read_card <= 0;
card_digit_ready <= 0;
end
end;
endmodule
/i650/trunk/rtl/ram_band_addr.v
0,0 → 1,92
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description:
// Convert "static" portion of a 650 address into a binary origin that is a
// multiple of 600. Used to address RAM representing general storage. In the
// real 650 this would be the band address which would select a band of five
// drum tracks.
//
// Additional Comments:
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
 
module ram_band_addr (
input addr_th_q1,
input [0:6] addr_h,
input addr_t_b5,
output reg [0:14] origin
);
always @(*) begin
case({addr_th_q1, addr_h, addr_t_b5})
9'b0_01_00001_0: origin = 15'd0;
9'b0_01_00001_1: origin = 15'd600;
9'b0_01_00010_0: origin = 15'd1200;
9'b0_01_00010_1: origin = 15'd1800;
9'b0_01_00100_0: origin = 15'd2400;
9'b0_01_00100_1: origin = 15'd3000;
9'b0_01_01000_0: origin = 15'd3600;
9'b0_01_01000_1: origin = 15'd4200;
9'b0_01_10000_0: origin = 15'd4800;
9'b0_01_10000_1: origin = 15'd5400;
9'b0_10_00001_0: origin = 15'd6000;
9'b0_10_00001_1: origin = 15'd6600;
9'b0_10_00010_0: origin = 15'd7200;
9'b0_10_00010_1: origin = 15'd7800;
9'b0_10_00100_0: origin = 15'd8400;
9'b0_10_00100_1: origin = 15'd9000;
9'b0_10_01000_0: origin = 15'd9600;
9'b0_10_01000_1: origin = 15'd10200;
9'b0_10_10000_0: origin = 15'd10800;
9'b0_10_10000_1: origin = 15'd11400;
 
9'b1_01_00001_0: origin = 15'd12000;
9'b1_01_00001_1: origin = 15'd12600;
9'b1_01_00010_0: origin = 15'd13200;
9'b1_01_00010_1: origin = 15'd13800;
9'b1_01_00100_0: origin = 15'd14400;
9'b1_01_00100_1: origin = 15'd15000;
9'b1_01_01000_0: origin = 15'd15600;
9'b1_01_01000_1: origin = 15'd16200;
9'b1_01_10000_0: origin = 15'd16800;
9'b1_01_10000_1: origin = 15'd17400;
9'b1_10_00001_0: origin = 15'd18000;
9'b1_10_00001_1: origin = 15'd18600;
9'b1_10_00010_0: origin = 15'd19200;
9'b1_10_00010_1: origin = 15'd19800;
9'b1_10_00100_0: origin = 15'd20400;
9'b1_10_00100_1: origin = 15'd21000;
9'b1_10_01000_0: origin = 15'd21600;
9'b1_10_01000_1: origin = 15'd22200;
9'b1_10_10000_0: origin = 15'd22800;
9'b1_10_10000_1: origin = 15'd23400;
 
default: origin = 15'd0;
endcase;
end;
 
endmodule
/i650/trunk/rtl/ram_word_offset.v
0,0 → 1,99
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description:
// Convert dynamic portion of 650 address into a word offset in general
// storage RAM.
//
// Additional Comments:
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
 
module ram_word_offset (
input [0:6] addr_t, addr_u,
output reg [0:14] offset
);
always @(*) begin
case({addr_t[2:6], addr_u})
12'b00001_01_00001: offset = 15'd0;
12'b00001_01_00010: offset = 15'd12;
12'b00001_01_00100: offset = 15'd24;
12'b00001_01_01000: offset = 15'd36;
12'b00001_01_10000: offset = 15'd48;
12'b00001_10_00001: offset = 15'd60;
12'b00001_10_00010: offset = 15'd72;
12'b00001_10_00100: offset = 15'd84;
12'b00001_10_01000: offset = 15'd96;
12'b00001_10_10000: offset = 15'd108;
 
12'b00010_01_00001: offset = 15'd120;
12'b00010_01_00010: offset = 15'd132;
12'b00010_01_00100: offset = 15'd144;
12'b00010_01_01000: offset = 15'd156;
12'b00010_01_10000: offset = 15'd168;
12'b00010_10_00001: offset = 15'd180;
12'b00010_10_00010: offset = 15'd192;
12'b00010_10_00100: offset = 15'd204;
12'b00010_10_01000: offset = 15'd216;
12'b00010_10_10000: offset = 15'd228;
 
12'b00100_01_00001: offset = 15'd240;
12'b00100_01_00010: offset = 15'd252;
12'b00100_01_00100: offset = 15'd264;
12'b00100_01_01000: offset = 15'd276;
12'b00100_01_10000: offset = 15'd288;
12'b00100_10_00001: offset = 15'd300;
12'b00100_10_00010: offset = 15'd312;
12'b00100_10_00100: offset = 15'd324;
12'b00100_10_01000: offset = 15'd336;
12'b00100_10_10000: offset = 15'd348;
 
12'b01000_01_00001: offset = 15'd360;
12'b01000_01_00010: offset = 15'd372;
12'b01000_01_00100: offset = 15'd384;
12'b01000_01_01000: offset = 15'd396;
12'b01000_01_10000: offset = 15'd408;
12'b01000_10_00001: offset = 15'd420;
12'b01000_10_00010: offset = 15'd432;
12'b01000_10_00100: offset = 15'd444;
12'b01000_10_01000: offset = 15'd456;
12'b01000_10_10000: offset = 15'd468;
 
12'b10000_01_00001: offset = 15'd480;
12'b10000_01_00010: offset = 15'd492;
12'b10000_01_00100: offset = 15'd504;
12'b10000_01_01000: offset = 15'd516;
12'b10000_01_10000: offset = 15'd528;
12'b10000_10_00001: offset = 15'd540;
12'b10000_10_00010: offset = 15'd552;
12'b10000_10_00100: offset = 15'd564;
12'b10000_10_01000: offset = 15'd576;
12'b10000_10_10000: offset = 15'd588;
 
default: offset = 15'd0;
endcase;
end;
 
endmodule

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