OpenCores

trunk/CTOOL/hexdasm.exe Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/CTOOL/hexdasm.c =================================================================== --- trunk/CTOOL/hexdasm.c (nonexistent) +++ trunk/CTOOL/hexdasm.c (revision 7) @@ -0,0 +1,965 @@ +#include "stdlib.h" +#include "stdio.h" +#include "string.h" + +int func1(int in) +{ +const int table[]={1,2,4,8,16,32,64,128,256,512,1024,2048}; +int i =0; +if (in>=2048)return -1; +for(;;i++) +if ((in>table[i])&&(in=8) goto else + if(p!=NULL) + strcpy(__hex,p); + else + { + __hex[0]='0' ; + __hex[1]='x' ; + __hex[2]=hex[t/16]; + __hex[3]=hex[t%16]; + __hex[4]=0 ; + } + return __hex ; +} + +char _temp[100]; +//get file reg adderss from instruction! +char*gen_ins_fa(char*ins) +{//gen_ins_in( + strcpy(_temp,ins); + return bs2hs(&_temp[7]); +} + +//get bit data from instruction! +unsigned int gen_ins_bd(char*ins) +{ +//1111_1111_1111 + unsigned int t=0 ; + if(ins[5+1]=='1')t+=1 ; + if(ins[4+1]=='1')t+=2 ; + if(ins[3+1]=='1')t+=4 ; + return t ; +} + +//get goto(and call) address data from instruction! +unsigned int gen_ins_goto(char*ins) +{ +//000_111111001 + unsigned int t=0 ; + if(ins[11-0]=='1')t+=1; + if(ins[11-1]=='1')t+=2 ; + if(ins[11-2]=='1')t+=4; + if(ins[11-3]=='1')t+=8 ; + if(ins[11-4]=='1')t+=16;//1<<4 ; + if(ins[11-5]=='1')t+=32;//1<<5 ; + if(ins[11-6]=='1')t+=64;//1<<6 ; + if(ins[11-7]=='1')t+=128;//1<<7 ; + if(ins[11-8]=='1')t+=256;//1<<8 ; + return t ; +} + +//get instant data from instruction! +unsigned int gen_ins_in(char*ins) +{ + unsigned int t=0 ; + if(ins[11-0]=='1')t+=1; + if(ins[11-1]=='1')t+=2 ; + if(ins[11-2]=='1')t+=4;//1<<3 ; + if(ins[11-3]=='1')t+=8;//1<<4 ; + if(ins[11-4]=='1')t+=16;//1<<4 ; + if(ins[11-5]=='1')t+=32;//1<<5 ; + if(ins[11-6]=='1')t+=64;//1<<6 ; + if(ins[11-7]=='1')t+=128;//1<<7 ; + // if(ins[11-8]=='1')t+=1<<8 ; + return t ; +} + + +unsigned int inscmp(char*src,char*dst) +{ + unsigned int i ; + for(i=0;i<=9;i++) + { + if(src[i]=='X')continue ; + else if(src[i]!=dst[i])return 0 ; + } + return 1 ; +} + + +unsigned int str2u12(char*str) +{ + unsigned int ret=0 ; + unsigned int i ; + for(i=0;i<=11;++i) + { + if(str[i]==0)return ret ; + ret=ret*10+str[i]-'0' ; + } + return ret ; +} +/* +unsigned int getfno(char *ins,unsigned char start, +unsigned char len) +{ +unsigned int data = str2u12(ins); + unsigned int tmp1=0xffff<>start ; + unsigned int ret ; + tmp1=~tmp1 ; + ret=tmp1&tmp2 ; + ret=ret&0xffff ; + return ret ; + +unsigned int i,ret=0; +for(i=11-start;i%s<\n",ins);getchar(); +strcpy(ins_tsted[index],ins); +} + +int main(int argc,char*argv[]) +{ + + + int i ; + int addr_wdt,wd_no; + int max=0; + init1(); + + if(argc==2)strcpy(fin,argv[1]); + else + { + // printf("\nThe Synthetic PIC --- Intel HEX File to Altera memory file"); + // printf("\nUsage: hex2mif "); + // printf("\n"); + getchar(); + return 0 ; + printf("Input Hex file name:"); + scanf("%s",fin); + printf("Input Mif file name:"); + scanf("%s",mif_fn); + } + + + + /* Open input HEX file */ + fpi=fopen(argv[1],"r"); + if(!fpi) + { + printf("\nCan't open input file %s.\n",argv[1]); + return 1 ; + } + + /* Read in the HEX file */ + /* */ + /* !! Note, that things are a little strange for us, because the PIC is */ + /* a 12-bit instruction, addresses are 16-bit, and the hex format is */ + /* 8-bit oriented!! */ + /* */ + nMemoryCount=0 ; + while(!feof(fpi)) + { + /* Get one Intel HEX line */ + fgets(szLine,80,fpi); + if(strlen(szLine)>=10) + { + /* This is the PIC, with its 12-bit "words". We're interested in these */ + /* words and not the bytes. Read 4 hex digits at a time for each */ + /* address. */ + /* */ + sscanf(&szLine[1],"%2x%4x",&ndata_bytes,&start_address); + if(start_address>=0&&start_address<=20000&&ndata_bytes>0) + { + /* Suck up data bytes starting at 9th byte. */ + i=9 ; + + /* Words.. not bytes.. */ + ndata_words=ndata_bytes/2 ; + start_address=start_address/2 ; + + /* Spit out all the data that is supposed to be on this line. */ + for(address=start_address;address>8)&0x00ff)|((data<<8)&0xff00); + i+=4 ; + + /* Store in our memory buffer */ + Memory[nMemoryCount].nAddress=address ; + Memory[nMemoryCount].byData=data ; + nMemoryCount++; + } + } + } + } + fclose(fpi); + + /* + for(i=0;;++i) + { + mif_fn[i]=fin[i]; + if(mif_fn[i]=='.') + { + mif_fn[i+1]='m' ; + mif_fn[i+2]='i' ; + mif_fn[3+i]='f' ; + mif_fn[4+i]=0 ; + break ; + } + } + */ + + strcpy(mif_fn,"init_file.mif"); + + fpi=fopen(mif_fn,"w"); + if(NULL==fpi)return ; + /* Now output the Verilog $readmemh format! */ + /* */ + + /* Now output the Verilog $readmemh format! */ + /* */ + fprintf(fpi,"WIDTH=12;\nDEPTH=2048;\n\nADDRESS_RADIX=HEX;\nDATA_RADIX=HEX;\n\nCONTENT BEGIN\n"); + printf("WIDTH=8;\nDEPTH=256;\n\nADDRESS_RADIX=HEX;\nDATA_RADIX=HEX;\n\nCONTENT BEGIN\n"); + printf("Email:McuPro@163.com\n"); + + for(i=0;imax) max=Memory[i].nAddress; + // Memory[i].nAddressfprintf(fpi,"%04d:%s\n",Memory[i].nAddress,ins12tostr(Memory[i].byData)); + // sprintf(Memory[i].ins,"%s",ins12tostr(Memory[i].byData)); + //fprintf(fpi,"%04d : %s\n",Memory[i].nAddress,branch_ins(ins12tostr(Memory[i].byData))); + // fprintf(fpi,"mem[%d] = %d;\n",Memory[i].nAddress,Memory[i].byData); + // fprintf(fpi,"mem[%d] = %d;\n", + } + addr_wdt = func1(max); + fprintf(fpi,"`define ALT_MEM_WIDTHAD %d\n",addr_wdt); + fprintf(fpi,"`define ALT_MEM_NUMWORDS %d\n",1< 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading. +; This is necessary when C++ files have been compiled with aCC's -AA option. +; The default behavior is to use /usr/lib/libCsup.sl. +; UseCsupV2 = 1 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (log only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; Specify whether or not integer arrays will appear as memories. +; The default is 1 (display integer arrays as memories). +; ShowIntMem = 0 + +; Specify whether or not enumerated type arrays (other than std_logic-based) +; will appear as memories. +; The default is 1 (display enumerated type arrays as memories). +; ShowEnumMem = 0 + +; Specify whether or not arrays of 3 or more dimensions will appear as memories. +; The default is 1 (display 3D+ type arrays as memories). +; Show3DMem = 0 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Turn on/off PSL assertion pass enable. Default is off. +; AssertionPassEnable = 1 + +; Turn on/off PSL assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL assertion pass limit. Default is 1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = -1 + +; Set PSL assertion fail limit. Default is 1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = -1 + +; Turn on/off PSL assertion pass log. Default is on. +; AssertionPassLog = 0 + +; Turn on/off PSL assertion fail log. Default is on. +; AssertionFailLog = 0 + +; Set action type for PSL assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +[lmc] +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; ModelSim's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so + +; ModelSim's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; ModelSim's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so +[Project] +Project_Version = 5 +Project_DefaultLib = work +Project_SortMethod = unused +Project_Files_Count = 7 +Project_File_0 = D:/LWRISC/RTL/test.v +Project_File_P_0 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 0 vlog_noload 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_options {} vlog_upper 0 compile_to work compile_order 6 dont_compile 0 cover_stmt 1 +Project_File_1 = D:/LWRISC/SIM/clairisc_def.h +Project_File_P_1 = compile_order 2 last_compile 0 folder {Top Level} dont_compile 0 group_id 0 file_type SystemC ood 1 compile_to work +Project_File_2 = D:/LWRISC/RTL/risc_core.v +Project_File_P_2 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 0 vlog_noload 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_options {} vlog_upper 0 compile_to work compile_order 4 dont_compile 0 cover_stmt 1 +Project_File_3 = D:/LWRISC/RTL/memory.v +Project_File_P_3 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 0 vlog_noload 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_options {} vlog_upper 0 compile_to work compile_order 3 dont_compile 0 cover_stmt 1 +Project_File_4 = D:/LWRISC/SIM/rom_set.h +Project_File_P_4 = compile_order 1 last_compile 0 folder {Top Level} dont_compile 0 group_id 0 file_type SystemC ood 1 compile_to work +Project_File_5 = D:/LWRISC/RTL/sim_rom.v +Project_File_P_5 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 0 vlog_noload 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_options {} vlog_upper 0 compile_to work compile_order 5 dont_compile 0 cover_stmt 1 +Project_File_6 = D:/LWRISC/RTL/mem_man.v +Project_File_P_6 = vlog_protect 0 file_type Verilog group_id 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 0 vlog_noload 0 vlog_disableopt 0 vlog_hazard 0 vlog_showsource 0 ood 1 vlog_options {} vlog_upper 0 compile_to work compile_order 0 dont_compile 0 cover_stmt 1 +Project_Sim_Count = 0 +Project_Folder_Count = 0 +Echo_Compile_Output = 0 +Save_Compile_Report = 1 +VHDL_DoubleClick = Edit +VERILOG_DoubleClick = Edit +SYSTEMC_DoubleClick = Edit +TCL_DoubleClick = Edit +TEXT_DoubleClick = Edit +VHDL_CustomDoubleClick = +VERILOG_CustomDoubleClick = +SYSTEMC_CustomDoubleClick = +TCL_CustomDoubleClick = +TEXT_CustomDoubleClick = +ForceSoftPaths = 0 Index: trunk/SIM/transcript =================================================================== --- trunk/SIM/transcript (nonexistent) +++ trunk/SIM/transcript (revision 7) @@ -0,0 +1,11 @@ +# Reading C:/Modeltech_5.8e/tcl/vsim/pref.tcl +# // ModelSim SE 5.8e Aug 28 2004 +# // +# // Copyright Model Technology, a Mentor Graphics Corporation company, 2004 +# // All Rights Reserved. +# // UNPUBLISHED, LICENSED SOFTWARE. +# // CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE +# // PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS. +# // +# OpenFile "D:/LWRISC/SIM/SIM_ClaiRISC.mpf" +# Loading project SIM_ClaiRISC Index: trunk/SIM/SIM_ClaiRISC.cr.mti =================================================================== --- trunk/SIM/SIM_ClaiRISC.cr.mti (nonexistent) +++ trunk/SIM/SIM_ClaiRISC.cr.mti (revision 7) @@ -0,0 +1 @@ + Index: trunk/SIM/clairisc_def.h =================================================================== --- trunk/SIM/clairisc_def.h (nonexistent) +++ trunk/SIM/clairisc_def.h (revision 7) @@ -0,0 +1,69 @@ +`define SIM + + + + +`define MUXA_W 0 +`define MUXA_BD 1 + +`define MUXB_EK 0 +`define MUXB_REG 1 + +`define BRC_NOP 0 +`define BRC_ZERO 1 +`define BRC_NZERO 2 + +`define BG_ZERO 1 +`define BG_NZERO 2 +`define BG_IGN 0 +`define BG_NOP 0 + +`define PC_NOP 0 +`define PC_BRC 1 +`define PC_GOTO 2 +`define PC_CALL 2 +`define PC_INS 2 +`define PC_RET 3 +`define PC_NEXT 4 + +`define MUXB_IGN 1'BX +`define MUXA_IGN 1'BX + +`define R1_LEN 1 +`define R2_LEN 2 +`define R3_LEN 3 +`define R4_LEN 4 +`define R5_LEN 5 +`define R8_LEN 8 +`define R9_LEN 9 +`define R11_LEN 11 +`define R12_LEN 12 + +`define ALU_NOP 0 +`define ALU_ADD 1 +`define ALU_SUB 2 +`define ALU_AND 3 +`define ALU_OR 4 +`define ALU_XOR 5 +`define ALU_COM 6 +`define ALU_ROR 7 +`define ALU_ROL 8 +`define ALU_SWAP 9 +`define ALU_BSF 10 +`define ALU_BCF 11 +`define ALU_ZERO 12 +`define ALU_DEC 13 +`define ALU_INC 14 +`define ALU_PB 15 +`define ALU_PA 16 +`define ALU_BTFSC 17 +`define ALU_BTFSS 18 + +`define STK_PSH 1 +`define STK_POP 2 +`define STK_NOP 0 + +`define EN 1 +`define DIS 0 + +//`define TTE_MTHD1 Index: trunk/SIM/rom_set.h =================================================================== --- trunk/SIM/rom_set.h (nonexistent) +++ trunk/SIM/rom_set.h (revision 7) @@ -0,0 +1 @@ +`define ROM_TYPE rom128x12 Index: trunk/SYN/syntmp.msg =================================================================== Index: trunk/SYN/ClaiRISC_core.prd =================================================================== --- trunk/SYN/ClaiRISC_core.prd (nonexistent) +++ trunk/SYN/ClaiRISC_core.prd (revision 7) @@ -0,0 +1,13 @@ +#-- Synplicity, Inc. +#-- Version Synplify Pro 8.1 +#-- Project file D:\LWRISC\SYN\ClaiRISC_core.prd +#-- Written on Mon Mar 10 17:43:02 2008 + +# +### Watch Implementation type ### +# +watch_impl -all +# +### Watch Implementation properties ### +# +watch_prop -clear Index: trunk/SYN/ClaiRISC_core.prj =================================================================== --- trunk/SYN/ClaiRISC_core.prj (nonexistent) +++ trunk/SYN/ClaiRISC_core.prj (revision 7) @@ -0,0 +1,76 @@ +#-- Synplicity, Inc. +#-- Version Synplify Pro 8.1 +#-- Project file D:\LWRISC\SYN\ClaiRISC_core.prj +#-- Written on Mon Mar 10 17:43:02 2008 + + +#add_file options +add_file -verilog "../RTL/sim_rom.v" +add_file -verilog "../RTL/test.v" +add_file -_include "../RTL/clairisc_def.h" +add_file -verilog "../RTL/mem_man.v" +add_file -verilog "../RTL/memory.v" +add_file -verilog "../RTL/risc_core.v" +add_file -_include "../RTL/rom_set.h" +add_file -verilog "../RTL/altera/rom512x12.v" +add_file -verilog "../RTL/altera/rom1024x12.v" +add_file -verilog "../RTL/altera/rom2048x12.v" +add_file -verilog "../RTL/altera/ram128x8.v" +add_file -verilog "../RTL/altera/rom32x12.v" +add_file -verilog "../RTL/altera/rom64x12.v" +add_file -verilog "../RTL/altera/rom128x12.v" +add_file -verilog "../RTL/altera/rom256x12.v" + + +#implementation: "rev_1" +impl -add rev_1 + +#device options +set_option -technology CYCLONE +set_option -part EP1C6 +set_option -package QC240 +set_option -speed_grade -6 + +#compilation/mapping options +set_option -default_enum_encoding onehot +set_option -symbolic_fsm_compiler 1 +set_option -resource_sharing 1 +set_option -use_fsm_explorer 0 +set_option -top_module "ClaiRISC_core" + +#map options +set_option -frequency auto +set_option -run_prop_extract 0 +set_option -fanout_limit 30 +set_option -disable_io_insertion 0 +set_option -verification_mode 0 +set_option -pipe 1 +set_option -update_models_cp 0 +set_option -retiming 1 +set_option -fixgatedclocks 0 +set_option -no_sequential_opt 0 + +#simulation options +set_option -write_verilog 0 +set_option -write_vhdl 0 + +#VIF options +set_option -write_vif 1 + +#automatic place and route (vendor) options +set_option -write_apr_constraint 1 + +#set result format/file last +project -result_file "rev_1/ClaiRISC_core.vqm" + +# +#implementation attributes + +set_option -vlog_std v2001 +set_option -dup 0 +set_option -project_relative_includes 1 + +#par_1 attributes +set_option -job par_1 -add par +set_option -job par_1 -option run_backannotation 0 +impl -active "rev_1"

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