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  • This comparison shows the changes necessary to convert path 
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    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/trunk/src/pc.vhd
21,8 → 21,9
ELSIF clk'EVENT AND clk='1' THEN
CASE control IS
-- WHEN nop | neg_s | and_s | exor_s | or_s | sra_s | ror_s | add_s | addc_s | sta_1 => pc_int := pc_int + 1;
WHEN jmp_1 | jmpc_1 | jmpz_1 => pc_int := addr_in;
WHEN lda_addr_1 | ldb_addr_1 => null;
WHEN jmp_2 | jmpc_2 | jmpz_2 => pc_int := addr_in;
-- WHEN lda_addr_2 | ldb_addr_2 => null;
WHEN jnt => pc_int := std_logic_vector(unsigned(unsigned(pc_int) + to_unsigned(2,d_bus_width))); -- jump not taken
WHEN OTHERS => pc_int := std_logic_vector(unsigned(unsigned(pc_int) + to_unsigned(1,d_bus_width)));
END CASE;
END IF;
/trunk/src/processor_tb.vhd
51,7 → 51,7
END COMPONENT;
for all: cpu USE ENTITY work.processor_E(rtl_A);
--for all: cpu use entity work.processor_E(structure); --backannotation
--for all: cpu use entity work.processor_E(structure); --vasco's cpu processor.model.vhdl
 
BEGIN
 
/trunk/src/cpu_types.vhd
13,8 → 13,8
type rom_memory is array (integer range 0 to 2**a_bus_width-1) of d_bus;
type opcode is (nop, neg_s, and_s, exor_s, or_s, sra_s, ror_s, add_s, addc_s,
jmp_1, jmpc_1, jmpz_1, jmp_2, jmpc_2, jmpz_2, lda_const_1, lda_const_2,
ldb_const_1, ldb_const_2, lda_addr_1, lda_addr_2, lda_addr_3,
ldb_addr_1, ldb_addr_2, ldb_addr_3, sta_1, sta_2 );
ldb_const_1, ldb_const_2, lda_addr_1, lda_addr_2,
ldb_addr_1, ldb_addr_2, sta_1, sta_2, jnt );
 
PROCEDURE addc (SIGNAL a, b : IN STD_LOGIC_VECTOR(d_bus_width-1 DOWNTO 0);
SIGNAL cin : IN STD_LOGIC;
/trunk/src/reg.vhd
33,10 → 33,10
zero_out <= zero_in;
a_out <= result_in;
carry_out <= carry_in;
WHEN lda_const_2 | lda_addr_3 => zero_out <= zero_in;
WHEN lda_const_2 | lda_addr_2 => zero_out <= zero_in;
a_out <= result_in;
carry_out <= carry_in;
WHEN ldb_const_2 | ldb_addr_3 => zero_out <= zero_in;
WHEN ldb_const_2 | ldb_addr_2 => zero_out <= zero_in;
b_out <= result_in;
carry_out <= carry_in;
WHEN OTHERS => NULL;
/trunk/src/ram_control.vhd
47,19 → 47,17
 
rd_p: process(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN
IF control=lda_addr_1 OR control=ldb_addr_1 then
ce_nrd <= '0';
ELSE
ce_nrd <= '1';
END IF;
END IF;
IF control=lda_addr_1 OR control=ldb_addr_1 then
ce_nrd <= clk;
else
ce_nrd <= '1';
end if;
END process;
 
ram_data: process(clk)
begin
if clk'event and clk='1' then
if control=lda_addr_2 or control=ldb_addr_2 then
if control=lda_addr_1 or control=ldb_addr_1 then
ram_data_reg <= input_ram;
end if;
end if;
/trunk/src/control.vhd
7,7 → 7,7
port( clk, rst : in std_logic;
carry, zero : IN std_logic;
input : IN d_bus;
output : OUT opcode );
output, output_nxt : OUT opcode );
end control;
 
 
15,8 → 15,8
signal pr_state, nxt_state : opcode;
begin
 
output <= pr_state;
-- output <= nxt_state;
output <= pr_state;
output_nxt <= nxt_state;
main_s_p: process(clk)
begin
34,7 → 34,7
begin
 
case pr_state is
WHEN nop | neg_s | and_s | exor_s | or_s | sra_s | ror_s | add_s | addc_s | jmp_2 | jmpc_2 | jmpz_2 | lda_const_2 | ldb_const_2 | lda_addr_3 | ldb_addr_3 | sta_2 =>
WHEN nop | jnt | neg_s | and_s | exor_s | or_s | sra_s | ror_s | add_s | addc_s | jmp_2 | jmpc_2 | jmpz_2 | lda_const_2 | ldb_const_2 | lda_addr_2 | ldb_addr_2 | sta_2 =>
CASE input(input'HIGH DOWNTO 5) IS
WHEN "000" => nxt_state <= nop;
WHEN "001" =>
59,12 → 59,12
WHEN "0010" => IF carry='1' THEN
nxt_state <= jmpc_1;
ELSE
nxt_state <= nop;
nxt_state <= jnt;
END IF;
WHEN "0001" => IF zero='1' THEN
nxt_state <= jmpz_1;
ELSE
nxt_state <= nop;
nxt_state <= jnt;
END IF;
WHEN OTHERS => nxt_state <= nop;
END case;
89,9 → 89,7
WHEN lda_const_1 => nxt_state <= lda_const_2;
WHEN ldb_const_1 => nxt_state <= ldb_const_2;
WHEN lda_addr_1 => nxt_state <= lda_addr_2;
WHEN lda_addr_2 => nxt_state <= lda_addr_3;
WHEN ldb_addr_1 => nxt_state <= ldb_addr_2;
WHEN ldb_addr_2 => nxt_state <= ldb_addr_3;
WHEN sta_1 => nxt_state <= sta_2;
WHEN OTHERS => nxt_state <= nop;
END case;
/trunk/src/alu.vhd
83,7 → 83,7
ELSE
zero_out <= '0';
END IF;
WHEN nop | jmp_1 | jmp_2 | jmpc_1 | jmpc_2 | jmpz_1 | jmpz_2 | lda_const_1 | ldb_const_1 | lda_addr_1 | ldb_addr_1 |sta_1 | sta_2 =>
WHEN nop | jnt | jmp_1 | jmp_2 | jmpc_1 | jmpc_2 | jmpz_1 | jmpz_2 | lda_const_1 | ldb_const_1 | sta_1 | sta_2 =>
result_int := a;
carry_out <= carry;
zero_out <= zero;
94,7 → 94,7
ELSE
zero_out <= '0';
END IF;
WHEN lda_addr_2 | ldb_addr_2 => result_int := rom_data;
WHEN lda_addr_1 | ldb_addr_1 => result_int := rom_data;
carry_out <= carry;
IF result_int=ZERO_BUS THEN
zero_out <= '1';
101,7 → 101,7
ELSE
zero_out <= '0';
END IF;
WHEN lda_addr_3 | ldb_addr_3 => result_int := ram_data;
WHEN lda_addr_2 | ldb_addr_2 => result_int := ram_data;
carry_out <= carry;
IF result_int=ZERO_BUS THEN
zero_out <= '1';
/trunk/src/processor_E.vhd
26,7 → 26,7
ARCHITECTURE rtl_A OF processor_E IS
SIGNAL carry_reg_alu,zero_reg_alu,rst_int,carry_alu_reg,zero_alu_reg : STD_LOGIC; -- H-activ internal reset SIGNAL
signal ram_data_reg,a_reg_alu,b_reg_alu,result_alu_reg : d_bus;
SIGNAL control_int : opcode;
SIGNAL control_int, control_nxt_int : opcode;
BEGIN
rst_int <= (NOT nreset) OR (NOT nreset_int);
 
63,7 → 63,8
carry => carry_reg_alu,
zero => zero_reg_alu,
input => prog_data,
output => control_int );
output => control_int,
output_nxt => control_nxt_int );
pc_i: pc
PORT MAP (
70,7 → 71,7
clk => clk,
rst => rst_int,
addr_in => prog_data,
control => control_int,
control => control_nxt_int,
pc => prog_adr );
 
ram_control_i: ram_control
/trunk/src/components.vhd
10,7 → 10,7
component control is
port( clk,rst,carry,zero : in std_logic; input : IN d_bus;
output : out opcode );
output,output_nxt : out opcode );
end component;
component pc is

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