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URL https://opencores.org/ocsvn/mdct/mdct/trunk

Subversion Repositories mdct

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  • This comparison shows the changes necessary to convert path 
    /
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/trunk/source/DCT1D.vhd
102,8 → 102,7
type ISTATE_T is
(
IDLE_I,
ACQUIRE_1ROW,
WAITF
ACQUIRE_1ROW
);
type INPUT_DATA is array (N-1 downto 0) of SIGNED(IP_W downto 0);
173,45 → 172,47
when ACQUIRE_1ROW =>
if idv = '1' then
-- read next data from input FIFO
ready_reg <= '1';
if ready_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
if latch_done_reg = '0' then
if idv = '1' then
-- read next data from input FIFO
ready_reg <= '1';
inpcnt_reg <= inpcnt_reg + 1;
if inpcnt_reg = N-1 then
latch_done_reg <= '1';
ready_reg <= '0';
istate_reg <= WAITF;
if ready_reg = '1' then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= SIGNED('0' & dcti) - LEVEL_SHIFT;
inpcnt_reg <= inpcnt_reg + 1;
if inpcnt_reg = N-1 then
latch_done_reg <= '1';
ready_reg <= '0';
--istate_reg <= WAITF;
end if;
end if;
end if;
else
ready_reg <= '0';
end if;
-- failure to allocate any memory buffer
if reqwrfail = '1' then
-- restart allocation procedure
istate_reg <= IDLE_I;
ready_reg <= '0';
end if;
else
ready_reg <= '0';
end if;
 
-- failure to allocate any memory buffer
if reqwrfail = '1' then
-- restart allocation procedure
istate_reg <= IDLE_I;
ready_reg <= '0';
end if;
when WAITF =>
-- wait until DCT1D_PROC process 1D DCT computation
-- before latching new 8 input words
if state_reg = IDLE then
latch_done_reg <= '0';
if completed_reg = '1' then
istate_reg <= IDLE_I;
else
istate_reg <= ACQUIRE_1ROW;
end if;
end if;
-- wait until DCT1D_PROC process 1D DCT computation
-- before latching new 8 input words
if state_reg = IDLE then
latch_done_reg <= '0';
if completed_reg = '1' then
istate_reg <= IDLE_I;
else
istate_reg <= ACQUIRE_1ROW;
end if;
end if;
end if;
when others =>
istate_reg <= IDLE_I;
end case;
/trunk/source/testbench/wave.do
23,6 → 23,7
add wave -noupdate -format Logic /tb_mdct/u_inpimage/ready
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/istate_reg
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u_dct1d/state_reg
add wave -noupdate -format Logic /tb_mdct/u_mdct/u_dct1d/latch_done_reg
add wave -noupdate -format Logic /tb_mdct/u_mdct/odv1
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/dcto1
add wave -noupdate -format Literal -radix decimal /tb_mdct/u_mdct/u_dct1d/dcto
99,9 → 100,8
add wave -noupdate -format Literal /tb_mdct/u_inpimage/error_dcto1_matrix_s
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u1_rome0/addr
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u1_rome0/datao
add wave -noupdate -format Literal -radix hexadecimal /tb_mdct/u_mdct/u1_rome0/rom
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1522621 ps} 0}
WaveRestoreCursors {{Cursor 1} {1350000 ps} 0}
configure wave -namecolwidth 155
configure wave -valuecolwidth 40
configure wave -justifyvalue left
115,4 → 115,4
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {0 ps} {4352709 ps}
WaveRestoreZoom {619231 ps} {2120231 ps}
/trunk/source/DCT2D.VHD
102,9 → 102,7
type ISTATE2_T is
(
IDLE_I,
WAIT_RAM,
ACQUIRE_1ROW,
WAITF
ACQUIRE_1ROW
);
type input_data2 is array (N-1 downto 0) of SIGNED(RAMDATA_W downto 0);
168,52 → 166,50
----------------------
when ACQUIRE_1ROW =>
-- not starting from zero b/c of RAM 1T delay
if colram_reg /= 0 then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
end if;
if latch_done_reg = '0' then
-- not starting from zero b/c of RAM 1T delay
if colram_reg /= 0 then
-- right shift input data
latchbuf_reg(N-2 downto 0) <= latchbuf_reg(N-1 downto 1);
latchbuf_reg(N-1) <= RESIZE(SIGNED(ramdatao),RAMDATA_W+1);
end if;
colram_reg <= colram_reg + 1;
colram_reg <= colram_reg + 1;
-- not N-1
if colram_reg = N then
-- finished reading 64 point 1D DCT from RAM
if rowram_reg = N-1 then
-- release memory
releaserd_reg <= '1';
completed_reg <= '1';
end if;
colram_reg <= (others => '0');
rowram_reg <= rowram_reg + 1;
-- 8 point input latched
latch_done_reg <= '1';
--istate_reg <= WAITF;
end if;
-- not N-1
if colram_reg = N then
-- finished reading 64 point 1D DCT from RAM
if rowram_reg = N-1 then
-- release memory
releaserd_reg <= '1';
completed_reg <= '1';
-- failure to allocate memory buffer
-- should never happen?
if reqrdfail = '1' then
istate_reg <= IDLE_I;
end if;
else
releaserd_reg <= '0';
-- wait until DCT1D_PROC process 1D DCT computation
-- before latching new 8 input words
if state_reg = IDLE then
latch_done_reg <= '0';
if completed_reg = '1' then
completed_reg <= '0';
istate_reg <= IDLE_I;
else
istate_reg <= ACQUIRE_1ROW;
end if;
end if;
colram_reg <= (others => '0');
rowram_reg <= rowram_reg + 1;
-- 8 point input latched
latch_done_reg <= '1';
istate_reg <= WAITF;
end if;
-- failure to allocate memory buffer
-- should never happen?
if reqrdfail = '1' then
istate_reg <= IDLE_I;
end if;
----------------------
-- wait until latched input is processed by DCT
----------------------
when WAITF =>
releaserd_reg <= '0';
-- wait until DCT1D_PROC process 1D DCT computation
-- before latching new 8 input words
if state_reg = IDLE then
latch_done_reg <= '0';
if completed_reg = '1' then
completed_reg <= '0';
istate_reg <= IDLE_I;
else
istate_reg <= ACQUIRE_1ROW;
end if;
end if;
end if;
when others =>
istate_reg <= IDLE_I;
/trunk/DOC/mdct_spec.doc Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/mdct.mpf
225,7 → 225,7
UserTimeUnit = default
 
; Default run length
RunLength = 100 ns
RunLength = 0 ps
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
558,14 → 558,14
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144946089 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_12 = C:/elektronika/dct/mdct/source/testbench/MDCTTB_PKG.vhd
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143976585 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_13 = C:/elektronika/dct/mdct/source/MDCT.VHD
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_14 = C:/elektronika/dct/mdct/source/DCT1D.vhd
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_15 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_16 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_13 = C:/elektronika/dct/mdct/source/DCT1D.vhd
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1145135163 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_14 = C:/elektronika/dct/mdct/source/MDCT.VHD
Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1143931873 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_15 = C:/elektronika/dct/mdct/source/MDCT_PKG.vhd
Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder SOURCE last_compile 1144447956 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_File_16 = C:/elektronika/dct/mdct/source/testbench/INPIMAGE.VHD
Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 1 vhdl_enable0In 0 folder TESTBENCH last_compile 1143979283 vhdl_disableopt 0 vhdl_vital 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 1 vlog_vopt {} vhdl_0InOptions {} vhdl_warn3 1 vhdl_options {} vhdl_warn4 1 ood 1 vhdl_warn5 1 compile_to work compile_order 5 dont_compile 0 cover_nosub 0 vhdl_use93 93
Project_Sim_Count = 0
Project_Folder_Count = 4
Project_Folder_0 = TESTBENCH
603,6 → 603,6
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/MDCT_TB.DO 0 0} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/MDCT_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 1} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 0}
EditorState = {tabbed horizontal 1} {C:/elektronika/dct/MDCT/source/testbench/MDCT_TB.DO 0 0} {C:/elektronika/dct/MDCT/source/MDCT.VHD 0 0} {C:/elektronika/dct/MDCT/source/MDCT_PKG.vhd 0 1} {C:/elektronika/dct/MDCT/source/DCT1D.vhd 0 0} {C:/elektronika/dct/MDCT/source/DCT2D.VHD 0 0} {C:/elektronika/dct/MDCT/source/testbench/MDCTTB_PKG.vhd 0 0} {C:/elektronika/dct/MDCT/source/RAM.VHD 0 0}
Project_Major_Version = 6
Project_Minor_Version = 1

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