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Rev 6 → Rev 7

/pairing/trunk/testbench/test_f36m_cubic.v
1,5 → 1,5
`timescale 1ns / 1ns
`include "../verilog/inc.v"
`include "../rtl/inc.v"
 
module test_f36m_cubic;
 
/pairing/trunk/testbench/test_f3m_inv.v
9,6 → 9,7
 
// Outputs
wire [193:0] C;
wire done;
 
// Instantiate the Unit Under Test (UUT)
f3m_inv uut (
15,7 → 16,8
.A(A),
.clk(clk),
.reset(reset),
.C(C)
.C(C),
.done(done)
);
 
always #`CLOCK_PERIOD clk = ~clk;
33,9 → 35,8
A = 32'b10_01_01_10_01_00; // A = "x";
@(negedge clk); reset = 1;
@(negedge clk); reset = 0;
$display("Go!");
#(200*2*`CLOCK_PERIOD);
if (C != 192'h65450169824811252a919a8a02964184221a1562655252a9) begin $display("Error!"); $finish; end
if (C != 192'h65450169824811252a919a8a02964184221a1562655252a9) $display("Error!");
$display("Good!"); $finish;
end
/pairing/trunk/testbench/test_f33m_inv.v
0,0 → 1,45
`timescale 1ns / 1ps
`include "../rtl/inc.v"
 
module test_f33m_inv;
 
// Inputs
reg clk;
reg reset;
reg [`W3:0] a, w;
 
// Outputs
wire done;
wire [`W3:0] c;
 
// Instantiate the Unit Under Test (UUT)
f33m_inv uut (
.clk(clk),
.reset(reset),
.a(a),
.c(c),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a = {194'h210226252a484596150544098559162512219149194a91008,194'h12622041181115a64a84159a001a15a0a0609a642962068a5,194'h25429526606a8552a8622169050aa29921641120a05866014};
w = {194'h9a08022aa299850a48900010428a4aa66211109901a00a89,194'h95869a60454411009148081200aaaa121864220208592809,194'h564a6642212a164990212611055046496851a96918954695};
@ (negedge clk); reset = 1;
@ (posedge clk); reset = 0;
@ (posedge done); @(negedge clk);
if (c !== w) $display("E");
$finish;
end
always #5 clk = ~clk;
endmodule
 
/pairing/trunk/testbench/test_duursma_lee_algo.v
1,5 → 1,5
`timescale 1ns / 1ns
`include "../verilog/inc.v"
`include "../rtl/inc.v"
 
module test_duursma_lee_algo;
 
/pairing/trunk/testbench/test_f32m_mult.v
37,7 → 37,7
@ (negedge clk) reset = 1;
@ (negedge clk) reset = 0;
@ (posedge done);
if (c!=={194'h9594010a580186621a840406105460622891085122060a45,194'h59a1595621295a89260802a045194a96050a6202164000a9}) $display("E");
if (c!=={194'h9594010a580186621a840406105460622891085122060a45,194'h59a1595621295a89260802a045194a96050a6202164000a9}) $display("E1");
#100;
a={194'h8864990666a959a88500249a244495aaa26a2a0194082aa1,194'h2a9481526946468065456052045865262520a4a9520a5a665};
45,7 → 45,7
@ (negedge clk) reset = 1;
@ (negedge clk) reset = 0;
@ (posedge done);
if (c!=={194'h215608121442a91950aaa59514a9486258684486825840894,194'h284845aa0664918068988811691a290658228028985249a48}) $display("E");
if (c!=={194'h215608121442a91950aaa59514a9486258684486825840894,194'h284845aa0664918068988811691a290658228028985249a48}) $display("E2");
#100;
$finish;
/pairing/trunk/testbench/test_f33m_mult.v
1,5 → 1,5
`timescale 1ns / 1ns
`include "../verilog/inc.v"
`include "../rtl/inc.v"
 
module test_f33m_mult;
 
/pairing/trunk/testbench/test_f3m_mult3.v
0,0 → 1,67
`timescale 1ns / 1ps
`include "../rtl/inc.v"
 
module test_f3m_mult3;
 
// Inputs
reg clk;
reg reset;
reg [`WIDTH:0] a0,b0,a1,b1,a2,b2,w0,w1,w2;
 
// Outputs
wire [`WIDTH:0] c0,c1,c2;
wire done;
 
// Instantiate the Unit Under Test (UUT)
f3m_mult3 uut (
.clk(clk),
.reset(reset),
.a0(a0),
.b0(b0),
.c0(c0),
.a1(a1),
.b1(b1),
.c1(c1),
.a2(a2),
.b2(b2),
.c2(c2),
.done(done)
);
 
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
a0 = 0;
b0 = 0;
a1 = 0;
b1 = 0;
a2 = 0;
b2 = 0;
 
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
a0 = 194'h2581921511a6952a4244918a069446a520480660152916412;
a1 = 194'haa59080a98122082111a110a400642169102154006590a28;
a2 = 194'h90026a06416441992252a2820a2860269a094a0a06428285;
b0 = 194'h158a5419212805158a941010a495a80966995599a660686a5;
b1 = 194'h115a25602090915a9086a1165169041652888086051510024;
b2 = 194'h191a5669201405a8589951644158119264522a6496809952;
w0 = 194'h145a548a114016289482246816a449911942a088540160102;
w1 = 194'h220652040980466020556941115a5085a5904a60118605858;
w2 = 194'h280a8885992001a950615026585a5592096891a9954506155;
@ (negedge clk); reset = 1;
@ (negedge clk); reset = 0;
@ (posedge done);
#10;
if (c0 !== w0) $display("E");
if (c1 !== w1) $display("E");
if (c2 !== w2) $display("E");
$finish;
end
 
always #5 clk = ~clk;
endmodule
 
/pairing/trunk/rtl/f3m.v
154,6 → 154,60
end
endmodule
 
// c0 == a0*b0; c1 == a1*b1; c2 == a2*b2; all in GF(3^M)
module f3m_mult3(clk, reset,
a0, b0, c0,
a1, b1, c1,
a2, b2, c2,
done);
input clk, reset;
input [`WIDTH:0] a0, b0, a1, b1, a2, b2;
output reg [`WIDTH:0] c0, c1, c2;
output reg done;
reg [3:0] K;
reg mult_reset, delay1, delay2;
wire e1, e2, e3, mult_done, delay3, rst;
wire [`WIDTH:0] in1, in2, o;
assign rst = delay2;
assign {e1,e2,e3} = K[3:1];
 
f3m_mux3
ins9 (a0, e1, a1, e2, a2, e3, in1),
ins10 (b0, e1, b1, e2, b2, e3, in2);
f3m_mult
ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
func6
ins12 (clk, mult_done, delay3);
 
always @ (posedge clk)
begin
if (e1) c0 <= o;
if (e2) c1 <= o;
if (e3) c2 <= o;
end
always @ (posedge clk)
if (reset) K <= 4'b1000;
else if (delay3) K <= {1'b0,K[3:1]};
always @ (posedge clk)
begin
if (rst) mult_reset <= 1;
else if (mult_done) mult_reset <= 1;
else mult_reset <= 0;
end
 
always @ (posedge clk)
if (reset) done <= 0;
else if (K[0]) done <= 1;
always @ (posedge clk)
begin
delay2 <= delay1; delay1 <= reset;
end
endmodule
 
/* out == in^3 mod p(x) */
/* p(x) == x^97 + x^12 + 2 */
module f3m_cubic(input [193:0] in, output [193:0] out);
431,11 → 485,12
endmodule
 
// inversion in GF(3^m). C = A^(-1)
module f3m_inv(clk, reset, A, C);
module f3m_inv(clk, reset, A, C, done);
input [`WIDTH:0] A;
input clk;
input reset;
output reg [`WIDTH:0] C;
output reg done;
reg [`WIDTH+2:0] S, R, U, V, d, i;
wire [1:0] q;
445,17 → 500,19
V1, V2,
d1, d2,
i1;
wire done;
wire don;
 
assign d1 = {d[`WIDTH+1:0], 1'b1}; // d1 == d+1
assign d2 = {1'b0, d[`WIDTH+2:1]}; // d2 == d-1
assign i1 = {1'b0, i[`WIDTH+2:1]}; // i1 == i-1
assign done = (i[2:1] == 2'b01);
assign don = (i[2:1] == 2'b01);
always @ (posedge clk)
if (done)
always @ (posedge clk)
if (reset)
done <= 0;
else if (don)
begin
C <= U2[`WIDTH:0];
done <= 1; C <= U2[`WIDTH:0];
end
 
f3_mult
475,17 → 532,12
ins8(U, U3); // U3 = (U/x) mod p
always @ (posedge clk)
begin
if (reset)
i <= ~0;
else
begin
i <= i1;
end
end
always @ (posedge clk)
begin
if (reset)
begin
S<=`PX; R<=A; U<=1; V<=0; d<=0;
502,7 → 554,6
begin
S<=S2; V<=V1; U<=U3; d<=d2;
end
end
endmodule
 
// put func1~5 here for breaking circular dependency in "f3m", "fun"
/pairing/trunk/rtl/f32m.v
70,24 → 70,13
input [`W2:0] a, b;
output reg [`W2:0] c;
output reg done;
wire [`WIDTH:0] a0,a1,b0,b1,
v1,v2,v6,
c0,c1,
in1,in2,o;
reg [`WIDTH:0] v3,v4,v5;
reg [3:0] K;
wire load1, load2, load3, set1, set2, set3;
wire [`WIDTH:0] a0,a1,b0,b1,c0,c1,
v1,v2,v3,v4,v5,v6;
reg mult_reset;
wire mult_done;
reg delay1, delay2;
wire delay3;
wire rst;
wire mult_done, p;
assign rst = delay2;
assign {a1,a0} = a;
assign {b1,b0} = b;
assign {load1,load2,load3} = K[3:1];
assign {set1,set2,set3} = K[3:1];
 
f3m_add
ins1 (a0, a1, v1), // v1 == a0 + a1
96,50 → 85,24
f3m_sub
ins7 (v5, v6, c1), // c1 == v5 - v6 = (a0+a1) * (b0+b1) - (a0*b0 + a1*b1)
ins8 (v3, v4, c0); // c0 == a0*b0 - a1*b1
// only one $f3m_mult$ module doing three multiplication
// v3 == a0 * b0
// v4 == a1 * b1
// v5 == v1 * v2 = (a0+a1) * (b0+b1)
f3m_mux3
ins9 (a0, load1, a1, load2, v1, load3, in1),
ins10 (b0, load1, b1, load2, v2, load3, in2);
f3m_mult
ins11 (clk, mult_reset, in1, in2, o, mult_done); // o == in1 * in2 in GF(3^m)
f3m_mult3
ins9 (clk, mult_reset, a0, b0, v3, a1, b1, v4, v1, v2, v5, mult_done);
func6
ins12 (clk, mult_done, delay3);
ins10 (clk, mult_done, p);
always @ (posedge clk)
begin
if (set1) begin v3 <= o; end
if (set2) begin v4 <= o; end
if (set3) begin v5 <= o; end
end
always @ (posedge clk)
begin
if (reset) K <= 4'b1000;
else if (delay3) K <= {1'b0,K[3:1]}; // wait for Mr. Comb. Logic :)
end
always @ (posedge clk)
begin
if (rst) mult_reset <= 1; // wait for Mr. Comb. Logic :)
else if (mult_done) mult_reset <= 1;
else mult_reset <= 0;
end
mult_reset <= reset;
 
always @ (posedge clk)
if (reset)
done <= 0;
else if (K[0])
begin
done <= 1; c <= {c1, c0};
end
always @ (posedge clk)
begin
delay2 <= delay1; delay1 <= reset;
end
if (reset)
done <= 0;
else if (p)
begin
done <= 1; c <= {c1, c0};
end
endmodule
 
// C == A^3 in GF(3^{2m})
/pairing/trunk/rtl/f33m.v
123,5 → 123,78
endmodule
 
// c == a^{-1} in GF(3^{3*M})
 
 
module f33m_inv(clk, reset, a, c, done);
input clk, reset;
input [`W3:0] a;
output reg [`W3:0] c;
output reg done;
wire [`WIDTH:0] a0, a1, a2,
c0, c1, c2,
v0, v1, v2, v3, v4, v5,
v6, v7, v8, v9, v10, v11,
v12, v13, v14, v15, v16,
v17, nv2, nv11, nv14;
wire rst1, rst2, rst3, rst4,
done1, done2, done3, done4,
dummy;
reg [4:0] K;
assign {a2, a1, a0} = a;
assign rst1 = reset;
f3m_mult3
ins1 (clk, rst1,
a0, a0, v0, // v0 == a0^2
a1, a1, v1, // v1 == a1^2
a2, a2, v2, // v2 == a2^2
done1),
ins2 (clk, rst2,
v0, v3, v6, // v6 == (a0-a2)*(a0^2)
v1, v4, v7, // v7 == (a1-a0)*(a1^2)
v2, v5, v8, // v8 == (a0-a1+a2)*(a2^2)
done2),
ins3 (clk, rst1,
a0, a2, v11, // v11 == a0*a2
a0, a1, v12, // v12 == a0*a1
a1, a2, v13, // v13 == a1*a2
dummy),
ins4 (clk, rst4,
v10, v15, c0,
v10, v16, c1,
v10, v17, c2,
done4);
f3m_sub
ins5 (a0, a2, v3), // v3 == a0-a2
ins6 (a1, a0, v4), // v4 == a1-a0
ins7 (a2, v4, v5); // v5 == a2-v4 == a0-a1+a2
f3m_add3
ins8 (v6, v7, v8, v9), // v9 == v6+v7+v8
ins9 (v11, v1, v13, v14), // v14 == v11+v1+v13
ins10 (nv14, v0, v2, v15), // v15 == v0+v2-(v11+v1+v13)
ins11 (v1, nv2, nv11, v17); // v17 == a1^2-a0*a2-a2^2
f3m_neg
ins12 (v2, nv2), // nv2 == -v2
ins13 (v11, nv11), // nv11 == -v11
ins14 (v14, nv14); // nv14 == -v14 == -(v11+v1+v13)
f3m_sub
ins15 (v2, v12, v16); // v16 == a2^2-a0*a1
f3m_inv
ins16 (clk, rst3, v9, v10, done3); // v10 == v9^(-1)
func6
ins17 (clk, done1, rst2),
ins18 (clk, done2, rst3),
ins19 (clk, done3, rst4);
always @ (posedge clk)
if (reset) K <= 5'h10;
else if ((K[4]&rst2)|(K[3]&rst3)|(K[2]&rst4)|(K[1]&done4))
K <= K >> 1;
always @ (posedge clk)
if (reset) done <= 0;
else if (K[0])
begin
done <= 1; c <= {c2,c1,c0};
end
endmodule

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