URL
https://opencores.org/ocsvn/plasma/plasma/trunk
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- This comparison shows the changes necessary to convert path
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- from Rev 6 to Rev 7
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Rev 6 → Rev 7
/trunk/tools/test.c
18,6 → 18,8
-- convert will pull out the MIPS opcodes, and switch the executable |
-- to Big Endian, and convert absolute jumps into relative jumps, |
-- and save the opcodes in "code.txt". |
-- |
-- The interrupt vector is set to address 0x30. |
--------------------------------------------------------------------*/ |
#ifdef SIMULATE |
#undef putchar |
/trunk/tools/tracehex.c
0,0 → 1,161
/*********************************************************** |
| tracehex by Steve Rhoads 12/25/01 |
| This tool modifies trace files from the free VHDL simulator |
| http://www.symphonyeda.com/. |
| The binary numbers are converted to hex values. |
************************************************************/ |
#include <stdio.h> |
#include <stdlib.h> |
#include <string.h> |
#include <ctype.h> |
|
#define BUF_SIZE (1024*1024) |
|
char drop_char[10000]; |
|
int main(int argc, char *argv[]) |
{ |
FILE *file; |
char *buf,*ptr_in,line[1000],*ptr_out; |
int bytes,digits,value,isbinary,col,col_num,row,drop_cnt; |
int col_index,line_index,back_count,temp; |
(void)argc,argv; |
|
/* Reading trace.txt */ |
file=fopen("trace.txt","r"); |
if(file==NULL) { |
printf("Can't open file\n"); |
return -1; |
} |
buf=(char*)malloc(BUF_SIZE*2); |
ptr_out=buf+BUF_SIZE; |
bytes=fread(buf,1,BUF_SIZE-1,file); |
buf[bytes]=0; |
fclose(file); |
|
digits=0; |
value=0; |
isbinary=0; |
col=0; |
col_num=0; |
row=0; |
for(ptr_in=strstr(buf,"=");*ptr_in;++ptr_in) { |
++col; |
if(col<4||col==10||col==11||col==12) { |
drop_char[col]=1; |
continue; |
} |
|
/* convert binary number to hex */ |
if(isbinary&&(*ptr_in=='0'||*ptr_in=='1')) { |
value=value*2+*ptr_in-'0'; |
++digits; |
drop_char[col_num++]=1; |
} else if(isbinary&&*ptr_in=='Z') { |
value=1000; |
++digits; |
drop_char[col_num++]=1; |
} else if(isbinary&&*ptr_in=='U') { |
value=10000; |
++digits; |
drop_char[col_num++]=1; |
} else { |
/* end of binary number? */ |
if(digits) { |
drop_char[--col_num]=0; |
if(value<100) { |
/* test if digits not divisible by 4 */ |
if('0'<=ptr_out[-1]&&ptr_out[-1]<='9') { |
/* adjust previous digit */ |
value=value+((ptr_out[-1]-'0')<<digits); |
temp=(value>>4); |
ptr_out[-1]=temp<10?temp+'0':temp-10+'A'; |
} else if('A'<=ptr_out[-1]&&ptr_out[-1]<='F') { |
value=value+((ptr_out[-1]-'A'+10)<<digits); |
temp=(value>>4); |
ptr_out[-1]=temp<10?temp+'0':temp-10+'A'; |
} |
value&=0xf; |
*ptr_out++=value<10?value+'0':value-10+'A'; |
} else if(value<5000) { |
*ptr_out++='Z'; |
} else { |
*ptr_out++='U'; |
} |
} |
if(*ptr_in=='\n') { |
col=0; |
isbinary=0; |
++row; |
} |
if(isspace(*ptr_in)) { |
if(col>10) { |
isbinary=1; |
col_num=col; |
} |
} else { |
isbinary=0; |
} |
*ptr_out++=*ptr_in; |
digits=0; |
value=0; |
} |
|
/* convert every four binary digits to a hex digit */ |
if(digits==4) { |
drop_char[--col_num]=0; |
if(value<100) { |
*ptr_out++=value<10?value+'0':value-10+'A'; |
} else if(value<5000) { |
*ptr_out++='Z'; |
} else { |
*ptr_out++='U'; |
} |
digits=0; |
value=0; |
} |
} |
*ptr_out=0; |
|
/* now process the header */ |
file=fopen("trace2.txt","w"); |
col=0; |
line[0]=0; |
for(ptr_in=buf;*ptr_in;++ptr_in) { |
if(*ptr_in=='=') { |
break; |
} |
line[col++]=*ptr_in; |
if(*ptr_in=='\n') { |
line[col]=0; |
line_index=0; |
for(col_index=0;col_index<col;++col_index) { |
if(drop_char[col_index]) { |
back_count=0; |
while(line[line_index-back_count]!=' '&&back_count<10) { |
++back_count; |
} |
if(line[line_index-back_count-1]!=' ') { |
--back_count; |
} |
strcpy(line+line_index-back_count,line+line_index-back_count+1); |
} else { |
++line_index; |
} |
} |
fprintf(file,"%s",line); |
col=0; |
} |
} |
drop_cnt=0; |
for(col_index=13;col_index<sizeof(drop_char);++col_index) { |
if(drop_char[col_index]) { |
++drop_cnt; |
} |
} |
fprintf(file,"%s",buf+BUF_SIZE+drop_cnt); |
|
fclose(file); |
free(buf); |
return 0; |
} |
/trunk/tools/makefile
6,7 → 6,7
LINK=link /nologo /machine:MIPS /SUBSYSTEM:WINDOWSCE /entry:main \ |
/libpath:$(LIBPATH) /nodefaultlib /base:0x00000000 |
|
all: convert.exe mips.exe test.exe |
all: convert.exe mips.exe test.exe tracehex.exe |
|
convert.exe: convert.c |
cl convert.c |
15,7 → 15,7
cl mips.c |
|
test.exe: test.c |
$(CC) test.c -D SIMULATE |
$(CC) test.c -D SIMULATE -DMIPS |
$(LINK) /out:test.exe /map:test.map test.obj |
convert |
mips test.exe DD > test.txt |
22,4 → 22,7
mips test2.exe DD > test2.txt |
mips test2.exe |
|
tracehex.exe: tracehex.c |
cl tracehex.c |
|
|
/trunk/vhdl/mips_cpu.vhd
30,6 → 30,22
-- The CPU is implemented as a two stage pipeline with step #1 in the |
-- first stage and steps #2-8 occuring the second stage. |
-- |
-- Writing to memory takes four cycles to meet RAM address hold times. |
-- Addresses with a(31)='1' take two cycles (assumed to be clocked). |
-- Here are the signals for writing a charater to address 0xffff: |
-- |
-- mem_write |
-- interrupt mem_byte_sel |
-- reset mem_pause |
-- ns mem_address m_data_w m_data_r |
-- =========================================== |
-- 6700 0 0 0 000002A4 ZZZZZZZZ A0AE0000 0 0 ( fetch write opcode) |
-- 6800 0 0 0 000002B0 ZZZZZZZZ 0443FFF6 0 0 (1 fetch NEXT opcode) |
-- 6900 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (2 address hold) |
-- 7000 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 1 (3 write the low byte) |
-- 7100 0 0 1 0000FFFF 31313131 ZZZZZZZZ 0 0 (4 address hold) |
-- 7200 0 0 0 000002B4 ZZZZZZZZ 00441806 0 0 ( execute NEXT opcode) |
-- |
-- The CPU core was synthesized for 0.13 um line widths with an area |
-- of 0.2 millimeters squared. The maximum latency was less than 6 ns |
-- for a maximum clock speed of 150 MHz. |
46,14 → 62,9
mem_address : out std_logic_vector(31 downto 0); |
mem_data_w : out std_logic_vector(31 downto 0); |
mem_data_r : in std_logic_vector(31 downto 0); |
mem_sel : out std_logic_vector(3 downto 0); |
mem_byte_sel: out std_logic_vector(3 downto 0); |
mem_write : out std_logic; |
mem_pause : in std_logic; |
|
t_pc : out std_logic_vector(31 downto 0); |
t_opcode : out std_logic_vector(31 downto 0); |
t_r_dest : out std_logic_vector(31 downto 0) |
); |
mem_pause : in std_logic); |
end; --entity mips_cpu |
|
architecture logic of mips_cpu is |
95,6 → 106,7
component control |
port(opcode : in std_logic_vector(31 downto 0); |
intr_signal : in std_logic; |
pause_in : in std_logic; |
rs_index : out std_logic_vector(5 downto 0); |
rt_index : out std_logic_vector(5 downto 0); |
rd_index : out std_logic_vector(5 downto 0); |
189,6 → 201,7
signal nullify_op : std_logic; |
signal intr_enable : std_logic; |
signal intr_signal : std_logic; |
signal reset_reg : std_logic; |
begin --architecture |
|
pause <= pause_mult or pause_memory; |
197,11 → 210,12
'0'; |
c_bus <= c_alu or c_shift or c_mult; |
|
--synchronize interrupt pin |
intr_proc: process(clk, intr_in, intr_enable, pc_source, pc, pause) |
--synchronize reset and interrupt pins |
intr_proc: process(clk, reset_in, intr_in, intr_enable, pc_source, pc, pause) |
begin |
if rising_edge(clk) then |
--don't try to interrupt an multi-cycle instruction |
reset_reg <= reset_in; |
--don't try to interrupt a multi-cycle instruction |
if intr_in = '1' and intr_enable = '1' and |
pc_source = from_inc4 and |
pc(2) = '0' and |
216,7 → 230,7
|
u1: pc_next PORT MAP ( |
clk => clk, |
reset_in => reset_in, |
reset_in => reset_reg, |
take_branch => take_branch, |
pause_in => pause, |
pc_new => c_alu(31 downto 2), |
227,7 → 241,7
|
u2: mem_ctrl PORT MAP ( |
clk => clk, |
reset_in => reset_in, |
reset_in => reset_reg, |
pause_in => pause, |
nullify_op => nullify_op, |
address_pc => pc, |
242,7 → 256,7
mem_address => mem_address, |
mem_data_w => mem_data_w, |
mem_data_r => mem_data_r, |
mem_byte_sel => mem_sel, |
mem_byte_sel => mem_byte_sel, |
mem_write => mem_write, |
mem_pause => mem_pause); |
|
249,6 → 263,7
u3: control PORT MAP ( |
opcode => opcode, |
intr_signal => intr_signal, |
pause_in => pause, |
rs_index => rs_index, |
rt_index => rt_index, |
rd_index => rd_index, |
313,9 → 328,5
c_mult => c_mult, |
pause_out => pause_mult); |
|
t_pc <= pc; |
t_opcode <= opcode; |
t_r_dest <= reg_dest; |
|
end; --architecture logic |
|
/trunk/vhdl/ram.vhd
58,9 → 58,10
storage(index) := data; |
index := index + 1; |
end loop; |
assert false report "done reading code" severity note; |
--assert false report "done reading code" severity note; |
|
wait on clk; --wait for line noise to go away |
wait on mem_address; |
|
loop |
wait on clk, mem_address, mem_write; |
67,7 → 68,7
|
--support putchar() when writing to address 0xffff |
if rising_edge(clk) then |
if mem_write = '1' and mem_address = ONES(15 downto 0) then |
if mem_byte_sel(0) = '1' and mem_address = ONES(15 downto 0) then |
index := conv_integer(mem_data_w(6 downto 0)); |
if index /= 10 then |
c := character'val(index); |
86,6 → 87,8
|
if mem_write = '0' then |
mem_data_r <= data; |
else |
mem_data_r <= HIGH_Z; --ZERO; |
end if; |
if mem_byte_sel(0) = '1' then |
data(7 downto 0) := mem_data_w(7 downto 0); |
/trunk/vhdl/control.vhd
23,6 → 23,7
entity control is |
port(opcode : in std_logic_vector(31 downto 0); |
intr_signal : in std_logic; |
pause_in : in std_logic; |
rs_index : out std_logic_vector(5 downto 0); |
rt_index : out std_logic_vector(5 downto 0); |
rd_index : out std_logic_vector(5 downto 0); |
408,6 → 409,10
rd := "000000"; |
end if; |
|
if pause_in = '1' then |
rd := "000000"; |
end if; |
|
if intr_signal = '1' then |
rs := "111111"; --interrupt vector |
rt := "000000"; |
/trunk/vhdl/alu.vhd
95,11 → 95,7
c := ZERO; |
end case; |
|
-- if alu_function = alu_nothing then |
-- c_alu <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; |
-- else |
c_alu <= c; |
-- end if; |
c_alu <= c; |
end process; |
|
end; --architecture logic |
/trunk/vhdl/mult.vhd
9,6 → 9,8
-- DESCRIPTION: |
-- Implements the multiplication and division unit. |
-- Normally takes 32 clock cycles. |
-- if b(31 downto 16) = ZERO(31 downto 16) then mult in 16 cycles. |
-- if b(31 downto 8) = ZERO(31 downto 8) then mult in 8 cycles. |
--------------------------------------------------------------------- |
library ieee; |
use ieee.std_logic_1164.all; |
104,7 → 106,7
end if; |
b_temp(30 downto 0) := ZERO(30 downto 0); |
else --multiply |
b_temp := zero & b; |
b_temp := ZERO & b; |
end if; |
elsif do_write = '1' then |
if do_hi = '0' then |
148,10 → 150,15
end if; |
b_temp(30 downto 0) := reg_b(31 downto 1); |
if count_reg = "010000" and --early stop |
reg_b(15 downto 0) = zero(15 downto 0) then |
reg_b(15 downto 0) = ZERO(15 downto 0) then |
count_temp := "111111"; |
b_temp(31 downto 0) := reg_b(47 downto 16); |
end if; |
if count_reg = "001000" and --early stop |
reg_b(23 downto 0) = ZERO(23 downto 0) then |
count_temp := "111111"; |
b_temp(31 downto 0) := reg_b(55 downto 24); |
end if; |
end if; |
end if; |
|
174,7 → 181,6
elsif mult_func = mult_read_hi then |
c_mult <= reg_b(63 downto 32); |
else |
-- c_mult <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; |
c_mult <= ZERO; |
end if; |
|
/trunk/vhdl/bus_mux.vhd
87,7 → 87,7
cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux) |
begin |
case c_mux is |
when c_from_alu | c_from_shift | c_from_mult => |
when c_from_alu => -- | c_from_shift | c_from_mult => |
reg_dest_out <= c_bus; |
when c_from_memory => |
reg_dest_out <= c_memory; |
/trunk/vhdl/mem_ctrl.vhd
9,6 → 9,7
-- DESCRIPTION: |
-- Memory controller for the MIPS CPU. |
-- Supports Big or Little Endian mode. |
-- Four cycles for a write unless a(31)='1' then two cycles. |
-- This entity could implement interfaces to: |
-- Data cache |
-- Address cache |
46,32 → 47,38
constant little_endian : std_logic_vector(1 downto 0) := "00"; |
signal opcode_reg : std_logic_vector(31 downto 0); |
signal next_opcode_reg : std_logic_vector(31 downto 0); |
signal setup_done : std_logic; |
|
subtype setup_state_type is std_logic_vector(1 downto 0); |
signal setup_state : setup_state_type; |
constant STATE_FETCH : setup_state_type := "00"; |
constant STATE_ADDR : setup_state_type := "01"; |
constant STATE_WRITE : setup_state_type := "10"; |
constant STATE_PAUSE : setup_state_type := "11"; |
begin |
|
mem_proc: process(clk, reset_in, pause_in, nullify_op, |
address_pc, address_data, mem_source, data_write, |
mem_data_r, mem_pause, |
opcode_reg, next_opcode_reg, setup_done) |
opcode_reg, next_opcode_reg, setup_state) |
variable data, datab : std_logic_vector(31 downto 0); |
variable opcode_temp : std_logic_vector(31 downto 0); |
variable byte_sel_temp : std_logic_vector(3 downto 0); |
variable write_temp : std_logic; |
variable setup_done_var : std_logic; |
variable opcode_next : std_logic_vector(31 downto 0); |
variable byte_sel_next : std_logic_vector(3 downto 0); |
variable write_next : std_logic; |
variable setup_state_next : setup_state_type; |
variable pause : std_logic; |
variable address_temp : std_logic_vector(31 downto 0); |
variable address_next : std_logic_vector(31 downto 0); |
variable bits : std_logic_vector(1 downto 0); |
variable mem_data_w_v : std_logic_vector(31 downto 0); |
begin |
byte_sel_temp := "0000"; |
write_temp := '0'; |
byte_sel_next := "0000"; |
write_next := '0'; |
pause := '0'; |
setup_done_var := setup_done; |
setup_state_next := setup_state; |
|
address_temp := address_pc; |
address_next := address_pc; |
data := mem_data_r; |
datab := ZERO; |
mem_data_w_v := ZERO; --"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; |
mem_data_w_v := ZERO; |
|
case mem_source is |
when mem_read32 => |
101,75 → 108,100
datab(31 downto 8) := ONES(31 downto 8); |
end if; |
when mem_write32 => |
write_temp := '1'; |
write_next := '1'; |
mem_data_w_v := data_write; |
byte_sel_temp := "1111"; |
byte_sel_next := "1111"; |
when mem_write16 => |
write_temp := '1'; |
write_next := '1'; |
mem_data_w_v := data_write(15 downto 0) & data_write(15 downto 0); |
if address_data(1) = little_endian(1) then |
byte_sel_temp := "1100"; |
byte_sel_next := "1100"; |
else |
byte_sel_temp := "0011"; |
byte_sel_next := "0011"; |
end if; |
when mem_write8 => |
write_temp := '1'; |
write_next := '1'; |
mem_data_w_v := data_write(7 downto 0) & data_write(7 downto 0) & |
data_write(7 downto 0) & data_write(7 downto 0); |
bits := address_data(1 downto 0) xor little_endian; |
case bits is |
when "00" => |
byte_sel_temp := "1000"; |
byte_sel_next := "1000"; |
when "01" => |
byte_sel_temp := "0100"; |
byte_sel_next := "0100"; |
when "10" => |
byte_sel_temp := "0010"; |
byte_sel_next := "0010"; |
when others => |
byte_sel_temp := "0001"; |
byte_sel_next := "0001"; |
end case; |
when others => |
end case; |
|
opcode_temp := opcode_reg; |
opcode_next := opcode_reg; |
if mem_source = mem_none then |
setup_done_var := '0'; |
setup_state_next := STATE_FETCH; |
if pause_in = '0' and mem_pause = '0' then |
opcode_temp := data; |
opcode_next := data; |
end if; |
else |
pause := not setup_done; |
setup_done_var := '1'; |
if setup_done = '1' then |
address_temp := address_data; |
if setup_state = STATE_FETCH then |
pause := '1'; |
byte_sel_next := "0000"; |
setup_state_next := STATE_ADDR; |
elsif setup_state = STATE_ADDR then |
address_next := address_data; |
if write_next ='1' and address_data(31) = '0' then |
pause := '1'; |
byte_sel_next := "0000"; |
setup_state_next := STATE_WRITE; --4 cycle access |
else |
if mem_pause = '0' then |
opcode_next := next_opcode_reg; |
setup_state_next := STATE_FETCH; --2 cycle access |
end if; |
end if; |
elsif setup_state = STATE_WRITE then |
pause := '1'; |
address_next := address_data; |
if mem_pause = '0' then |
opcode_temp := next_opcode_reg; |
setup_done_var := '0'; |
setup_state_next := STATE_PAUSE; |
end if; |
elsif setup_state = STATE_PAUSE then |
address_next := address_data; |
byte_sel_next := "0000"; |
opcode_next := next_opcode_reg; |
setup_state_next := STATE_FETCH; |
end if; |
end if; |
|
if nullify_op = '1' then |
opcode_temp := ZERO; --NOP |
opcode_next := ZERO; --NOP |
end if; |
if reset_in = '1' then |
setup_done_var := '0'; |
opcode_temp := ZERO; |
setup_state_next := STATE_FETCH; |
opcode_next := ZERO; |
end if; |
|
if rising_edge(clk) then |
opcode_reg <= opcode_temp; |
if setup_done = '0' then |
opcode_reg <= opcode_next; |
if setup_state = STATE_FETCH then |
next_opcode_reg <= data; |
end if; |
setup_done <= setup_done_var; |
setup_state <= setup_state_next; |
end if; |
|
opcode_out <= opcode_reg; |
data_read <= datab; |
pause_out <= mem_pause or pause; |
mem_byte_sel <= byte_sel_temp; |
mem_address <= address_temp; |
mem_write <= write_temp and setup_done; |
mem_data_w <= mem_data_w_v; |
mem_byte_sel <= byte_sel_next; |
mem_address <= address_next; |
if write_next = '1' and setup_state /= STATE_FETCH then |
mem_write <= '1'; |
mem_data_w <= mem_data_w_v; |
else |
mem_write <= '0'; |
mem_data_w <= HIGH_Z; --ZERO; |
end if; |
|
end process; --data_proc |
|
/trunk/vhdl/tbench.vhd
14,9 → 14,7
use work.mips_pack.all; |
|
entity tbench is |
port(clk_out : out std_logic; |
pc : out std_logic_vector(31 downto 0) |
); |
port(clk_out : out std_logic); |
end; --entity tbench |
|
architecture logic of tbench is |
29,14 → 27,9
mem_address : out std_logic_vector(31 downto 0); |
mem_data_w : out std_logic_vector(31 downto 0); |
mem_data_r : in std_logic_vector(31 downto 0); |
mem_sel : out std_logic_vector(3 downto 0); |
mem_byte_sel: out std_logic_vector(3 downto 0); |
mem_write : out std_logic; |
mem_pause : in std_logic; |
|
t_pc : out std_logic_vector(31 downto 0); |
t_opcode : out std_logic_vector(31 downto 0); |
t_r_dest : out std_logic_vector(31 downto 0) |
); |
mem_pause : in std_logic); |
end component; |
|
component ram |
49,26 → 42,22
mem_data_r : out std_logic_vector(31 downto 0)); |
end component; |
|
signal clk : std_logic := '0'; |
signal reset : std_logic := '1'; --, '0' after 100 ns; |
signal clk : std_logic := '1'; |
signal reset : std_logic := '1'; |
signal interrupt : std_logic := '0'; |
signal mem_sel : std_logic_vector(3 downto 0); |
signal mem_write : std_logic; |
signal mem_address : std_logic_vector(31 downto 0); |
signal mem_data_w : std_logic_vector(31 downto 0); |
signal mem_data_r : std_logic_vector(31 downto 0); |
signal mem_pause : std_logic; |
signal t_pc : std_logic_vector(31 downto 0); |
signal t_opcode : std_logic_vector(31 downto 0); |
signal t_r_dest : std_logic_vector(31 downto 0); |
signal mem_byte_sel: std_logic_vector(3 downto 0); |
begin --architecture |
clk <= not clk after 50 ns; |
reset <= '0' after 100 ns; |
reset <= '0' after 320 ns; |
mem_pause <= '0'; |
|
--Uncomment the line below to test interrupts |
-- interrupt <= '1' after 10000 ns when interrupt = '0' else '0' after 600 ns; |
-- interrupt <= '1' after 10 us when interrupt = '0' else '0' after 600 ns; |
|
u1: mips_cpu PORT MAP ( |
clk => clk, |
78,14 → 67,10
mem_address => mem_address, |
mem_data_w => mem_data_w, |
mem_data_r => mem_data_r, |
mem_sel => mem_byte_sel, |
mem_byte_sel => mem_byte_sel, |
mem_write => mem_write, |
mem_pause => mem_pause, |
mem_pause => mem_pause); |
|
t_pc => t_pc, |
t_opcode => t_opcode, |
t_r_dest => t_r_dest); |
|
u2: ram generic map ("code.txt") |
PORT MAP ( |
clk => clk, |
96,7 → 81,6
mem_data_r => mem_data_r); |
|
clk_out <= clk; |
pc <= t_pc; |
|
end; --architecture logic |
|
/trunk/vhdl/shifter.vhd
96,7 → 96,6
end if; |
end if; --shift_dir |
if shift_func = shift_nothing then |
-- c_shift <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; |
c_shift <= ZERO; |
else |
c_shift <= shift16; |
/trunk/vhdl/mips_pack.vhd
17,6 → 17,9
"00000000000000000000000000000000"; |
constant ONES : std_logic_vector(31 downto 0) := |
"11111111111111111111111111111111"; |
--make HIGH_Z equal to ZERO if compiler complains |
constant HIGH_Z : std_logic_vector(31 downto 0) := |
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; |
|
-- type alu_function_type is (alu_nothing, alu_add, alu_subtract, |
-- alu_less_than, alu_less_than_signed, alu_equal, alu_not_equal, |
79,16 → 82,16
-- type c_source_type is (from_null, from_alu, from_shift, |
-- from_mult, from_memory, from_pc, from_imm_shift16, |
-- from_reg_source_nez, from_reg_source_eqz); |
subtype c_source_type is std_logic_vector(3 downto 0); |
constant c_from_alu : c_source_type := "0000"; |
constant c_from_shift : c_source_type := "0001"; |
constant c_from_mult : c_source_type := "0010"; |
constant c_from_memory : c_source_type := "0011"; |
constant c_from_pc : c_source_type := "0100"; |
constant c_from_pc_plus4 : c_source_type := "0101"; |
constant c_from_imm_shift16: c_source_type := "0110"; |
constant c_from_reg_sourcen: c_source_type := "0111"; |
constant c_from_null : c_source_type := "1000"; |
subtype c_source_type is std_logic_vector(2 downto 0); |
constant c_from_null : c_source_type := "000"; |
constant c_from_alu : c_source_type := "001"; |
constant c_from_shift : c_source_type := "001"; --same as alu |
constant c_from_mult : c_source_type := "001"; --same as alu |
constant c_from_memory : c_source_type := "010"; |
constant c_from_pc : c_source_type := "011"; |
constant c_from_pc_plus4 : c_source_type := "100"; |
constant c_from_imm_shift16: c_source_type := "101"; |
constant c_from_reg_sourcen: c_source_type := "110"; |
|
-- type pc_source_type is (from_inc4, from_inc8, from_reg_source, |
-- from_opcode25_0, from_branch, from_lbranch); |
/trunk/vhdl/simili.cmd
0,0 → 1,4
add list /u1/pc /u1/opcode /u1/* |
#add list /tbench/* |
SetListStyle nodelta collapse |
SetListInterval 0us 1ms |
trunk/vhdl/simili.cmd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/vhdl/makefile
===================================================================
--- trunk/vhdl/makefile (revision 6)
+++ trunk/vhdl/makefile (revision 7)
@@ -1,52 +1,74 @@
-VHD = mips_pack alu bus_mux control mem_ctrl mult pc_next reg_bank shifter \
- mips_cpu
+#Makefile for MIPS-lite
-all: work/tbench/_primary.dat
+#for ModelSim
+#WORK_DIR = work
+#DEP_FILE = _primary.dat
+#COMPILE = vcom -check_synthesis
-work/mips_pack/_primary.dat: mips_pack.vhd
- vcom -check_synthesis mips_pack.vhd
+#for FREE VHDL simulator http://www.symphonyeda.com
+WORK_DIR = work.sym
+DEP_FILE = prim.dep
+COMPILE = vhdlp -s
-work/alu/_primary.dat: mips_pack.vhd alu.vhd
- vcom -check_synthesis alu.vhd
+all: $(WORK_DIR)/tbench/$(DEP_FILE)
-work/bus_mux/_primary.dat: mips_pack.vhd bus_mux.vhd
- vcom -check_synthesis bus_mux.vhd
+run: all
+ -@echo off > output.txt
+ -@echo on
+ -@start tail -f output.txt
+ vhdle -t 10ms tbench
+ -@diff output.txt ../tools/output.txt
-work/control/_primary.dat: mips_pack.vhd control.vhd
- vcom -check_synthesis control.vhd
+simulate: all
+ vhdle -s -t 10us tbench -do simili.cmd -list trace.txt
+ -@..\tools\tracehex
+ -@ed trace2.txt
-work/mem_ctrl/_primary.dat: mips_pack.vhd mem_ctrl.vhd
- vcom -check_synthesis mem_ctrl.vhd
+$(WORK_DIR)/mips_pack/$(DEP_FILE): mips_pack.vhd
+ $(COMPILE) mips_pack.vhd
-work/mult/_primary.dat: mips_pack.vhd mult.vhd
- vcom -check_synthesis mult.vhd
+$(WORK_DIR)/alu/$(DEP_FILE): mips_pack.vhd alu.vhd
+ $(COMPILE) alu.vhd
-work/pc_next/_primary.dat: mips_pack.vhd pc_next.vhd
- vcom -check_synthesis pc_next.vhd
+$(WORK_DIR)/bus_mux/$(DEP_FILE): mips_pack.vhd bus_mux.vhd
+ $(COMPILE) bus_mux.vhd
-work/reg_bank/_primary.dat: mips_pack.vhd reg_bank.vhd
- vcom -check_synthesis reg_bank.vhd
+$(WORK_DIR)/control/$(DEP_FILE): mips_pack.vhd control.vhd
+ $(COMPILE) control.vhd
-work/shifter/_primary.dat: mips_pack.vhd shifter.vhd
- vcom -check_synthesis shifter.vhd
+$(WORK_DIR)/mem_ctrl/$(DEP_FILE): mips_pack.vhd mem_ctrl.vhd
+ $(COMPILE) mem_ctrl.vhd
-work/mips_cpu/_primary.dat: mips_cpu.vhd \
- work/mips_pack/_primary.dat \
- work/alu/_primary.dat \
- work/bus_mux/_primary.dat \
- work/control/_primary.dat \
- work/mem_ctrl/_primary.dat \
- work/mult/_primary.dat \
- work/pc_next/_primary.dat \
- work/reg_bank/_primary.dat \
- work/shifter/_primary.dat
- vcom -check_synthesis mips_cpu.vhd
+$(WORK_DIR)/mult/$(DEP_FILE): mips_pack.vhd mult.vhd
+ $(COMPILE) mult.vhd
-work/ram/_primary.dat: ram.vhd
- vcom -explicit ram.vhd
+$(WORK_DIR)/pc_next/$(DEP_FILE): mips_pack.vhd pc_next.vhd
+ $(COMPILE) pc_next.vhd
-work/tbench/_primary.dat: tbench.vhd \
- work/mips_cpu/_primary.dat \
- work/ram/_primary.dat
- vcom tbench.vhd
+$(WORK_DIR)/reg_bank/$(DEP_FILE): mips_pack.vhd reg_bank.vhd
+ $(COMPILE) reg_bank.vhd
+$(WORK_DIR)/shifter/$(DEP_FILE): mips_pack.vhd shifter.vhd
+ $(COMPILE) shifter.vhd
+
+$(WORK_DIR)/mips_cpu/$(DEP_FILE): mips_cpu.vhd \
+ $(WORK_DIR)/mips_pack/$(DEP_FILE) \
+ $(WORK_DIR)/alu/$(DEP_FILE) \
+ $(WORK_DIR)/bus_mux/$(DEP_FILE) \
+ $(WORK_DIR)/control/$(DEP_FILE) \
+ $(WORK_DIR)/mem_ctrl/$(DEP_FILE) \
+ $(WORK_DIR)/mult/$(DEP_FILE) \
+ $(WORK_DIR)/pc_next/$(DEP_FILE) \
+ $(WORK_DIR)/reg_bank/$(DEP_FILE) \
+ $(WORK_DIR)/shifter/$(DEP_FILE)
+ $(COMPILE) mips_cpu.vhd
+
+$(WORK_DIR)/ram/$(DEP_FILE): mips_pack.vhd ram.vhd
+ $(COMPILE) -87 ram.vhd
+
+$(WORK_DIR)/tbench/$(DEP_FILE): mips_pack.vhd tbench.vhd \
+ $(WORK_DIR)/mips_pack/$(DEP_FILE) \
+ $(WORK_DIR)/mips_cpu/$(DEP_FILE) \
+ $(WORK_DIR)/ram/$(DEP_FILE)
+ $(COMPILE) tbench.vhd
+