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URL https://opencores.org/ocsvn/rs232_interface/rs232_interface/trunk

Subversion Repositories rs232_interface

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    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/rs232_interface/trunk/uart.vhd
20,6 → 20,8
-- External Interface
rx : in std_logic; -- RS232 received serial data
tx : out std_logic; -- RS232 transmitted serial data
-- RS232/UART Configuration
par_en : in std_logic; -- Parity bit enable
-- uPC Interface
tx_req : in std_logic; -- Request SEND of data
tx_end : out std_logic; -- Data SENDED
32,22 → 34,28
architecture Behavioral of uart is
 
-- Constants
constant uart_idle : std_logic := '1';
constant uart_start : std_logic := '0';
constant UART_IDLE : std_logic := '1';
constant UART_START : std_logic := '0';
constant PARITY_EN : std_logic := '1';
constant RST_LVL : std_logic := '1';
 
-- Types
type state is (idle,data,stop1,stop2);
type state is (idle,data,parity,stop1,stop2); -- Stop1 and Stop2 are inter frame gap
 
-- Signals
signal rx_fsm : state;
signal tx_fsm : state;
signal clock_en : std_logic;
signal rx_fsm : state; -- Control of reception
signal tx_fsm : state; -- Control of transmission
signal clock_en : std_logic; -- Internal clock enable
 
-- Data Temp
signal data_cnt_tx : std_logic_vector(2 downto 0) := "000";
signal data_cnt_rx : std_logic_vector(2 downto 0);
-- RX Data Temp
signal rx_par_bit : std_logic;
signal rx_data_tmp : std_logic_vector(7 downto 0);
signal rx_data_cnt : std_logic_vector(2 downto 0);
 
-- TX Data Temp
signal tx_par_bit : std_logic;
signal tx_data_tmp : std_logic_vector(7 downto 0);
signal tx_data_cnt : std_logic_vector(2 downto 0);
 
begin
 
64,7 → 72,7
counter := counter + 1;
end if;
-- Reset condition
if rst = '1' then
if rst = RST_LVL then
counter := 0;
end if;
end if;
77,7 → 85,7
if clock_en = '1' then
-- Default values
tx_end <= '0';
tx <= uart_idle;
tx <= UART_IDLE;
-- FSM description
case tx_fsm is
-- Wait to transfer data
84,38 → 92,49
when idle =>
-- Send Init Bit
if tx_req = '1' then
tx <= uart_start;
tx <= UART_START;
tx_data_tmp <= tx_data;
tx_fsm <= data;
data_cnt_tx <= (others=>'1');
tx_data_cnt <= (others=>'1');
tx_par_bit <= '0';
end if;
-- Data receive
when data =>
tx <= tx_data_tmp(0);
if data_cnt_tx = 0 then
tx_fsm <= stop1;
data_cnt_tx <= (others=>'1');
tx <= tx_data_tmp(0);
tx_par_bit <= tx_par_bit xor tx_data_tmp(0);
if tx_data_cnt = 0 then
if par_en = PARITY_EN then
tx_fsm <= parity;
else
tx_fsm <= stop1;
end if;
tx_data_cnt <= (others=>'1');
else
tx_data_tmp <= '0' & tx_data_tmp(7 downto 1);
data_cnt_tx <= data_cnt_tx - 1;
tx_data_cnt <= tx_data_cnt - 1;
end if;
when parity =>
tx <= tx_par_bit;
tx_fsm <= stop1;
-- End of communication
when stop1 =>
-- Send Stop Bit
tx <= uart_idle;
tx <= UART_IDLE;
tx_fsm <= stop2;
when stop2 =>
-- Send Stop Bit
tx_end <= '1';
tx <= uart_idle;
tx <= UART_IDLE;
tx_fsm <= idle;
-- Invalid States
when others => null;
end case;
-- Reset condition
if rst = '1' then
if rst = RST_LVL then
tx_fsm <= idle;
tx_par_bit <= '0';
tx_data_tmp <= (others=>'0');
tx_data_cnt <= (others=>'0');
end if;
end if;
end if;
126,37 → 145,57
if clk'event and clk = '1' then
if clock_en = '1' then
-- Default values
rx_ready <= '0';
rx_ready <= '0';
-- FSM description
case rx_fsm is
-- Wait to transfer data
when idle =>
if rx = uart_start then
if rx = UART_START then
rx_fsm <= data;
end if;
data_cnt_rx <= (others=>'0');
rx_par_bit <= '0';
rx_data_cnt <= (others=>'0');
-- Data receive
when data =>
if data_cnt_rx = 7 then
rx_fsm <= idle;
rx_ready <= '1';
rx_data(7) <= rx;
-- Check data to generate parity
if par_en = PARITY_EN then
rx_par_bit <= rx_par_bit xor rx;
end if;
 
if rx_data_cnt = 7 then
-- Data path
rx_data(7) <= rx;
for i in 0 to 6 loop
rx_data(i) <= rx_data_tmp(6-i);
rx_data(i) <= rx_data_tmp(6-i);
end loop;
 
-- With parity verification
if par_en = PARITY_EN then
rx_fsm <= parity;
-- Without parity verification
else
rx_ready <= '1';
rx_fsm <= idle;
end if;
else
rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
data_cnt_rx <= data_cnt_rx + 1;
rx_data_tmp <= rx_data_tmp(6 downto 0) & rx;
rx_data_cnt <= rx_data_cnt + 1;
end if;
when parity =>
-- Check received parity
rx_fsm <= idle;
if rx_par_bit = rx then
rx_ready <= '1';
end if;
when others => null;
end case;
-- Reset condition
if rst = '1' then
if rst = RST_LVL then
rx_fsm <= idle;
rx_ready <= '0';
rx_data <= (others=>'0');
data_cnt_rx <= (others=>'0');
rx_data_tmp <= (others=>'0');
rx_data_cnt <= (others=>'0');
end if;
end if;
end if;

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