URL
https://opencores.org/ocsvn/uart/uart/trunk
Subversion Repositories uart
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- This comparison shows the changes necessary to convert path
/
- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/trunk/uart_lib.vhd
23,7 → 23,7
-- Version Author Date Changes |
-- |
-- 0.1 Ovidiu Lupas 15 January 2000 New model |
-- ovilup@mail.dnttm.ro |
-- olupas@opencores.org |
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------- |
-- package UART_Def |
/trunk/clkUnit.vhd
23,7 → 23,7
-- Version Author Date Changes |
-- |
-- 0.1 Ovidiu Lupas 15 January 2000 New model |
-- ovilup@mail.dnttm.ro |
-- olupas@opencores.org |
------------------------------------------------------------------------------- |
-- Description : Generates the Baud clock and enable signals for RX & TX |
-- units. |
/trunk/UARTtest.vhd
157,6 → 157,7
ProcCyc : process(Clk,IntRx_N,IntTx_N,Reset) |
variable counter : unsigned(3 downto 0); |
constant cone : unsigned(3 downto 0):= "0001"; |
variable temp : bit := '0'; |
begin |
if Rising_Edge(Reset) then |
counter := "0000"; |
165,21 → 166,38
CS_N <= '1'; |
elsif Rising_Edge(Clk) then |
if IntTx_N = '0' then |
case counter is |
when "0000" => |
Addr <= "00"; |
DataIn <= x"AA"; |
WR_N <= '0'; |
CS_N <= '0'; |
counter := counter + cone; |
when "0001" => |
Addr <= "00"; |
DataIn <= x"55"; |
WR_N <= '0'; |
CS_N <= '0'; |
counter := "0000"; |
when others => null; |
end case; |
if temp = '0' then |
temp := '1'; |
case counter is |
when "0000" => |
Addr <= "00"; |
DataIn <= x"AA"; |
WR_N <= '0'; |
CS_N <= '0'; |
counter := counter + cone; |
when "0001" => |
Addr <= "00"; |
DataIn <= x"AF"; |
WR_N <= '0'; |
CS_N <= '0'; |
counter := counter + cone; |
when "0010" => |
Addr <= "00"; |
DataIn <= x"55"; |
WR_N <= '0'; |
CS_N <= '0'; |
counter := counter + cone; |
when "0011" => |
Addr <= "00"; |
DataIn <= x"E8"; |
WR_N <= '0'; |
CS_N <= '0'; |
counter := "0000"; |
when others => null; |
end case; |
elsif temp = '1' then |
temp := '0'; |
end if; |
elsif IntRx_N = '0' then |
Addr <= "00"; |
RD_N <= '0'; |