URL
https://opencores.org/ocsvn/uart_fpga_slow_control_migrated/uart_fpga_slow_control_migrated/trunk
Subversion Repositories uart_fpga_slow_control_migrated
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- This comparison shows the changes necessary to convert path
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- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/uart_fpga_slow_control/trunk/code/ab_uart_lbus_slave.vhd
356,7 → 356,7
when WRITE_DIVLTC => -- init WRITE_DIVLTC |
if s_write_msb = '0' then |
v_add_init <= O"0"; -- init Divisor Latch lsb |
v_data_init <= "00000010";--"00001111"; -- DEC 15 Baudrate = 230400 bps @ 55,296 MHz |
v_data_init <= "00000010"; -- DEC 2 Baudrate = 921600 bps @ 29,4912 MHz |
s_write_msb <= '1'; |
s_slave_init <= WRITE_DIVLTC; |
else |