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URL https://opencores.org/ocsvn/usb_phy/usb_phy/trunk

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Rev 6 → Rev 7

/trunk/rtl/verilog/usb_rx_phy.v
39,10 → 39,10
 
// CVS Log
//
// $Id: usb_rx_phy.v,v 1.1.1.1 2002-09-16 14:27:01 rudi Exp $
// $Id: usb_rx_phy.v,v 1.2 2003-10-19 17:40:13 rudi Exp $
//
// $Date: 2002-09-16 14:27:01 $
// $Revision: 1.1.1.1 $
// $Date: 2003-10-19 17:40:13 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/09/16 14:27:01 rudi
// Created Directory Structure
//
//
//
56,6 → 58,7
//
//
//
//
 
`include "timescale.v"
 
84,9 → 87,9
// Local Wires and Registers
//
 
reg rxd_t1, rxd_s1, rxd_s;
reg rxdp_t1, rxdp_s1, rxdp_s;
reg rxdn_t1, rxdn_s1, rxdn_s;
reg rxd_t1, rxd_s0, rxd_s1, rxd_s;
reg rxdp_t1, rxdp_s0, rxdp_s1, rxdp_s, rxdp_s_r;
reg rxdn_t1, rxdn_s0, rxdn_s1, rxdn_s, rxdn_s_r;
reg synced_d;
wire k, j, se0;
reg rx_en;
103,11 → 106,12
reg [1:0] dpll_state, dpll_next_state;
reg fs_ce_d, fs_ce;
wire change;
reg rxdp_s1r, rxdn_s1r;
wire lock_en;
reg fs_ce_r1, fs_ce_r2, fs_ce_r3;
reg [2:0] fs_state, fs_next_state;
reg rx_valid_r;
reg sync_err_d, sync_err;
reg bit_stuff_err;
reg se0_r, byte_err;
 
///////////////////////////////////////////////////////////////////
//
116,12 → 120,12
 
assign RxActive_o = rx_active;
assign RxValid_o = rx_valid;
assign RxError_o = 0;
assign RxError_o = sync_err | bit_stuff_err | byte_err;
assign DataIn_o = hold_reg;
assign LineState = {rxdp_s1, rxdn_s1};
 
always @(posedge clk)
rx_en <= #1 RxEn_i;
always @(posedge clk) rx_en <= RxEn_i;
always @(posedge clk) sync_err <= sync_err_d;
 
///////////////////////////////////////////////////////////////////
//
129,35 → 133,30
//
 
// First synchronize to the local system clock to
// avoid metastability outside the sync block (*_s1)
// Second synchronise to the internal bit clock (*_s)
always @(posedge clk)
rxd_t1 <= #1 rxd;
// avoid metastability outside the sync block (*_s0).
// Then make sure we see the signal for at least two
// clock cycles stable to avoid glitches and noise
 
always @(posedge clk)
rxd_s1 <= #1 rxd_t1;
always @(posedge clk) rxd_t1 <= rxd;
always @(posedge clk) rxd_s0 <= rxd_t1;
always @(posedge clk) rxd_s1 <= rxd_s0;
always @(posedge clk) // Avoid detecting Line Glitches and noise
if(rxd_s0 && rxd_s1) rxd_s <= 1'b1;
else
if(!rxd_s0 && !rxd_s1) rxd_s <= 1'b0;
 
always @(posedge clk)
rxd_s <= #1 rxd_s1;
always @(posedge clk) rxdp_t1 <= rxdp;
always @(posedge clk) rxdp_s0 <= rxdp_t1;
always @(posedge clk) rxdp_s1 <= rxdp_s0;
always @(posedge clk) rxdp_s_r <= rxdp_s0 & rxdp_s1;
always @(posedge clk) rxdp_s <= (rxdp_s0 & rxdp_s1) | rxdp_s_r; // Avoid detecting Line Glitches and noise
 
always @(posedge clk)
rxdp_t1 <= #1 rxdp;
always @(posedge clk) rxdn_t1 <= rxdn;
always @(posedge clk) rxdn_s0 <= rxdn_t1;
always @(posedge clk) rxdn_s1 <= rxdn_s0;
always @(posedge clk) rxdn_s_r <= rxdn_s0 & rxdn_s1;
always @(posedge clk) rxdn_s <= (rxdn_s0 & rxdn_s1) | rxdn_s_r; // Avoid detecting Line Glitches and noise
 
always @(posedge clk)
rxdp_s1 <= #1 rxdp_t1;
 
always @(posedge clk)
rxdp_s <= #1 rxdp_s1;
 
always @(posedge clk)
rxdn_t1 <= #1 rxdn;
 
always @(posedge clk)
rxdn_s1 <= #1 rxdn_t1;
 
always @(posedge clk)
rxdn_s <= #1 rxdn_s1;
 
assign k = !rxdp_s & rxdn_s;
assign j = rxdp_s & !rxdn_s;
assign se0 = !rxdp_s & !rxdn_s;
180,14 → 179,8
assign lock_en = rx_en;
 
// Edge detector
always @(posedge clk)
rxdp_s1r <= #1 rxdp_s1;
assign change = (rxdp_s0 != rxdp_s1) | (rxdn_s0 != rxdn_s1);
 
always @(posedge clk)
rxdn_s1r <= #1 rxdn_s1;
 
assign change = (rxdp_s1r != rxdp_s1) | (rxdn_s1r != rxdn_s1);
 
// DPLL FSM
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
194,8 → 187,8
`else
always @(posedge clk)
`endif
if(!rst) dpll_state <= #1 2'h1;
else dpll_state <= #1 dpll_next_state;
if(!rst) dpll_state <= 2'h1;
else dpll_state <= dpll_next_state;
 
always @(dpll_state or lock_en or change)
begin
202,37 → 195,26
fs_ce_d = 1'b0;
case(dpll_state) // synopsys full_case parallel_case
2'h0:
if(lock_en & change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h1;
if(lock_en && change) dpll_next_state = 2'h0;
else dpll_next_state = 2'h1;
2'h1:begin
fs_ce_d = 1'b1;
//if(lock_en & change) dpll_next_state = 3'h0;
if(lock_en & change) dpll_next_state = 3'h3;
else dpll_next_state = 3'h2;
if(lock_en && change) dpll_next_state = 2'h3;
else dpll_next_state = 2'h2;
end
2'h2:
if(lock_en & change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h3;
if(lock_en && change) dpll_next_state = 2'h0;
else dpll_next_state = 2'h3;
2'h3:
if(lock_en & change) dpll_next_state = 3'h0;
else dpll_next_state = 3'h0;
if(lock_en && change) dpll_next_state = 2'h0;
else dpll_next_state = 2'h0;
endcase
end
 
// Compensate for sync registers at the input - allign full speed
// clock enable to be in the middle between two bit changes ...
always @(posedge clk)
fs_ce_r1 <= #1 fs_ce_d;
always @(posedge clk) fs_ce <= fs_ce_d;
 
always @(posedge clk)
fs_ce_r2 <= #1 fs_ce_r1;
 
always @(posedge clk)
fs_ce_r3 <= #1 fs_ce_r2;
 
always @(posedge clk)
fs_ce <= #1 fs_ce_r3;
 
///////////////////////////////////////////////////////////////////
//
// Find Sync Pattern FSM
252,50 → 234,75
`else
always @(posedge clk)
`endif
if(!rst) fs_state <= #1 FS_IDLE;
else fs_state <= #1 fs_next_state;
if(!rst) fs_state <= FS_IDLE;
else fs_state <= fs_next_state;
 
always @(fs_state or fs_ce or k or j or rx_en)
begin
synced_d = 1'b0;
sync_err_d = 1'b0;
fs_next_state = fs_state;
if(fs_ce)
case(fs_state) // synopsys full_case parallel_case
FS_IDLE:
begin
if(k & rx_en) fs_next_state = K1;
if(k && rx_en) fs_next_state = K1;
end
K1:
begin
if(j & rx_en) fs_next_state = J1;
else fs_next_state = FS_IDLE;
if(j && rx_en) fs_next_state = J1;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
J1:
begin
if(k & rx_en) fs_next_state = K2;
else fs_next_state = FS_IDLE;
if(k && rx_en) fs_next_state = K2;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
K2:
begin
if(j & rx_en) fs_next_state = J2;
else fs_next_state = FS_IDLE;
if(j && rx_en) fs_next_state = J2;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
J2:
begin
if(k & rx_en) fs_next_state = K3;
else fs_next_state = FS_IDLE;
if(k && rx_en) fs_next_state = K3;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
K3:
begin
if(j & rx_en) fs_next_state = J3;
if(j && rx_en) fs_next_state = J3;
else
if(k & rx_en) fs_next_state = K4; // Allow missing one J
else fs_next_state = FS_IDLE;
if(k && rx_en) fs_next_state = K4; // Allow missing one J
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
J3:
begin
if(k & rx_en) fs_next_state = K4;
else fs_next_state = FS_IDLE;
if(k && rx_en) fs_next_state = K4;
else
begin
sync_err_d = 1'b1;
fs_next_state = FS_IDLE;
end
end
K4:
begin
315,16 → 322,16
`else
always @(posedge clk)
`endif
if(!rst) rx_active <= #1 1'b0;
if(!rst) rx_active <= 1'b0;
else
if(synced_d & rx_en) rx_active <= #1 1'b1;
if(synced_d && rx_en) rx_active <= 1'b1;
else
if(se0 & rx_valid_r ) rx_active <= #1 1'b0;
if(se0 && rx_valid_r) rx_active <= 1'b0;
 
always @(posedge clk)
if(rx_valid) rx_valid_r <= #1 1'b1;
if(rx_valid) rx_valid_r <= 1'b1;
else
if(fs_ce) rx_valid_r <= #1 1'b0;
if(fs_ce) rx_valid_r <= 1'b0;
 
///////////////////////////////////////////////////////////////////
//
332,7 → 339,7
//
 
always @(posedge clk)
if(fs_ce) sd_r <= #1 rxd_s;
if(fs_ce) sd_r <= rxd_s;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
339,9 → 346,9
`else
always @(posedge clk)
`endif
if(!rst) sd_nrzi <= #1 1'b0;
if(!rst) sd_nrzi <= 1'b0;
else
if(rx_active & fs_ce) sd_nrzi <= #1 !(rxd_s ^ sd_r);
if(rx_active && fs_ce) sd_nrzi <= !(rxd_s ^ sd_r);
 
///////////////////////////////////////////////////////////////////
//
353,18 → 360,21
`else
always @(posedge clk)
`endif
if(!rst) one_cnt <= #1 3'h0;
if(!rst) one_cnt <= 3'h0;
else
if(!shift_en) one_cnt <= #1 3'h0;
if(!shift_en) one_cnt <= 3'h0;
else
if(fs_ce)
begin
if(!sd_nrzi | drop_bit) one_cnt <= #1 3'h0;
else one_cnt <= #1 one_cnt + 3'h1;
if(!sd_nrzi || drop_bit) one_cnt <= 3'h0;
else one_cnt <= one_cnt + 3'h1;
end
 
assign drop_bit = (one_cnt==3'h6);
 
always @(posedge clk) // Bit Stuff Error
bit_stuff_err <= drop_bit & sd_nrzi & fs_ce & !se0 & rx_active;
 
///////////////////////////////////////////////////////////////////
//
// Serial => Parallel converter
371,11 → 381,11
//
 
always @(posedge clk)
if(fs_ce) shift_en <= #1 synced_d | rx_active;
if(fs_ce) shift_en <= synced_d | rx_active;
 
always @(posedge clk)
if(fs_ce & shift_en & !drop_bit)
hold_reg <= #1 {sd_nrzi, hold_reg[7:1]};
if(fs_ce && shift_en && !drop_bit)
hold_reg <= {sd_nrzi, hold_reg[7:1]};
 
///////////////////////////////////////////////////////////////////
//
387,11 → 397,11
`else
always @(posedge clk)
`endif
if(!rst) bit_cnt <= #1 3'b0;
if(!rst) bit_cnt <= 3'b0;
else
if(!shift_en) bit_cnt <= #1 3'h0;
if(!shift_en) bit_cnt <= 3'h0;
else
if(fs_ce & !drop_bit) bit_cnt <= #1 bit_cnt + 3'h1;
if(fs_ce && !drop_bit) bit_cnt <= bit_cnt + 3'h1;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
398,14 → 408,18
`else
always @(posedge clk)
`endif
if(!rst) rx_valid1 <= #1 1'b0;
if(!rst) rx_valid1 <= 1'b0;
else
if(fs_ce & !drop_bit & (bit_cnt==3'h7)) rx_valid1 <= #1 1'b1;
if(fs_ce && !drop_bit && (bit_cnt==3'h7)) rx_valid1 <= 1'b1;
else
if(rx_valid1 & fs_ce & !drop_bit) rx_valid1 <= #1 1'b0;
if(rx_valid1 && fs_ce && !drop_bit) rx_valid1 <= 1'b0;
 
always @(posedge clk)
rx_valid <= #1 !drop_bit & rx_valid1 & fs_ce;
rx_valid <= !drop_bit & rx_valid1 & fs_ce;
 
always @(posedge clk) se0_r <= se0;
 
always @(posedge clk) byte_err <= se0 & !se0_r & (|bit_cnt);
 
endmodule
 
/trunk/rtl/verilog/usb_tx_phy.v
39,10 → 39,10
 
// CVS Log
//
// $Id: usb_tx_phy.v,v 1.1.1.1 2002-09-16 14:27:02 rudi Exp $
// $Id: usb_tx_phy.v,v 1.2 2003-10-19 17:40:13 rudi Exp $
//
// $Date: 2002-09-16 14:27:02 $
// $Revision: 1.1.1.1 $
// $Date: 2003-10-19 17:40:13 $
// $Revision: 1.2 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
49,6 → 49,8
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1 2002/09/16 14:27:02 rudi
// Created Directory Structure
//
//
//
55,6 → 57,7
//
//
//
//
 
`include "timescale.v"
 
91,7 → 94,6
 
reg TxReady_o;
reg [2:0] state, next_state;
reg tx_ready;
reg tx_ready_d;
reg ld_sop_d;
reg ld_data_d;
125,19 → 127,16
// Misc Logic
//
 
always @(posedge clk)
tx_ready <= #1 tx_ready_d;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
`else
always @(posedge clk)
`endif
if(!rst) TxReady_o <= #1 1'b0;
else TxReady_o <= #1 tx_ready_d & TxValid_i;
if(!rst) TxReady_o <= 1'b0;
else TxReady_o <= tx_ready_d & TxValid_i;
 
always @(posedge clk)
ld_data <= #1 ld_data_d;
ld_data <= ld_data_d;
 
///////////////////////////////////////////////////////////////////
//
149,11 → 148,11
`else
always @(posedge clk)
`endif
if(!rst) tx_ip <= #1 1'b0;
if(!rst) tx_ip <= 1'b0;
else
if(ld_sop_d) tx_ip <= #1 1'b1;
if(ld_sop_d) tx_ip <= 1'b1;
else
if(eop_done) tx_ip <= #1 1'b0;
if(eop_done) tx_ip <= 1'b0;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
160,9 → 159,9
`else
always @(posedge clk)
`endif
if(!rst) tx_ip_sync <= #1 1'b0;
if(!rst) tx_ip_sync <= 1'b0;
else
if(fs_ce) tx_ip_sync <= #1 tx_ip;
if(fs_ce) tx_ip_sync <= tx_ip;
 
// data_done helps us to catch cases where TxValid drops due to
// packet end and then gets re-asserted as a new packet starts.
173,11 → 172,11
`else
always @(posedge clk)
`endif
if(!rst) data_done <= #1 1'b0;
if(!rst) data_done <= 1'b0;
else
if(TxValid_i & ! tx_ip) data_done <= #1 1'b1;
if(TxValid_i && ! tx_ip) data_done <= 1'b1;
else
if(!TxValid_i) data_done <= #1 1'b0;
if(!TxValid_i) data_done <= 1'b0;
 
///////////////////////////////////////////////////////////////////
//
189,41 → 188,41
`else
always @(posedge clk)
`endif
if(!rst) bit_cnt <= #1 3'h0;
if(!rst) bit_cnt <= 3'h0;
else
if(!tx_ip_sync) bit_cnt <= #1 3'h0;
if(!tx_ip_sync) bit_cnt <= 3'h0;
else
if(fs_ce & !hold) bit_cnt <= #1 bit_cnt + 3'h1;
if(fs_ce && !hold) bit_cnt <= bit_cnt + 3'h1;
 
assign hold = stuff;
 
always @(posedge clk)
if(!tx_ip_sync) sd_raw_o <= #1 1'b0;
if(!tx_ip_sync) sd_raw_o <= 1'b0;
else
case(bit_cnt) // synopsys full_case parallel_case
3'h0: sd_raw_o <= #1 hold_reg[0];
3'h1: sd_raw_o <= #1 hold_reg[1];
3'h2: sd_raw_o <= #1 hold_reg[2];
3'h3: sd_raw_o <= #1 hold_reg[3];
3'h4: sd_raw_o <= #1 hold_reg[4];
3'h5: sd_raw_o <= #1 hold_reg[5];
3'h6: sd_raw_o <= #1 hold_reg[6];
3'h7: sd_raw_o <= #1 hold_reg[7];
3'h0: sd_raw_o <= hold_reg[0];
3'h1: sd_raw_o <= hold_reg[1];
3'h2: sd_raw_o <= hold_reg[2];
3'h3: sd_raw_o <= hold_reg[3];
3'h4: sd_raw_o <= hold_reg[4];
3'h5: sd_raw_o <= hold_reg[5];
3'h6: sd_raw_o <= hold_reg[6];
3'h7: sd_raw_o <= hold_reg[7];
endcase
 
always @(posedge clk)
sft_done <= #1 !hold & (bit_cnt == 3'h7);
sft_done <= !hold & (bit_cnt == 3'h7);
 
always @(posedge clk)
sft_done_r <= #1 sft_done;
sft_done_r <= sft_done;
 
assign sft_done_e = sft_done & !sft_done_r;
 
// Out Data Hold Register
always @(posedge clk)
if(ld_sop_d) hold_reg <= #1 8'h80;
if(ld_sop_d) hold_reg <= 8'h80;
else
if(ld_data) hold_reg <= #1 DataOut_i;
if(ld_data) hold_reg <= DataOut_i;
 
///////////////////////////////////////////////////////////////////
//
235,14 → 234,14
`else
always @(posedge clk)
`endif
if(!rst) one_cnt <= #1 3'h0;
if(!rst) one_cnt <= 3'h0;
else
if(!tx_ip_sync) one_cnt <= #1 3'h0;
if(!tx_ip_sync) one_cnt <= 3'h0;
else
if(fs_ce)
begin
if(!sd_raw_o | stuff) one_cnt <= #1 3'h0;
else one_cnt <= #1 one_cnt + 3'h1;
if(!sd_raw_o || stuff) one_cnt <= 3'h0;
else one_cnt <= one_cnt + 3'h1;
end
 
assign stuff = (one_cnt==3'h6);
252,10 → 251,9
`else
always @(posedge clk)
`endif
if(!rst) sd_bs_o <= #1 1'h0;
if(!rst) sd_bs_o <= 1'h0;
else
if(fs_ce) sd_bs_o <= #1 !tx_ip_sync ? 1'b0 :
(stuff ? 1'b0 : sd_raw_o);
if(fs_ce) sd_bs_o <= !tx_ip_sync ? 1'b0 : (stuff ? 1'b0 : sd_raw_o);
 
///////////////////////////////////////////////////////////////////
//
267,11 → 265,11
`else
always @(posedge clk)
`endif
if(!rst) sd_nrzi_o <= #1 1'b1;
if(!rst) sd_nrzi_o <= 1'b1;
else
if(!tx_ip_sync | !txoe_r1) sd_nrzi_o <= #1 1'b1;
if(!tx_ip_sync || !txoe_r1) sd_nrzi_o <= 1'b1;
else
if(fs_ce) sd_nrzi_o <= #1 sd_bs_o ? sd_nrzi_o : ~sd_nrzi_o;
if(fs_ce) sd_nrzi_o <= sd_bs_o ? sd_nrzi_o : ~sd_nrzi_o;
 
///////////////////////////////////////////////////////////////////
//
283,11 → 281,11
`else
always @(posedge clk)
`endif
if(!rst) append_eop <= #1 1'b0;
if(!rst) append_eop <= 1'b0;
else
if(ld_eop_d) append_eop <= #1 1'b1;
if(ld_eop_d) append_eop <= 1'b1;
else
if(append_eop_sync2) append_eop <= #1 1'b0;
if(append_eop_sync2) append_eop <= 1'b0;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
294,9 → 292,9
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync1 <= #1 1'b0;
if(!rst) append_eop_sync1 <= 1'b0;
else
if(fs_ce) append_eop_sync1 <= #1 append_eop;
if(fs_ce) append_eop_sync1 <= append_eop;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
303,9 → 301,9
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync2 <= #1 1'b0;
if(!rst) append_eop_sync2 <= 1'b0;
else
if(fs_ce) append_eop_sync2 <= #1 append_eop_sync1;
if(fs_ce) append_eop_sync2 <= append_eop_sync1;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
312,9 → 310,9
`else
always @(posedge clk)
`endif
if(!rst) append_eop_sync3 <= #1 1'b0;
if(!rst) append_eop_sync3 <= 1'b0;
else
if(fs_ce) append_eop_sync3 <= #1 append_eop_sync2;
if(fs_ce) append_eop_sync3 <= append_eop_sync2;
 
assign eop_done = append_eop_sync3;
 
328,9 → 326,9
`else
always @(posedge clk)
`endif
if(!rst) txoe_r1 <= #1 1'b0;
if(!rst) txoe_r1 <= 1'b0;
else
if(fs_ce) txoe_r1 <= #1 tx_ip_sync;
if(fs_ce) txoe_r1 <= tx_ip_sync;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
337,9 → 335,9
`else
always @(posedge clk)
`endif
if(!rst) txoe_r2 <= #1 1'b0;
if(!rst) txoe_r2 <= 1'b0;
else
if(fs_ce) txoe_r2 <= #1 txoe_r1;
if(fs_ce) txoe_r2 <= txoe_r1;
 
`ifdef USB_ASYNC_REST
always @(posedge clk or negedge rst)
346,9 → 344,9
`else
always @(posedge clk)
`endif
if(!rst) txoe <= #1 1'b1;
if(!rst) txoe <= 1'b1;
else
if(fs_ce) txoe <= #1 !(txoe_r1 | txoe_r2);
if(fs_ce) txoe <= !(txoe_r1 | txoe_r2);
 
///////////////////////////////////////////////////////////////////
//
360,9 → 358,9
`else
always @(posedge clk)
`endif
if(!rst) txdp <= #1 1'b1;
if(!rst) txdp <= 1'b1;
else
if(fs_ce) txdp <= #1 phy_mode ?
if(fs_ce) txdp <= phy_mode ?
(!append_eop_sync3 & sd_nrzi_o) :
sd_nrzi_o;
 
371,9 → 369,9
`else
always @(posedge clk)
`endif
if(!rst) txdn <= #1 1'b0;
if(!rst) txdn <= 1'b0;
else
if(fs_ce) txdn <= #1 phy_mode ?
if(fs_ce) txdn <= phy_mode ?
(!append_eop_sync3 & ~sd_nrzi_o) :
append_eop_sync3;
 
387,8 → 385,8
`else
always @(posedge clk)
`endif
if(!rst) state <= #1 IDLE;
else state <= #1 next_state;
if(!rst) state <= IDLE;
else state <= next_state;
 
always @(state or TxValid_i or data_done or sft_done_e or eop_done or fs_ce)
begin
419,13 → 417,13
end
DATA:
begin
if(!data_done & sft_done_e)
if(!data_done && sft_done_e)
begin
ld_eop_d = 1'b1;
next_state = EOP1;
end
if(data_done & sft_done_e)
if(data_done && sft_done_e)
begin
tx_ready_d = 1'b1;
ld_data_d = 1'b1;
437,7 → 435,7
end
EOP2:
begin
if(!eop_done & fs_ce) next_state = WAIT;
if(!eop_done && fs_ce) next_state = WAIT;
end
WAIT:
begin
444,7 → 442,6
if(fs_ce) next_state = IDLE;
end
endcase
end
 
endmodule
/trunk/rtl/verilog/usb_phy.v
38,10 → 38,10
 
// CVS Log
//
// $Id: usb_phy.v,v 1.2 2002-09-16 16:06:37 rudi Exp $
// $Id: usb_phy.v,v 1.3 2003-10-19 17:40:13 rudi Exp $
//
// $Date: 2002-09-16 16:06:37 $
// $Revision: 1.2 $
// $Date: 2003-10-19 17:40:13 $
// $Revision: 1.3 $
// $Author: rudi $
// $Locker: $
// $State: Exp $
48,6 → 48,9
//
// Change History:
// $Log: not supported by cvs2svn $
// Revision 1.2 2002/09/16 16:06:37 rudi
// Changed top level name to be consistent ...
//
// Revision 1.1.1.1 2002/09/16 14:26:59 rudi
// Created Directory Structure
//
92,7 → 95,7
// Local Wires and Registers
//
 
reg [5:0] rst_cnt;
reg [4:0] rst_cnt;
reg usb_rst;
wire reset;
 
155,14 → 158,14
//
 
always @(posedge clk)
if(!rst) rst_cnt <= #1 5'h0;
if(!rst) rst_cnt <= 5'h0;
else
if(LineState_o != 2'h0) rst_cnt <= #1 5'h0;
if(LineState_o != 2'h0) rst_cnt <= 5'h0;
else
if(!usb_rst & fs_ce) rst_cnt <= #1 rst_cnt + 5'h1;
if(!usb_rst && fs_ce) rst_cnt <= rst_cnt + 5'h1;
 
always @(posedge clk)
usb_rst <= #1 (rst_cnt == 5'd31);
usb_rst <= (rst_cnt == 5'h1f);
 
endmodule
 
/trunk/doc/README.txt
16,16 → 16,23
Documentation
-------------
Sorry, there is none. I just don't have the time to write it. I have tried
to follow the UTMI interface specification from USB 2.0 with one exception:
I have not added any error checking in the RX PHY, hence the RxError pin
is permanently tide to ground.
to follow the UTMI interface specification from USB 2.0.
'phy_mode' selects between single ended and differential tx_phy output. See
Philips ISP 1105 transceiver data sheet for an explanation of it's MODE
select pin.
select pin (see Note below).
Currently this PHY only operates in Full-Speed mode. Required clock frequency
is 48MHz, from which the 12MHz USB transmit and receive clocks are derived.
 
Notes:
RxError reports the following errors:
- sync errors
Could not synchronize to incoming bit stream
- Bit Stuff Error
Stuff bit had the wrong value (expected '0' got '1')
- Byte Error
Got a EOP (se0) before finished assembling a full byteAll of those errors
are or'ed together and reported via RxError.
 
Note:
1) "phy_tx_mode" selects the PHY Transmit Mode:
When phy_tx_mode is '0' the outputs are encoded as:
txdn, txdp
44,7 → 51,7
See PHILIPS Transceiver Data Sheet for: ISP1105, ISP1106 and ISP1107
for more details.
 
2) "usb_rst" Indicates a USB Bus Reset (this output is also ored with
2) "usb_rst" Indicates a USB Bus Reset (this output is also or'ed with
the reset input).
 
Misc

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