URL
https://opencores.org/ocsvn/versatile_fifo/versatile_fifo/trunk
Subversion Repositories versatile_fifo
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- This comparison shows the changes necessary to convert path
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- from Rev 6 to Rev 7
- ↔ Reverse comparison
Rev 6 → Rev 7
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v
0,0 → 1,69
module versatile_fifo_async_cmp ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst ); |
|
parameter ADDR_WIDTH = 4; |
parameter N = ADDR_WIDTH-1; |
|
parameter Q1 = 2'b00; |
parameter Q2 = 2'b01; |
parameter Q3 = 2'b11; |
parameter Q4 = 2'b10; |
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parameter going_empty = 1'b0; |
parameter going_full = 1'b1; |
|
input [N:0] wptr, rptr; |
output reg fifo_empty, fifo_full; |
input wclk, rclk, rst; |
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reg direction, direction_set, direction_clr; |
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wire async_empty, async_full; |
reg fifo_full2, fifo_empty2; |
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// direction_set |
always @ (wptr[N:N-1] or rptr[N:N-1]) |
case ({wptr[N:N-1],rptr[N:N-1]}) |
{Q1,Q2} : direction_set <= 1'b1; |
{Q2,Q3} : direction_set <= 1'b1; |
{Q3,Q4} : direction_set <= 1'b1; |
{Q4,Q1} : direction_set <= 1'b1; |
default : direction_set <= 1'b0; |
endcase |
|
// direction_clear |
always @ (wptr[N:N-1] or rptr[N:N-1] or rst) |
if (rst) |
direction_clr <= 1'b1; |
else |
case ({wptr[N:N-1],rptr[N:N-1]}) |
{Q2,Q1} : direction_clr <= 1'b1; |
{Q3,Q2} : direction_clr <= 1'b1; |
{Q4,Q3} : direction_clr <= 1'b1; |
{Q1,Q4} : direction_clr <= 1'b1; |
default : direction_clr <= 1'b0; |
endcase |
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always @ (posedge direction_set or posedge direction_clr) |
if (direction_clr) |
direction <= going_empty; |
else |
direction <= going_full; |
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assign async_empty = (wptr == rptr) && (direction==going_empty); |
assign async_full = (wptr == rptr) && (direction==going_full); |
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always @ (posedge wclk or posedge rst or posedge async_full) |
if (rst) |
{fifo_full, fifo_full2} <= 2'b00; |
else if (async_full) |
{fifo_full, fifo_full2} <= 2'b11; |
else |
{fifo_full, fifo_full2} <= {fifo_full2, async_full}; |
|
always @ (posedge rclk or posedge async_empty) |
if (async_empty) |
{fifo_empty, fifo_empty2} <= 2'b11; |
else |
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; |
|
endmodule // async_comp |
versatile_fifo/trunk/rtl/verilog/versatile_fifo_async_cmp.v
Property changes :
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: versatile_fifo/trunk/rtl/verilog/sd_counter_defines.v
===================================================================
--- versatile_fifo/trunk/rtl/verilog/sd_counter_defines.v (nonexistent)
+++ versatile_fifo/trunk/rtl/verilog/sd_counter_defines.v (revision 7)
@@ -0,0 +1,39 @@
+// module name
+`define CNT_MODULE_NAME sd_counter
+
+// counter type = [BINARY, GRAY, LFSR]
+//`define CNT_TYPE_BINARY
+`define CNT_TYPE_GRAY
+//`define CNT_TYPE_LFSR
+
+// q as output
+`define CNT_Q
+// for gray type counter optional binary output
+`define CNT_Q_BIN
+
+// number of CNT bins
+`define CNT_LENGTH 9
+
+// clear
+//`define CNT_CLEAR
+
+// set
+//`define CNT_SET
+`define CNT_SET_VALUE `CNT_LENGTH'h9
+
+// wrap around creates shorter cycle than maximum length
+//`define CNT_WRAP
+`define CNT_WRAP_VALUE `CNT_LENGTH'h9
+
+// clock enable
+`define CNT_CE
+
+// q_next as an output
+//`define CNT_QNEXT
+
+// q=0 as an output
+//`define CNT_Z
+
+// q_next=0 as a registered output
+//`define CNT_ZQ
+
Index: versatile_fifo/trunk/rtl/verilog/Makefile
===================================================================
--- versatile_fifo/trunk/rtl/verilog/Makefile (revision 6)
+++ versatile_fifo/trunk/rtl/verilog/Makefile (revision 7)
@@ -16,3 +16,7 @@
vpp versatile_counter.v > tmp1.v
vppp --simple tmp1.v | cat copyright.v - > gray_counter.v
+sd:
+ cp sd_counter_defines.v versatile_counter_defines.v
+ vpp versatile_counter.v > tmp1.v
+ vppp --simple tmp1.v | cat copyright.v - > sd_counter.v
/versatile_fifo/trunk/rtl/verilog/versatile_fifo_dual_port_ram_dc_dw.v
12,7 → 12,7
clk_b |
); |
parameter DATA_WIDTH = 8; |
parameter ADDR_WIDTH = 9; |
parameter ADDR_WIDTH = 11; |
input [(DATA_WIDTH-1):0] d_a; |
input [(ADDR_WIDTH-1):0] adr_a; |
input [(ADDR_WIDTH-1):0] adr_b; |