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https://opencores.org/ocsvn/wb2hpi/wb2hpi/trunk
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Rev 6 → Rev 7
/tags/ver_1_0/apps/pci2dsp/syn/synplify/src/regPCI.sdc
0,0 → 1,206
#************************** CVS history ***************************# |
# $Author: gvozden $ |
# $Date: 2003-07-29 13:09:42 $ |
# $Revision: 1.3 $ |
# $Name: not supported by cvs2svn $ |
#************************** CVS history ***************************# |
|
|
# |
# Clocks |
# |
define_clock -name {CLK} -freq 35.000 -clockgroup clkkrp_pci |
define_clock -name {WB_CLK} -freq 30.000 -clockgroup clkgrp_wb |
|
# |
# Inputs/Outputs |
# |
define_input_delay {AD0} 7.00 -ref CLK:r |
define_input_delay {AD1} 7.00 -ref CLK:r |
define_input_delay {AD2} 7.00 -ref CLK:r |
define_input_delay {AD3} 7.00 -ref CLK:r |
define_input_delay {AD4} 7.00 -ref CLK:r |
define_input_delay {AD5} 7.00 -ref CLK:r |
define_input_delay {AD6} 7.00 -ref CLK:r |
define_input_delay {AD7} 7.00 -ref CLK:r |
define_input_delay {AD8} 7.00 -ref CLK:r |
define_input_delay {AD9} 7.00 -ref CLK:r |
define_input_delay {AD10} 7.00 -ref CLK:r |
define_input_delay {AD11} 7.00 -ref CLK:r |
define_input_delay {AD12} 7.00 -ref CLK:r |
define_input_delay {AD13} 7.00 -ref CLK:r |
define_input_delay {AD14} 7.00 -ref CLK:r |
define_input_delay {AD15} 7.00 -ref CLK:r |
define_input_delay {AD16} 7.00 -ref CLK:r |
define_input_delay {AD17} 7.00 -ref CLK:r |
define_input_delay {AD18} 7.00 -ref CLK:r |
define_input_delay {AD19} 7.00 -ref CLK:r |
define_input_delay {AD20} 7.00 -ref CLK:r |
define_input_delay {AD21} 7.00 -ref CLK:r |
define_input_delay {AD22} 7.00 -ref CLK:r |
define_input_delay {AD23} 7.00 -ref CLK:r |
define_input_delay {AD24} 7.00 -ref CLK:r |
define_input_delay {AD25} 7.00 -ref CLK:r |
define_input_delay {AD26} 7.00 -ref CLK:r |
define_input_delay {AD27} 7.00 -ref CLK:r |
define_input_delay {AD28} 7.00 -ref CLK:r |
define_input_delay {AD29} 7.00 -ref CLK:r |
define_input_delay {AD30} 7.00 -ref CLK:r |
define_input_delay {AD31} 7.00 -ref CLK:r |
define_input_delay {CBE0} 7.00 -ref CLK:r |
define_input_delay {CBE1} 7.00 -ref CLK:r |
define_input_delay {CBE2} 7.00 -ref CLK:r |
define_input_delay {CBE3} 7.00 -ref CLK:r |
define_input_delay {FRAME} 7.00 -ref CLK:r |
define_input_delay {IRDY} 7.00 -ref CLK:r |
define_input_delay {IDSEL} 7.00 -ref CLK:r |
define_input_delay {TRDY} 7.00 -route 3.00 -ref CLK:r |
define_input_delay {STOP} 7.00 -route 1.00 -ref CLK:r |
define_input_delay {PAR} 7.00 -ref CLK:r |
define_input_delay {PERR} 7.00 -ref CLK:r |
define_input_delay {GNT} 10.00 -route 2.00 -ref CLK:r |
define_output_delay {AD0} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD1} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD2} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD3} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD4} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD5} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD6} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD7} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD8} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD9} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD10} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD11} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD12} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD13} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD14} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD15} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD16} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD17} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD18} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD19} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD20} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD21} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD22} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD23} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD24} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD25} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD26} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD27} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD28} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD29} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD30} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {AD31} 11.00 -route 4.00 -ref CLK:r |
define_output_delay {CBE0} 11.00 -ref CLK:r |
define_output_delay {CBE1} 11.00 -ref CLK:r |
define_output_delay {CBE2} 11.00 -ref CLK:r |
define_output_delay {CBE3} 11.00 -ref CLK:r |
define_output_delay {FRAME} 11.00 -ref CLK:r |
define_output_delay {IRDY} 11.00 -ref CLK:r |
define_input_delay {DEVSEL} 11.00 -ref CLK:r |
define_output_delay {TRDY} 11.00 -ref CLK:r |
define_output_delay {STOP} 11.00 -ref CLK:r |
define_output_delay {PAR} 11.00 -ref CLK:r |
define_output_delay {PERR} 11.00 -ref CLK:r |
define_output_delay {SERR} 11.00 -ref CLK:r |
define_output_delay {REQ} 12.00 -ref CLK:r |
|
# |
# Registers |
# |
|
# |
# Multicycle Path |
# |
|
# |
# False Path |
# |
define_false_path -from {i:bridge.configuration.*} -to {i:WB2HPI.WB_slave.WBS_DAT_O[31:0]} |
|
# |
# Attributes |
# |
define_global_attribute syn_netlist_hierarchy {0} |
define_global_attribute syn_forward_io_constraints {1} |
define_attribute {v:work.pci_io_mux} syn_hier {hard} |
define_attribute {v:work.pci_parity_check} syn_hier {hard} |
define_attribute {v:work.pci_cbe_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_frame_crit} syn_hier {hard} |
define_attribute {v:work.pci_frame_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_frame_load_crit} syn_hier {hard} |
define_attribute {v:work.pci_irdy_out_crit} syn_hier {hard} |
define_attribute {v:work.pci_mas_ad_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_mas_ad_load_crit} syn_hier {hard} |
define_attribute {v:work.pci_mas_ch_state_crit} syn_hier {hard} |
define_attribute {v:work.pci_par_crit} syn_hier {hard} |
define_attribute {v:work.pci_io_mux_ad_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_io_mux_ad_load_crit} syn_hier {hard} |
define_attribute {v:work.pci_target32_devs_crit} syn_hier {hard} |
define_attribute {v:work.pci_target32_stop_crit} syn_hier {hard} |
define_attribute {v:work.pci_target32_trdy_crit} syn_hier {hard} |
define_attribute {v:work.pci_perr_crit} syn_hier {hard} |
define_attribute {v:work.pci_perr_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_serr_crit} syn_hier {hard} |
define_attribute {v:work.pci_serr_en_crit} syn_hier {hard} |
define_attribute {v:work.pci_cur_out_reg} syn_hier {hard} |
define_attribute {v:work.pci_out_reg} syn_hier {hard} |
define_attribute {AD0} syn_useioff {1} |
define_attribute {AD1} syn_useioff {1} |
define_attribute {AD2} syn_useioff {1} |
define_attribute {AD3} syn_useioff {1} |
define_attribute {AD4} syn_useioff {1} |
define_attribute {AD5} syn_useioff {1} |
define_attribute {AD6} syn_useioff {1} |
define_attribute {AD7} syn_useioff {1} |
define_attribute {AD8} syn_useioff {1} |
define_attribute {AD9} syn_useioff {1} |
define_attribute {AD10} syn_useioff {1} |
define_attribute {AD11} syn_useioff {1} |
define_attribute {AD12} syn_useioff {1} |
define_attribute {AD13} syn_useioff {1} |
define_attribute {AD14} syn_useioff {1} |
define_attribute {AD15} syn_useioff {1} |
define_attribute {AD16} syn_useioff {1} |
define_attribute {AD17} syn_useioff {1} |
define_attribute {AD18} syn_useioff {1} |
define_attribute {AD19} syn_useioff {1} |
define_attribute {AD20} syn_useioff {1} |
define_attribute {AD21} syn_useioff {1} |
define_attribute {AD22} syn_useioff {1} |
define_attribute {AD23} syn_useioff {1} |
define_attribute {AD24} syn_useioff {1} |
define_attribute {AD25} syn_useioff {1} |
define_attribute {AD26} syn_useioff {1} |
define_attribute {AD27} syn_useioff {1} |
define_attribute {AD28} syn_useioff {1} |
define_attribute {AD29} syn_useioff {1} |
define_attribute {AD30} syn_useioff {1} |
define_attribute {AD31} syn_useioff {1} |
define_attribute {CBE0} syn_useioff {1} |
define_attribute {CBE1} syn_useioff {1} |
define_attribute {CBE2} syn_useioff {1} |
define_attribute {CBE3} syn_useioff {1} |
define_attribute {DEVSEL} syn_useioff {1} |
define_attribute {FRAME} syn_useioff {1} |
define_attribute {GNT} syn_useioff {1} |
define_attribute {IDSEL} syn_useioff {1} |
define_attribute {INTA} syn_useioff {1} |
define_attribute {IRDY} syn_useioff {1} |
define_attribute {PAR} syn_useioff {1} |
define_attribute {PERR} syn_useioff {1} |
define_attribute {REQ} syn_useioff {1} |
define_attribute {RST} syn_useioff {1} |
define_attribute {SERR} syn_useioff {1} |
define_attribute {STOP} syn_useioff {1} |
define_attribute {TRDY} syn_useioff {1} |
define_attribute {CLK} xc_padtype {BUFGP} |
define_attribute {DSP_HINT} syn_noclockbuf {1} |
|
# |
# Other Constraints |
# |
|
# |
# Order of waveforms |
# |
/tags/ver_1_0/apps/pci2dsp/syn/synplify/src/regPCI.prj
0,0 → 1,110
#************************** CVS history ***************************# |
# $Author: gvozden $ |
# $Date: 2003-02-28 14:10:53 $ |
# $Revision: 1.2 $ |
# $Name: not supported by cvs2svn $ |
#************************** CVS history ***************************# |
|
#add_file options |
add_file -verilog "../../../pci/virtex.v" |
add_file -verilog "../../../rtl/verilog/top.v" |
add_file -verilog "../../../pci/meta_flop.v" |
add_file -verilog "../../../pci/pci_async_reset_flop.v" |
add_file -verilog "../../../pci/pci_bridge32.v" |
add_file -verilog "../../../pci/pci_cbe_en_crit.v" |
add_file -verilog "../../../pci/pci_conf_cyc_addr_dec.v" |
add_file -verilog "../../../pci/pci_conf_space.v" |
add_file -verilog "../../../pci/pci_constants.v" |
add_file -verilog "../../../pci/pci_cur_out_reg.v" |
add_file -verilog "../../../pci/pci_delayed_sync.v" |
add_file -verilog "../../../pci/pci_delayed_write_reg.v" |
add_file -verilog "../../../pci/pci_frame_crit.v" |
add_file -verilog "../../../pci/pci_frame_en_crit.v" |
add_file -verilog "../../../pci/pci_frame_load_crit.v" |
add_file -verilog "../../../pci/pci_in_reg.v" |
add_file -verilog "../../../pci/pci_io_mux.v" |
add_file -verilog "../../../pci/pci_io_mux_ad_en_crit.v" |
add_file -verilog "../../../pci/pci_io_mux_ad_load_crit.v" |
add_file -verilog "../../../pci/pci_irdy_out_crit.v" |
add_file -verilog "../../../pci/pci_mas_ad_en_crit.v" |
add_file -verilog "../../../pci/pci_mas_ad_load_crit.v" |
add_file -verilog "../../../pci/pci_mas_ch_state_crit.v" |
add_file -verilog "../../../pci/pci_master32_sm.v" |
add_file -verilog "../../../pci/pci_master32_sm_if.v" |
add_file -verilog "../../../pci/pci_out_reg.v" |
add_file -verilog "../../../pci/pci_par_crit.v" |
add_file -verilog "../../../pci/pci_parity_check.v" |
add_file -verilog "../../../pci/pci_pci_decoder.v" |
add_file -verilog "../../../pci/pci_pci_tpram.v" |
add_file -verilog "../../../pci/pci_pcir_fifo_control.v" |
add_file -verilog "../../../pci/pci_pciw_fifo_control.v" |
add_file -verilog "../../../pci/pci_pciw_pcir_fifos.v" |
add_file -verilog "../../../pci/pci_perr_crit.v" |
add_file -verilog "../../../pci/pci_perr_en_crit.v" |
add_file -verilog "../../../pci/pci_ram_16x40d.v" |
add_file -verilog "../../../pci/pci_rst_int.v" |
add_file -verilog "../../../pci/pci_serr_crit.v" |
add_file -verilog "../../../pci/pci_serr_en_crit.v" |
add_file -verilog "../../../pci/pci_sync_module.v" |
add_file -verilog "../../../pci/pci_target32_clk_en.v" |
add_file -verilog "../../../pci/pci_target32_devs_crit.v" |
add_file -verilog "../../../pci/pci_target32_interface.v" |
add_file -verilog "../../../pci/pci_target32_sm.v" |
add_file -verilog "../../../pci/pci_target32_stop_crit.v" |
add_file -verilog "../../../pci/pci_target32_trdy_crit.v" |
add_file -verilog "../../../pci/pci_target_unit.v" |
add_file -verilog "../../../pci/pci_wb_addr_mux.v" |
add_file -verilog "../../../pci/pci_wb_decoder.v" |
add_file -verilog "../../../pci/pci_wb_master.v" |
add_file -verilog "../../../pci/pci_wb_slave.v" |
add_file -verilog "../../../pci/pci_wb_slave_unit.v" |
add_file -verilog "../../../pci/pci_wb_tpram.v" |
add_file -verilog "../../../pci/pci_wbr_fifo_control.v" |
add_file -verilog "../../../pci/pci_wbw_fifo_control.v" |
add_file -verilog "../../../pci/pci_wbw_wbr_fifos.v" |
add_file -verilog "../../../pci/synchronizer_flop.v" |
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi.vhd" |
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBmaster.vhd" |
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_WBslave.vhd" |
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_control.vhd" |
add_file -vhdl -lib work "../../../../../rtl/vhdl/wb2hpi_interface.vhd" |
add_file -constraint "regPCI.sdc" |
|
#reporting options |
|
#implementation: "syn" |
impl -add syn |
|
#device options |
set_option -technology SPARTAN2 |
set_option -part XC2S200 |
set_option -package PQ208 |
set_option -speed_grade -5 |
|
#compilation/mapping options |
set_option -default_enum_encoding default |
set_option -symbolic_fsm_compiler 1 |
set_option -resource_sharing 0 |
set_option -use_fsm_explorer 1 |
set_option -top_module "TOP" |
|
#map options |
set_option -frequency 30.000 |
set_option -fanout_limit 32 |
set_option -disable_io_insertion 0 |
set_option -pipe 1 |
set_option -retiming 1 |
set_option -modular 0 |
|
#simulation options |
set_option -write_verilog 0 |
set_option -write_vhdl 0 |
|
#automatic place and route (vendor) options |
set_option -write_apr_constraint 1 |
|
#set result format/file last |
project -result_format "edif" |
project -log_file "../log/pci2dsp.log" |
project -result_file "../out/pci2dsp.edn" |
impl -active "syn" |
/tags/ver_1_0/apps/pci2dsp/syn/xilinxISE/ucf/pci2dsp.ucf
0,0 → 1,218
#************************** CVS history ***************************# |
# $Author: gvozden $ |
# $Date: 2003-02-28 14:10:54 $ |
# $Revision: 1.2 $ |
# $Name: not supported by cvs2svn $ |
#************************** CVS history ***************************# |
|
CONFIG PART = XC2S200-PQ208-5; |
|
NET "CLK" TNM_NET = "CLK"; |
TIMESPEC "TS_CLK" = PERIOD "CLK" 30 ns HIGH 50 %; |
|
INST "AD0.PAD" TNM = "PCI_AD"; |
INST "AD1.PAD" TNM = "PCI_AD"; |
INST "AD2.PAD" TNM = "PCI_AD"; |
INST "AD3.PAD" TNM = "PCI_AD"; |
INST "AD4.PAD" TNM = "PCI_AD"; |
INST "AD5.PAD" TNM = "PCI_AD"; |
INST "AD6.PAD" TNM = "PCI_AD"; |
INST "AD7.PAD" TNM = "PCI_AD"; |
INST "AD8.PAD" TNM = "PCI_AD"; |
INST "AD9.PAD" TNM = "PCI_AD"; |
INST "AD10.PAD" TNM = "PCI_AD"; |
INST "AD11.PAD" TNM = "PCI_AD"; |
INST "AD12.PAD" TNM = "PCI_AD"; |
INST "AD13.PAD" TNM = "PCI_AD"; |
INST "AD14.PAD" TNM = "PCI_AD"; |
INST "AD15.PAD" TNM = "PCI_AD"; |
INST "AD16.PAD" TNM = "PCI_AD"; |
INST "AD17.PAD" TNM = "PCI_AD"; |
INST "AD18.PAD" TNM = "PCI_AD"; |
INST "AD19.PAD" TNM = "PCI_AD"; |
INST "AD20.PAD" TNM = "PCI_AD"; |
INST "AD21.PAD" TNM = "PCI_AD"; |
INST "AD22.PAD" TNM = "PCI_AD"; |
INST "AD23.PAD" TNM = "PCI_AD"; |
INST "AD24.PAD" TNM = "PCI_AD"; |
INST "AD25.PAD" TNM = "PCI_AD"; |
INST "AD26.PAD" TNM = "PCI_AD"; |
INST "AD27.PAD" TNM = "PCI_AD"; |
INST "AD28.PAD" TNM = "PCI_AD"; |
INST "AD29.PAD" TNM = "PCI_AD"; |
INST "AD30.PAD" TNM = "PCI_AD"; |
INST "AD31.PAD" TNM = "PCI_AD"; |
|
TIMEGRP "PCI_AD" OFFSET = IN 7 ns BEFORE "CLK"; |
TIMEGRP "PCI_AD" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "AD0" IOSTANDARD = PCI33_5; |
NET "AD1" IOSTANDARD = PCI33_5; |
NET "AD2" IOSTANDARD = PCI33_5; |
NET "AD3" IOSTANDARD = PCI33_5; |
NET "AD4" IOSTANDARD = PCI33_5; |
NET "AD5" IOSTANDARD = PCI33_5; |
NET "AD6" IOSTANDARD = PCI33_5; |
NET "AD7" IOSTANDARD = PCI33_5; |
NET "AD8" IOSTANDARD = PCI33_5; |
NET "AD9" IOSTANDARD = PCI33_5; |
NET "AD10" IOSTANDARD = PCI33_5; |
NET "AD11" IOSTANDARD = PCI33_5; |
NET "AD12" IOSTANDARD = PCI33_5; |
NET "AD13" IOSTANDARD = PCI33_5; |
NET "AD14" IOSTANDARD = PCI33_5; |
NET "AD15" IOSTANDARD = PCI33_5; |
NET "AD16" IOSTANDARD = PCI33_5; |
NET "AD17" IOSTANDARD = PCI33_5; |
NET "AD18" IOSTANDARD = PCI33_5; |
NET "AD19" IOSTANDARD = PCI33_5; |
NET "AD20" IOSTANDARD = PCI33_5; |
NET "AD21" IOSTANDARD = PCI33_5; |
NET "AD22" IOSTANDARD = PCI33_5; |
NET "AD23" IOSTANDARD = PCI33_5; |
NET "AD24" IOSTANDARD = PCI33_5; |
NET "AD25" IOSTANDARD = PCI33_5; |
NET "AD26" IOSTANDARD = PCI33_5; |
NET "AD27" IOSTANDARD = PCI33_5; |
NET "AD28" IOSTANDARD = PCI33_5; |
NET "AD29" IOSTANDARD = PCI33_5; |
NET "AD30" IOSTANDARD = PCI33_5; |
NET "AD31" IOSTANDARD = PCI33_5; |
|
INST "CBE0.PAD" TNM = "PCI_CBE"; |
INST "CBE1.PAD" TNM = "PCI_CBE"; |
INST "CBE2.PAD" TNM = "PCI_CBE"; |
INST "CBE3.PAD" TNM = "PCI_CBE"; |
|
NET "CBE0" IOSTANDARD = PCI33_5; |
NET "CBE1" IOSTANDARD = PCI33_5; |
NET "CBE2" IOSTANDARD = PCI33_5; |
NET "CBE3" IOSTANDARD = PCI33_5; |
|
TIMEGRP "PCI_CBE" OFFSET = IN 7 ns BEFORE "CLK"; |
TIMEGRP "PCI_CBE" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "DEVSEL" IOSTANDARD = PCI33_5; |
NET "DEVSEL" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "DEVSEL" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "FRAME" IOSTANDARD = PCI33_5; |
NET "FRAME" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "FRAME" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "GNT" IOSTANDARD = PCI33_5; |
NET "GNT" OFFSET = IN 10 ns BEFORE "CLK"; |
|
NET "INTA" IOSTANDARD = PCI33_5; |
|
NET "RST" IOSTANDARD = PCI33_5; |
|
NET "IRDY" IOSTANDARD = PCI33_5; |
NET "IRDY" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "IRDY" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "PAR" IOSTANDARD = PCI33_5; |
NET "PAR" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "PAR" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "PERR" IOSTANDARD = PCI33_5; |
NET "PERR" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "PERR" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "REQ" IOSTANDARD = PCI33_5; |
NET "REQ" OFFSET = OUT 12 ns AFTER "CLK"; |
|
NET "SERR" IOSTANDARD = PCI33_5; |
NET "SERR" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "STOP" IOSTANDARD = PCI33_5; |
NET "STOP" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "STOP" OFFSET = OUT 11 ns AFTER "CLK"; |
|
NET "TRDY" IOSTANDARD = PCI33_5; |
NET "TRDY" OFFSET = IN 7 ns BEFORE "CLK"; |
NET "TRDY" OFFSET = OUT 10 ns AFTER "CLK"; |
|
NET "IDSEL" IOSTANDARD = PCI33_5; |
|
#################################################################### |
# Pin locations |
#################################################################### |
NET "CLK" LOC = "P185"; |
NET "INTA" LOC = "P195"; |
NET "RST" LOC = "P199"; |
NET "GNT" LOC = "P200"; |
NET "REQ" LOC = "P201"; |
|
NET "AD0" LOC = "P67"; |
NET "AD1" LOC = "P63"; |
NET "AD2" LOC = "P62"; |
NET "AD3" LOC = "P61"; |
NET "AD4" LOC = "P59"; |
NET "AD5" LOC = "P58"; |
NET "AD6" LOC = "P57"; |
NET "AD7" LOC = "P49"; |
NET "AD8" LOC = "P47"; |
NET "AD9" LOC = "P46"; |
NET "AD10" LOC = "P45"; |
NET "AD11" LOC = "P43"; |
NET "AD12" LOC = "P42"; |
NET "AD13" LOC = "P41"; |
NET "AD14" LOC = "P37"; |
NET "AD15" LOC = "P36"; |
NET "AD16" LOC = "P21"; |
NET "AD17" LOC = "P20"; |
NET "AD18" LOC = "P18"; |
NET "AD19" LOC = "P17"; |
NET "AD20" LOC = "P16"; |
NET "AD21" LOC = "P15"; |
NET "AD22" LOC = "P14"; |
NET "AD23" LOC = "P10"; |
NET "AD24" LOC = "P6"; |
NET "AD25" LOC = "P5"; |
NET "AD26" LOC = "P4"; |
NET "AD27" LOC = "P3"; |
NET "AD28" LOC = "P206"; |
NET "AD29" LOC = "P205"; |
NET "AD30" LOC = "P204"; |
NET "AD31" LOC = "P203"; |
|
NET "CBE0" LOC = "P48"; |
NET "CBE1" LOC = "P35"; |
NET "CBE2" LOC = "P22"; |
NET "CBE3" LOC = "P8"; |
|
NET "IDSEL" LOC = "P9"; |
NET "FRAME" LOC = "P23"; |
NET "IRDY" LOC = "P24"; |
NET "TRDY" LOC = "P27"; |
NET "DEVSEL" LOC = "P29"; |
NET "STOP" LOC = "P30"; |
NET "PERR" LOC = "P31"; |
NET "SERR" LOC = "P33"; |
NET "PAR" LOC = "P34"; |
|
NET "DSP_HINT" LOC = "P127"; |
NET "DSP_INT2" LOC = "P115"; |
NET "DSP_RST" LOC = "P101"; |
|
NET "DSP_HAD[0]" LOC = "P123"; |
NET "DSP_HAD[1]" LOC = "P112"; |
NET "DSP_HAD[2]" LOC = "P109"; |
NET "DSP_HAD[3]" LOC = "P102"; |
NET "DSP_HAD[4]" LOC = "P166"; |
NET "DSP_HAD[5]" LOC = "P165"; |
NET "DSP_HAD[6]" LOC = "P162"; |
NET "DSP_HAD[7]" LOC = "P161"; |
|
NET "DSP_HCNTL[0]" LOC = "P147"; |
NET "DSP_HCNTL[1]" LOC = "P139"; |
NET "DSP_HBIL" LOC = "P121"; |
NET "DSP_HCS" LOC = "P154"; |
NET "DSP_HDS1" LOC = "P164"; |
NET "DSP_HDS2" LOC = "P163"; |
NET "DSP_HRW" LOC = "P152"; |
NET "DSP_HRDY" LOC = "P125"; |
NET "DSP_HAS" LOC = "P160"; |
|
NET "LED" LOC = "P202"; |
/tags/ver_1_0/apps/pci2dsp/syn/xilinxISE/src/xilinx.npl
0,0 → 1,21
JDF E |
// Created by ISE ver 1.0 |
PROJECT xilinx |
DESIGN xilinx Normal |
DEVKIT xc2s200-5pq208 |
DEVFAM spartan2 |
FLOW EDIF |
MODULE ..\..\synplify\out\pci2dsp.edn |
MODSTYLE TOP Normal |
[STRATEGY-LIST] |
Normal=True, 1034858003 |
[Normal] |
xilxNgdbldUCF=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1038923296, ..\ucf\pci2dsp.ucf |
xilxMapPackRegInto=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1035374944, For Inputs and Outputs |
xilxPAReffortLevel=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, Highest |
xilxPARroutingPasses=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, 0 |
xilxPARdelayBasedPasses=edif, SPARTAN2, Implementation.t_placeAndRouteDes, 1027686394, 0 |
mpprStartingPlacerCostTbl=edif, SPARTAN2, Implementation.t_mppr, 1027686417, 20 |
mpprPARiterations=edif, SPARTAN2, Implementation.t_mppr, 1027687139, 0 |
mpprResultsToSave=edif, SPARTAN2, Implementation.t_mppr, 1027687139, 1 |
xilxBitgCfg_GenOpt_MaskFile=edif, SPARTAN2, Implementation.t_bitFile, 1034850741, True |
/tags/ver_1_0/apps/pci2dsp/syn/xilinxISE/src/README.txt
0,0 → 1,21
Just start Multipass Place & Route |
/tags/ver_1_0/apps/pci2dsp/rtl/verilog/top.v
0,0 → 1,534
////////////////////////////////////////////////////////////////////// |
//// //// |
//// File name "top.v" //// |
//// //// |
//// This file is part of the WB2HPI sample aplication //// |
//// (modified top.v from CRT - PCI Bridge sample application) //// |
//// //// |
//// http://www.opencores.org/cores/wb2hpi/ //// |
//// //// |
//// Author(s): //// |
//// - Gvozden Marinkovic (gvozden@opencores.org) //// |
//// - Dusko Krsmanovic (dusko@opencores.org) //// |
//// //// |
//// All additional information is avaliable in the README //// |
//// file. //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS History |
// |
// $Author: gvozden $ |
// $Date: 2003-03-18 14:38:34 $ |
// $Revision: 1.3 $ |
|
module TOP |
( |
CLK, |
RST, |
INTA, |
REQ, |
GNT, |
FRAME, |
IRDY, |
IDSEL, |
DEVSEL, |
TRDY, |
STOP, |
PAR, |
PERR, |
SERR, |
AD0, |
AD1, |
AD2, |
AD3, |
AD4, |
AD5, |
AD6, |
AD7, |
AD8, |
AD9, |
AD10, |
AD11, |
AD12, |
AD13, |
AD14, |
AD15, |
AD16, |
AD17, |
AD18, |
AD19, |
AD20, |
AD21, |
AD22, |
AD23, |
AD24, |
AD25, |
AD26, |
AD27, |
AD28, |
AD29, |
AD30, |
AD31, |
CBE0, |
CBE1, |
CBE2, |
CBE3, |
|
DSP_HAD, |
DSP_HCNTL, |
DSP_HBIL, |
DSP_HCS, |
DSP_HDS1, |
DSP_HDS2, |
DSP_HRW, |
DSP_HRDY, |
DSP_RST, |
DSP_HAS, |
DSP_HINT, |
DSP_INT2, |
|
LED |
); |
|
inout [ 7:0] DSP_HAD; |
output [ 1:0] DSP_HCNTL; |
output DSP_HBIL; |
output DSP_HCS; |
output DSP_HDS1; |
output DSP_HDS2; |
output DSP_HRW; |
input DSP_HRDY; |
output DSP_RST; |
output DSP_HAS; |
input DSP_HINT; |
output DSP_INT2; |
|
output LED; |
|
wire INT_REQ; |
|
input CLK ; |
inout AD0, |
AD1, |
AD2, |
AD3, |
AD4, |
AD5, |
AD6, |
AD7, |
AD8, |
AD9, |
AD10, |
AD11, |
AD12, |
AD13, |
AD14, |
AD15, |
AD16, |
AD17, |
AD18, |
AD19, |
AD20, |
AD21, |
AD22, |
AD23, |
AD24, |
AD25, |
AD26, |
AD27, |
AD28, |
AD29, |
AD30, |
AD31 ; |
|
inout CBE0, |
CBE1, |
CBE2, |
CBE3 ; |
|
inout RST ; |
inout INTA ; |
output REQ ; |
input GNT ; |
inout FRAME ; |
inout IRDY ; |
input IDSEL ; |
inout DEVSEL ; |
inout TRDY ; |
inout STOP ; |
inout PAR ; |
inout PERR ; |
output SERR ; |
|
// WISHBONE system signals |
wire RST_I = 1'b0 ; |
wire RST_O ; |
wire INT_I = 1'b0 ; |
wire INT_O ; |
|
wire [15:0] rgb_int ; |
// WISHBONE slave interface |
wire [31:0] ADR_I ; |
wire [31:0] SDAT_I ; |
wire [31:0] SDAT_O ; |
wire [3:0] SEL_I ; |
wire CYC_I ; |
wire STB_I ; |
wire WE_I ; |
wire CAB_I ; |
wire ACK_O ; |
wire RTY_O ; |
wire ERR_O ; |
|
// WISHBONE master interface |
wire [31:0] ADR_O ; |
wire [31:0] MDAT_I ; |
wire [31:0] MDAT_O ; |
wire [3:0] SEL_O ; |
wire CYC_O ; |
wire STB_O ; |
wire WE_O ; |
wire CAB_O ; |
wire ACK_I ; |
wire RTY_I ; |
wire ERR_I ; |
|
wire [31:0] AD_out ; |
wire [31:0] AD_en ; |
|
|
wire [31:0] AD_in = |
{ |
AD31, |
AD30, |
AD29, |
AD28, |
AD27, |
AD26, |
AD25, |
AD24, |
AD23, |
AD22, |
AD21, |
AD20, |
AD19, |
AD18, |
AD17, |
AD16, |
AD15, |
AD14, |
AD13, |
AD12, |
AD11, |
AD10, |
AD9, |
AD8, |
AD7, |
AD6, |
AD5, |
AD4, |
AD3, |
AD2, |
AD1, |
AD0 |
} ; |
|
wire [3:0] CBE_in = |
{ |
CBE3, |
CBE2, |
CBE1, |
CBE0 |
} ; |
|
wire [3:0] CBE_out ; |
wire [3:0] CBE_en ; |
|
|
|
wire RST_in = RST ; |
wire RST_out ; |
wire RST_en ; |
|
wire INTA_in = INTA ; |
wire INTA_en ; |
wire INTA_out ; |
|
wire REQ_en ; |
wire REQ_out ; |
|
wire FRAME_in = FRAME ; |
wire FRAME_out ; |
wire FRAME_en ; |
|
wire IRDY_in = IRDY ; |
wire IRDY_out ; |
wire IRDY_en ; |
|
wire DEVSEL_in = DEVSEL ; |
wire DEVSEL_out ; |
wire DEVSEL_en ; |
|
wire TRDY_in = TRDY ; |
wire TRDY_out ; |
wire TRDY_en ; |
|
wire STOP_in = STOP ; |
wire STOP_out ; |
wire STOP_en ; |
|
wire PAR_in = PAR ; |
wire PAR_out ; |
wire PAR_en ; |
|
wire PERR_in = PERR ; |
wire PERR_out ; |
wire PERR_en ; |
|
wire SERR_out ; |
wire SERR_en ; |
|
wire [ 7:0] DSP_HAD_in = DSP_HAD; |
wire [ 7:0] DSP_HAD_out; |
wire DSP_HAD_en; |
|
pci_bridge32 bridge |
( |
// WISHBONE system signals |
.wb_clk_i(CLK), |
.wb_rst_i(RST_I), |
.wb_rst_o(RST_O), |
.wb_int_i(INT_I), |
.wb_int_o(INT_O), |
|
// WISHBONE slave interface |
.wbs_adr_i(ADR_I), |
.wbs_dat_i(SDAT_I), |
.wbs_dat_o(SDAT_O), |
.wbs_sel_i(SEL_I), |
.wbs_cyc_i(CYC_I), |
.wbs_stb_i(STB_I), |
.wbs_we_i (WE_I), |
.wbs_cab_i(CAB_I), |
.wbs_ack_o(ACK_O), |
.wbs_rty_o(RTY_O), |
.wbs_err_o(ERR_O), |
|
// WISHBONE master interface |
.wbm_adr_o(ADR_O), |
.wbm_dat_i(MDAT_I), |
.wbm_dat_o(MDAT_O), |
.wbm_sel_o(SEL_O), |
.wbm_cyc_o(CYC_O), |
.wbm_stb_o(STB_O), |
.wbm_we_o (WE_O), |
.wbm_cab_o(CAB_O), |
.wbm_ack_i(ACK_I), |
.wbm_rty_i(RTY_I), |
.wbm_err_i(ERR_I), |
|
// pci interface - system pins |
.pci_clk_i ( CLK ), |
.pci_rst_i ( RST_in ), |
.pci_rst_o ( RST_out ), |
.pci_inta_i ( INTA_in ), |
.pci_inta_o ( INTA_out), |
.pci_rst_oe_o ( RST_en), |
.pci_inta_oe_o( INTA_en ), |
|
// arbitration pins |
.pci_req_o ( REQ_out ), |
.pci_req_oe_o( REQ_en ), |
|
.pci_gnt_i ( GNT ), |
|
// protocol pins |
.pci_frame_i ( FRAME_in), |
.pci_frame_o ( FRAME_out ), |
|
.pci_frame_oe_o ( FRAME_en ), |
.pci_irdy_oe_o ( IRDY_en ), |
.pci_devsel_oe_o ( DEVSEL_en ), |
.pci_trdy_oe_o ( TRDY_en ), |
.pci_stop_oe_o ( STOP_en ), |
.pci_ad_oe_o ( AD_en ), |
.pci_cbe_oe_o ( CBE_en) , |
|
.pci_irdy_i ( IRDY_in ), |
.pci_irdy_o ( IRDY_out ), |
|
.pci_idsel_i ( IDSEL ), |
|
.pci_devsel_i ( DEVSEL_in ), |
.pci_devsel_o ( DEVSEL_out ), |
|
.pci_trdy_i ( TRDY_in ), |
.pci_trdy_o ( TRDY_out ), |
|
.pci_stop_i ( STOP_in ), |
.pci_stop_o ( STOP_out ), |
|
// data transfer pins |
.pci_ad_i (AD_in), |
.pci_ad_o (AD_out), |
|
.pci_cbe_i( CBE_in ), |
.pci_cbe_o( CBE_out ), |
|
// parity generation and checking pins |
.pci_par_i ( PAR_in ), |
.pci_par_o ( PAR_out ), |
.pci_par_oe_o ( PAR_en ), |
|
.pci_perr_i ( PERR_in ), |
.pci_perr_o ( PERR_out ), |
.pci_perr_oe_o( PERR_en ), |
|
// system error pin |
.pci_serr_o ( SERR_out ), |
.pci_serr_oe_o( SERR_en ) |
); |
|
// PCI IO buffers instantiation |
bufif0 AD_buf0 ( AD0, AD_out[0], AD_en[0]) ; |
bufif0 AD_buf1 ( AD1, AD_out[1], AD_en[1]) ; |
bufif0 AD_buf2 ( AD2, AD_out[2], AD_en[2]) ; |
bufif0 AD_buf3 ( AD3, AD_out[3], AD_en[3]) ; |
bufif0 AD_buf4 ( AD4, AD_out[4], AD_en[4]) ; |
bufif0 AD_buf5 ( AD5, AD_out[5], AD_en[5]) ; |
bufif0 AD_buf6 ( AD6, AD_out[6], AD_en[6]) ; |
bufif0 AD_buf7 ( AD7, AD_out[7], AD_en[7]) ; |
bufif0 AD_buf8 ( AD8, AD_out[8], AD_en[8]) ; |
bufif0 AD_buf9 ( AD9, AD_out[9], AD_en[9]) ; |
bufif0 AD_buf10 ( AD10, AD_out[10],AD_en[10] ) ; |
bufif0 AD_buf11 ( AD11, AD_out[11],AD_en[11] ) ; |
bufif0 AD_buf12 ( AD12, AD_out[12],AD_en[12] ) ; |
bufif0 AD_buf13 ( AD13, AD_out[13],AD_en[13] ) ; |
bufif0 AD_buf14 ( AD14, AD_out[14],AD_en[14] ) ; |
bufif0 AD_buf15 ( AD15, AD_out[15],AD_en[15] ) ; |
bufif0 AD_buf16 ( AD16, AD_out[16],AD_en[16] ) ; |
bufif0 AD_buf17 ( AD17, AD_out[17],AD_en[17] ) ; |
bufif0 AD_buf18 ( AD18, AD_out[18],AD_en[18] ) ; |
bufif0 AD_buf19 ( AD19, AD_out[19],AD_en[19] ) ; |
bufif0 AD_buf20 ( AD20, AD_out[20],AD_en[20] ) ; |
bufif0 AD_buf21 ( AD21, AD_out[21],AD_en[21] ) ; |
bufif0 AD_buf22 ( AD22, AD_out[22],AD_en[22] ) ; |
bufif0 AD_buf23 ( AD23, AD_out[23],AD_en[23] ) ; |
bufif0 AD_buf24 ( AD24, AD_out[24],AD_en[24] ) ; |
bufif0 AD_buf25 ( AD25, AD_out[25],AD_en[25] ) ; |
bufif0 AD_buf26 ( AD26, AD_out[26],AD_en[26] ) ; |
bufif0 AD_buf27 ( AD27, AD_out[27],AD_en[27] ) ; |
bufif0 AD_buf28 ( AD28, AD_out[28],AD_en[28] ) ; |
bufif0 AD_buf29 ( AD29, AD_out[29],AD_en[29] ) ; |
bufif0 AD_buf30 ( AD30, AD_out[30],AD_en[30] ) ; |
bufif0 AD_buf31 ( AD31, AD_out[31],AD_en[31] ) ; |
|
bufif0 CBE_buf0 ( CBE0, CBE_out[0], CBE_en[0] ) ; |
bufif0 CBE_buf1 ( CBE1, CBE_out[1], CBE_en[1] ) ; |
bufif0 CBE_buf2 ( CBE2, CBE_out[2], CBE_en[2] ) ; |
bufif0 CBE_buf3 ( CBE3, CBE_out[3], CBE_en[3] ) ; |
|
bufif0 FRAME_buf ( FRAME, FRAME_out, FRAME_en ) ; |
bufif0 IRDY_buf ( IRDY, IRDY_out, IRDY_en ) ; |
bufif0 DEVSEL_buf ( DEVSEL, DEVSEL_out, DEVSEL_en ) ; |
bufif0 TRDY_buf ( TRDY, TRDY_out, TRDY_en ) ; |
bufif0 STOP_buf ( STOP, STOP_out, STOP_en ) ; |
|
bufif0 RST_buf ( RST, RST_out, RST_en ) ; |
bufif0 INTA_buf ( INTA, INTA_out, INTA_en) ; |
bufif0 REQ_buf ( REQ, REQ_out, REQ_en ) ; |
bufif0 PAR_buf ( PAR, PAR_out, PAR_en ) ; |
bufif0 PERR_buf ( PERR, PERR_out, PERR_en ) ; |
bufif0 SERR_buf ( SERR, SERR_out, SERR_en ) ; |
|
bufif0 DSP_HAD_buf0 (DSP_HAD[0], DSP_HAD_out[0], DSP_HAD_en); |
bufif0 DSP_HAD_buf1 (DSP_HAD[1], DSP_HAD_out[1], DSP_HAD_en); |
bufif0 DSP_HAD_buf2 (DSP_HAD[2], DSP_HAD_out[2], DSP_HAD_en); |
bufif0 DSP_HAD_buf3 (DSP_HAD[3], DSP_HAD_out[3], DSP_HAD_en); |
bufif0 DSP_HAD_buf4 (DSP_HAD[4], DSP_HAD_out[4], DSP_HAD_en); |
bufif0 DSP_HAD_buf5 (DSP_HAD[5], DSP_HAD_out[5], DSP_HAD_en); |
bufif0 DSP_HAD_buf6 (DSP_HAD[6], DSP_HAD_out[6], DSP_HAD_en); |
bufif0 DSP_HAD_buf7 (DSP_HAD[7], DSP_HAD_out[7], DSP_HAD_en); |
|
wb2hpi WB2HPI |
( |
// Clock and reset |
.WB_CLK_I (CLK), |
.WB_RST_I (RST_O), |
|
// WISHBONE Master I/F |
.WBM_CYC_O (CYC_I), |
.WBM_STB_O (STB_I), |
.WBM_SEL_O (SEL_I), |
.WBM_WE_O (WE_I), |
.WBM_ADR_O (ADR_I), |
.WBM_DAT_O (SDAT_I), |
.WBM_CAB_O (CAB_I), |
.WBM_DAT_I (SDAT_O), |
.WBM_ACK_I (ACK_O), |
.WBM_ERR_I (ERR_O), |
.WBM_RTY_I (RTY_O), |
|
// WISHBONE Slave I/F |
.WBS_CYC_I (CYC_O), |
.WBS_STB_I (STB_O), |
.WBS_SEL_I (SEL_O), |
.WBS_WE_I (WE_O), |
.WBS_ADR_I (ADR_O), |
.WBS_DAT_I (MDAT_O), |
.WBS_CAB_I (CAB_O), |
.WBS_DAT_O (MDAT_I), |
.WBS_ACK_O (ACK_I), |
.WBS_ERR_O (ERR_I), |
.WBS_RTY_O (RTY_I), |
|
//To PCI |
.INT_REQ (INT_REQ), |
|
//54x DSP_HPI8 Signals |
.DSP_HAD_I (DSP_HAD_in), |
.DSP_HAD_O (DSP_HAD_out), |
.DSP_HAD_ENn (DSP_HAD_en), |
|
.DSP_HCNTL_PAD_O (DSP_HCNTL), |
.DSP_HBIL_PAD_O (DSP_HBIL), |
.DSP_HCS_PAD_O (DSP_HCS), |
.DSP_HDS1_PAD_O (DSP_HDS1), |
.DSP_HDS2_PAD_O (DSP_HDS2), |
.DSP_HRW_PAD_O (DSP_HRW), |
.DSP_HRDY_PAD_I (DSP_HRDY), |
.DSP_RST_PAD_O (DSP_RST), |
.DSP_HAS_PAD_O (DSP_HAS), |
.DSP_HINT_PAD_I (DSP_HINT), |
.DSP_INT2_PAD_O (DSP_INT2), |
|
.LED (LED) |
); |
endmodule |
/tags/ver_1_0/apps/pci2dsp/pci/README.TXT
0,0 → 1,65
Put Opencores PCI core here: |
------------------------------------------------- |
pci_user_constants.v |
pci_target_unit.v |
pci_target32_trdy_crit.v |
pci_target32_stop_crit.v |
pci_target32_sm.v |
pci_target32_interface.v |
pci_target32_devs_crit.v |
pci_target32_clk_en.v |
pci_rst_int.v |
pci_parity_check.v |
pci_master32_sm_if.v |
pci_master32_sm.v |
pci_io_mux_ad_load_crit.v |
pci_io_mux_ad_en_crit.v |
pci_io_mux.v |
pci_in_reg.v |
pci_bridge32.v |
pci_serr_en_crit.v |
pci_serr_crit.v |
pci_perr_en_crit.v |
pci_perr_crit.v |
pci_par_crit.v |
pci_wbw_wbr_fifos.v |
pci_wb_master.v |
pci_pciw_pcir_fifos.v |
pci_wbw_fifo_control.v |
pci_wbr_fifo_control.v |
pci_wb_tpram.v |
pci_wb_slave_unit.v |
pci_wb_slave.v |
pci_wb_decoder.v |
pci_wb_addr_mux.v |
pci_sync_module.v |
pci_pciw_fifo_control.v |
pci_pcir_fifo_control.v |
pci_pci_tpram.v |
pci_pci_decoder.v |
pci_out_reg.v |
pci_mas_ch_state_crit.v |
pci_mas_ad_load_crit.v |
pci_mas_ad_en_crit.v |
pci_irdy_out_crit.v |
pci_frame_load_crit.v |
pci_frame_en_crit.v |
pci_frame_crit.v |
pci_delayed_write_reg.v |
pci_delayed_sync.v |
pci_cur_out_reg.v |
pci_conf_space.v |
pci_conf_cyc_addr_dec.v |
pci_cbe_en_crit.v |
pci_async_reset_flop.v |
bus_commands.v |
meta_flop.v |
pci_ram_16x40d.v |
timescale.v |
synchronizer_flop.v |
pci_constants.v |
|
Put library files here: |
------------------------------------------------- |
virtex.v |
|
/tags/ver_1_0/apps/pci2dsp/pci/pci_user_constants.v
0,0 → 1,209
////////////////////////////////////////////////////////////////////// |
//// //// |
//// File name "pci_user_constants.v" //// |
//// //// |
//// This file is part of the "PCI bridge" project //// |
//// http://www.opencores.org/cores/pci/ //// |
//// //// |
//// Author(s): //// |
//// - Miha Dolenc (mihad@opencores.org) //// |
//// - Tadej Markovic (tadej@opencores.org) //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Author: gvozden $ |
// $Date: 2003-01-16 18:06:03 $ |
// $Revision: 1.1.1.1 $ |
|
// Fifo implementation defines: |
// If FPGA and XILINX are defined, Xilinx's BlockSelectRAM+ is instantiated for Fifo storage. |
// 16 bit width is used, so 8 bits of address ( 256 ) locations are available. If RAM_DONT_SHARE is not defined (commented out), |
// then one block RAM is shared between two FIFOs. That means each Fifo can have a maximum address length of 7 - depth of 128 and only 6 block rams are used |
// If RAM_DONT_SHARE is defined ( not commented out ), then 12 block RAMs are used and each Fifo can have a maximum address length of 8 ( 256 locations ) |
// If FPGA is not defined, then ASIC RAMs are used. Currently there is only one version of ARTISAN RAM supported. User should generate synchronous RAM with |
// width of 40 and instantiate it in pci_tpram.v. If RAM_DONT_SHARE is defined, then these can be dual port rams ( write port |
// in one clock domain, read in other ), otherwise it must be two port RAM ( read and write ports in both clock domains ). |
// If RAM_DONT_SHARE is defined, then all RAM address lengths must be specified accordingly, otherwise there are two relevant lengths - PCI_FIFO_RAM_ADDR_LENGTH and |
// WB_FIFO_RAM_ADDR_LENGTH. |
|
`define WBW_ADDR_LENGTH 3 |
`define WBR_ADDR_LENGTH 6 |
`define PCIW_ADDR_LENGTH 4 |
`define PCIR_ADDR_LENGTH 4 |
|
`define FPGA |
`define XILINX |
|
//`define WB_RAM_DONT_SHARE |
`define PCI_RAM_DONT_SHARE |
|
`ifdef FPGA |
`ifdef XILINX |
`define PCI_FIFO_RAM_ADDR_LENGTH 4 // PCI target unit fifo storage definition |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition |
//`define PCI_XILINX_RAMB4 |
`define WB_XILINX_RAMB4 |
`define PCI_XILINX_DIST_RAM |
//`define WB_XILINX_DIST_RAM |
`endif |
`else |
`define PCI_FIFO_RAM_ADDR_LENGTH 8 // PCI target unit fifo storage definition when RAM sharing is used ( both pcir and pciw fifo use same instance of RAM ) |
`define WB_FIFO_RAM_ADDR_LENGTH 8 // WB slave unit fifo storage definition when RAM sharing is used ( both wbr and wbw fifo use same instance of RAM ) |
`define WB_ARTISAN_SDP |
`define PCI_ARTISAN_SDP |
`endif |
|
// these two defines allow user to select active high or low output enables on PCI bus signals, depending on |
// output buffers instantiated. Xilinx FPGAs use active low output enables. |
`define ACTIVE_LOW_OE |
//`define ACTIVE_HIGH_OE |
|
// HOST/GUEST implementation selection - see design document and specification for description of each implementation |
// only one can be defined at same time |
`define GUEST |
//`define HOST |
|
// if NO_CNF_IMAGE is commented out, then READ-ONLY access to configuration space is ENABLED: |
// - ENABLED Read-Only access from WISHBONE for GUEST bridges |
// - ENABLED Read-Only access from PCI for HOST bridges |
// with defining NO_CNF_IMAGE, one decoder and one multiplexer are saved |
`define NO_CNF_IMAGE |
|
// number defined here specifies how many MS bits in PCI address are compared with base address, to decode |
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number |
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of PCI images, |
// you have to define a number of minimum sized image and enlarge others by specifying different address mask. |
// smaller the number here, faster the decoder operation |
`define PCI_NUM_OF_DEC_ADDR_LINES 12 |
|
// no. of PCI Target IMAGES |
// - PCI provides 6 base address registers for image implementation. |
// PCI_IMAGE1 definition is not required and has no effect, since PCI image 1 is always implemented |
// If GUEST is defined, PCI Image 0 is also always implemented and is used for configuration space |
// access. |
// If HOST is defined and NO_CNF_IMAGE is not, then PCI Image 0 is used for Read Only access to configuration |
// space. If HOST is defined and NO_CNF_IMAGE is defined, then user can define PCI_IMAGE0 as normal image, and there |
// is no access to Configuration space possible from PCI bus. |
// Implementation of all other PCI images is selected by defining PCI_IMAGE2 through PCI_IMAGE5 regardles of HOST |
// or GUEST implementation. |
`ifdef HOST |
`ifdef NO_CNF_IMAGE |
//`define PCI_IMAGE0 |
`endif |
`endif |
|
//`define PCI_IMAGE2 |
//`define PCI_IMAGE3 |
//`define PCI_IMAGE4 |
//`define PCI_IMAGE5 |
|
// initial value for PCI image address masks. Address masks can be defined in enabled state, |
// to allow device independent software to detect size of image and map base addresses to |
// memory space. If initial mask for an image is defined as 0, then device independent software |
// won't detect base address implemented and device dependent software will have to configure |
// address masks as well as base addresses! |
`define PCI_AM0 20'hffff_f |
`define PCI_AM1 20'hffff_f |
`define PCI_AM2 20'hffff_f |
`define PCI_AM3 20'hffff_f |
`define PCI_AM4 20'hffff_f |
`define PCI_AM5 20'hffff_f |
|
// initial value for PCI image maping to MEMORY or IO spaces. If initial define is set to 0, |
// then IMAGE with that base address points to MEMORY space, othervise it points ti IO space. D |
// Device independent software sets the base addresses acording to MEMORY or IO maping! |
`define PCI_BA0_MEM_IO 1'b0 // considered only when PCI_IMAGE0 is used as general PCI-WB image! |
`define PCI_BA1_MEM_IO 1'b0 |
`define PCI_BA2_MEM_IO 1'b0 |
`define PCI_BA3_MEM_IO 1'b0 |
`define PCI_BA4_MEM_IO 1'b0 |
`define PCI_BA5_MEM_IO 1'b0 |
|
// number defined here specifies how many MS bits in WB address are compared with base address, to decode |
// accesses. Maximum number allows for minimum image size ( number = 20, image size = 4KB ), minimum number |
// allows for maximum image size ( number = 1, image size = 2GB ). If you intend on using different sizes of WB images, |
// you have to define a number of minimum sized image and enlarge others by specifying different address mask. |
// smaller the number here, faster the decoder operation |
`define WB_NUM_OF_DEC_ADDR_LINES 1 |
|
// no. of WISHBONE Slave IMAGES |
// WB image 0 is always used for access to configuration space. In case configuration space access is not implemented, |
// ( both GUEST and NO_CNF_IMAGE defined ), then WB image 0 is not implemented. User doesn't need to define image 0. |
// WB Image 1 is always implemented and user doesnt need to specify its definition |
// WB images' 2 through 5 implementation by defining each one. |
//`define WB_IMAGE2 |
//`define WB_IMAGE3 |
//`define WB_IMAGE4 |
//`define WB_IMAGE5 |
|
// If this define is commented out, then address translation will not be implemented. |
// addresses will pass through bridge unchanged, regardles of address translation enable bits. |
// Address translation also slows down the decoding |
//`define ADDR_TRAN_IMPL |
|
// decode speed for WISHBONE definition - initial cycle on WISHBONE bus will take 1 WS for FAST, 2 WSs for MEDIUM and 3 WSs for slow. |
// slower decode speed can be used, to provide enough time for address to be decoded. |
`define WB_DECODE_FAST |
//`define WB_DECODE_MEDIUM |
//`define WB_DECODE_SLOW |
|
// Base address for Configuration space access from WB bus. This value cannot be changed during runtime |
`define WB_CONFIGURATION_BASE 20'h0000_0 |
|
// Turn registered WISHBONE slave outputs on or off |
// all outputs from WB Slave state machine are registered, if this is defined - WB bus outputs as well as |
// outputs to internals of the core. |
//`define REGISTER_WBS_OUTPUTS |
|
/*----------------------------------------------------------------------------------------------------------- |
Core speed definition - used for simulation and 66MHz Capable bit value in status register indicating 66MHz |
capable device |
-----------------------------------------------------------------------------------------------------------*/ |
`define PCI33 |
//`define PCI66 |
|
/*----------------------------------------------------------------------------------------------------------- |
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type ! |
Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g. |
Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used |
together by application. |
-----------------------------------------------------------------------------------------------------------*/ |
`define HEADER_VENDOR_ID 16'h2321 |
`define HEADER_DEVICE_ID 16'h0001 |
`define HEADER_REVISION_ID 8'h01 |
|
// Turn registered WISHBONE master outputs on or off |
// all outputs from WB Master state machine are registered, if this is defined - WB bus outputs as well as |
// outputs to internals of the core. |
//`define REGISTER_WBM_OUTPUTS |
|
// MAX Retry counter value for WISHBONE Master state-machine |
// This value is 8-bit because of 8-bit retry counter !!! |
`define WB_RTY_CNT_MAX 8'hff |
/tags/ver_1_0/rtl/vhdl/wb2hpi_WBmaster.vhd
0,0 → 1,319
---------------------------------------------------------------------- |
---- ---- |
---- File name "wb2hpi_WBmaster.vhd" ---- |
---- ---- |
---- This file is part of the "WB2HPI" project ---- |
---- http://www.opencores.org/cores/wb2hpi/ ---- |
---- ---- |
---- Author(s): ---- |
---- - Gvozden Marinkovic (gvozden@opencores.org) ---- |
---- - Dusko Krsmanovic (dusko@opencores.org) ---- |
---- ---- |
---- All additional information is avaliable in the README ---- |
---- file. ---- |
---- ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
--==================================================================-- |
-- Design : wb2hpi_WBmaster |
-- ( entity i architecture ) |
-- |
-- File : wb2hpi_WBmaster.vhd |
-- |
-- Errors : |
-- |
-- Library : ieee.std_logic_1164 |
-- ieee.std_logic_arith.all; |
-- ieee.std_logic_unsigned.all; |
-- |
-- Dependency : |
-- |
-- Author : Gvozden Marinkovic |
-- mgvozden@eunet.yu |
-- |
-- Simulators : ActiveVHDL 3.5 on a WindowsXP PC |
---------------------------------------------------------------------- |
-- Description : WB Master for WB2HPI application |
---------------------------------------------------------------------- |
-- Copyright (c) 2002 Gvozden Marinkovic |
-- |
-- This VHDL design file is an open design; you can redistribute it |
-- and/or modify it and/or implement it after contacting the author |
--==================================================================-- |
|
--************************** CVS history ***************************-- |
-- $Author: gvozden $ |
-- $Date: 2003-01-16 18:06:20 $ |
-- $Revision: 1.1.1.1 $ |
-- $Name: not supported by cvs2svn $ |
--************************** CVS history ***************************-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_arith.all; |
use ieee.std_logic_unsigned.all; |
|
---------------------------------------------------------------------- |
-- entity wb2hpi_WBmaster |
---------------------------------------------------------------------- |
entity wb2hpi_WBmaster is |
generic ( |
MAX_RTY : natural range 0 to 255 := 255 |
); |
port ( |
-- WISHBONE common signals |
WB_CLK_I : in std_logic; -- Clock |
WB_RST_I : in std_logic; -- Reset |
|
-- WISHBONE MASTER signals |
WBM_ACK_I : in std_logic; -- Acknowledge |
WBM_ERR_I : in std_logic; -- Error |
WBM_RTY_I : in std_logic; -- Retry |
WBM_DAT_I : in std_logic_vector(31 downto 0); -- Data input |
WBM_CYC_O : out std_logic; -- Cycle in progress |
WBM_STB_O : out std_logic; -- Strobe |
WBM_WE_O : out std_logic; -- Write enable |
WBM_CAB_O : out std_logic; -- |
WBM_ADR_O : out std_logic_vector(31 downto 0); -- Address |
WBM_DAT_O : out std_logic_vector(31 downto 0); -- Data output |
WBM_SEL_O : out std_logic_vector(3 downto 0); -- Select |
|
-- From HPI Interface |
pci_address : in std_logic_vector(31 downto 1); -- PCI Address |
pci_counter : in std_logic_vector(15 downto 0); -- Number of bytes for transfer |
pci_data_in : in std_logic_vector(15 downto 0); -- Data |
start_write : in std_logic; -- Start PCI write |
start_read : in std_logic; -- Start PCI read |
|
-- To WB Slave |
pci_error : out std_logic; -- PCI error |
|
-- To HPI Interface |
ready : out std_logic; -- Ready |
pci_data_out : out std_logic_vector(15 downto 0); -- Data |
pci_get_next : out std_logic -- Get next word |
); |
end entity wb2hpi_WBmaster; |
|
---------------------------------------------------------------------- |
-- architecture wb2hpi_WBmaster |
---------------------------------------------------------------------- |
architecture behavioral of wb2hpi_WBmaster is |
|
---------------------------------------------------------------------- |
-- type declaration |
---------------------------------------------------------------------- |
type wbm_state is (IDLE, INIT_WRITE, INIT_READ, END_STATE, |
WRITE_DATA, READ_DATA); -- WB Master states |
|
---------------------------------------------------------------------- |
-- signal declaration |
---------------------------------------------------------------------- |
signal current_state, next_state: wbm_state; |
signal wbm_adr : std_logic_vector(31 downto 1); |
signal wbm_strobe : std_logic; |
signal wbm_cyc : std_logic; |
signal finished : std_logic; |
signal pci_err : std_logic; |
signal odd_word : std_logic; |
|
begin -- architecture Behavioral of myWBMaster |
WBM_CAB_O <= '1'; |
|
-- purpose: finite state machines |
-- type : sequential |
-- inputs : WB_CLK_I, WB_RST_I, next_state |
-- outputs: current_state |
fsm_set_state: process (WB_CLK_I, WB_RST_I, next_state) is |
begin |
if (WB_RST_I = '1') then |
current_state <= IDLE; |
elsif rising_edge(WB_CLK_I) then |
current_state <= next_state; |
end if; |
end process fsm_set_state; |
|
-- purpose: fsm combination input/output logic |
-- type : combinational |
-- inputs : current_state |
-- outputs: next_state |
fsm_set_next: process (current_state, start_write, start_read, finished) is |
begin |
next_state <= IDLE; |
case (current_state) is |
when IDLE => |
if start_write = '1' then |
next_state <= INIT_WRITE; |
elsif start_read = '1' then |
next_state <= INIT_READ; |
end if; |
when INIT_WRITE => |
next_state <= WRITE_DATA; |
when INIT_READ => |
next_state <= READ_DATA; |
when WRITE_DATA => |
if (finished = '1') then |
next_state <= END_STATE; |
else |
next_state <= WRITE_DATA; |
end if; |
when READ_DATA => |
if (finished = '1') then |
next_state <= END_STATE; |
else |
next_state <= READ_DATA; |
end if; |
when others => null; |
end case; |
end process fsm_set_next; |
|
-- purpose: prepare next address and data |
-- type : sequential |
-- inputs : WB_RST_I, WB_CLK_I, next_state, WBM_ACK_I, wbm_strobe |
-- outputs: wbm_adr, odd_word, pci_get_next, finished |
set_finished: process (WB_RST_I, WB_CLK_I) is |
begin |
if (WB_RST_I = '1') then |
wbm_adr <= (others => '0'); |
odd_word <= '0'; |
finished <= '0'; |
pci_get_next <= '0'; |
elsif rising_edge (WB_CLK_I) then |
pci_get_next <= '0'; |
case (next_state) is |
when INIT_WRITE | INIT_READ=> |
wbm_adr <= pci_address; |
odd_word <= pci_address(1); |
finished <= '0'; |
when WRITE_DATA | READ_DATA => |
if (WBM_ACK_I = '1' and wbm_strobe = '1') then |
pci_get_next <= '1'; |
finished <= '1'; |
end if; |
when others => null; |
end case; |
end if; |
end process set_finished; |
|
-- purpose: set output data |
-- type : combinational |
-- inputs : pci_data_in, odd_word |
-- outputs: WBM_DAT_O |
set_data:process (pci_data_in, odd_word) is |
begin |
WBM_DAT_O <= (others => '0'); |
if (odd_word = '1') then |
WBM_DAT_O(31 downto 16) <= pci_data_in; |
else |
WBM_DAT_O(15 downto 0) <= pci_data_in; |
end if; |
end process set_data; |
|
-- purpose: get input data |
-- type : sequential |
-- inputs : WBM_DAT_I, WBM_ACK_I, wbm_strobe, odd_word |
-- outputs: pci_data_out |
get_data: process (WB_RST_I, WB_CLK_I) is |
begin |
if (WB_RST_I = '1') then |
pci_data_out <= (others => '0'); |
elsif rising_edge (WB_CLK_I) then |
if (WBM_ACK_I = '1' and wbm_strobe = '1') then |
if (odd_word = '1') then |
pci_data_out <= WBM_DAT_I(31 downto 16); |
else |
pci_data_out <= WBM_DAT_I(15 downto 0); |
end if; |
end if; |
end if; |
end process get_data; |
|
|
-- purpose: Retry counter. Just signalize PCI error |
-- type : sequential |
-- inputs : WB_RST_I, WB_CLK_I, current_state |
-- outputs: pci_err |
count_rty: process(WB_RST_I, WB_CLK_I, current_state) is |
variable rty_cnt: natural range 0 to MAX_RTY; |
begin |
if (WB_RST_I = '1' or current_state = INIT_WRITE or |
current_state = INIT_READ) then |
rty_cnt := MAX_RTY; |
pci_err <= '0'; |
elsif rising_edge(WB_CLK_I) then |
if (WBM_RTY_I = '1') then |
if (rty_cnt = 0) then |
pci_err <= '1'; |
else |
rty_cnt := rty_cnt - 1; |
end if; |
end if; |
end if; |
end process count_rty; |
|
-- purpose: propagate pci error flag to WB Slave |
-- type : combinational |
-- inputs : pci_err |
-- outputs: pci_error |
pci_error <= pci_err; |
|
|
-- purpose: WB master is ready |
-- type : combinational |
-- inputs : current_state |
-- outputs: ready |
ready <= '1' when current_state = IDLE else '0'; |
|
-- purpose: WB control signals |
-- type : combinational |
-- inputs : current_state, wbm_adr, wbm_strobe |
-- outputs: WBM_WE_O, WBM_ADR_O, WBM_STB_O, WBM_CYC_O, WBM_SEL_O |
wbm_cyc <= '1' when current_state = WRITE_DATA or current_state = READ_DATA else '0'; |
wbm_strobe <= wbm_cyc and not finished; |
WBM_WE_O <= '1' when current_state = WRITE_DATA else '0'; |
WBM_ADR_O <= wbm_adr(31 downto 2) & "00"; |
WBM_STB_O <= wbm_strobe; |
WBM_CYC_O <= wbm_cyc; |
WBM_SEL_O <= "1100" when odd_word = '1' else "0011"; |
end architecture behavioral; |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/tags/ver_1_0/rtl/vhdl/wb2hpi.vhd
0,0 → 1,427
---------------------------------------------------------------------- |
---- ---- |
---- File name "wb2hpi.vhd" ---- |
---- ---- |
---- This file is part of the "WB2HPI" project ---- |
---- http://www.opencores.org/cores/wb2hpi/ ---- |
---- ---- |
---- Author(s): ---- |
---- - Gvozden Marinkovic (gvozden@opencores.org) ---- |
---- - Dusko Krsmanovic (dusko@opencores.org) ---- |
---- ---- |
---- All additional information is avaliable in the README ---- |
---- file. ---- |
---- ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
--==================================================================-- |
-- Design : wb2hpi_WBmaster |
-- ( entity i architecture ) |
-- |
-- File : wb2hpi_WBmaster.vhd |
-- |
-- Errors : |
-- |
-- Library : ieee.std_logic_1164 |
-- |
-- Dependency : |
-- |
-- Author : Gvozden Marinkovic |
-- mgvozden@eunet.yu |
-- |
-- Simulators : ActiveVHDL 3.5 on a WindowsXP PC |
---------------------------------------------------------------------- |
-- Description : Top module for WB2HPI application |
---------------------------------------------------------------------- |
-- Copyright (c) 2002 Gvozden Marinkovic |
-- |
-- This VHDL design file is an open design; you can redistribute it |
-- and/or modify it and/or implement it after contacting the author |
--==================================================================-- |
|
--************************** CVS history ***************************-- |
--$Author: gvozden $ |
--$Date: 2003-01-16 18:06:19 $ |
--$Revision: 1.1.1.1 $ |
--$Name: not supported by cvs2svn $ |
--************************** CVS history ***************************-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
---------------------------------------------------------------------- |
-- entity wb2hpi |
---------------------------------------------------------------------- |
entity wb2hpi is |
port ( |
-- WISHBONE common signals to MASTER and SLAVE |
WB_CLK_I : in std_logic; -- Clock |
WB_RST_I : in std_logic; -- Reset |
|
-- WISHBONE SLAVE signals |
WBS_CYC_I : in std_logic; -- Cycle in progress |
WBS_STB_I : in std_logic; -- Strobe |
WBS_WE_I : in std_logic; -- Write enable |
WBS_CAB_I : in std_logic; |
WBS_ADR_I : in std_logic_vector(31 downto 0); -- Address |
WBS_DAT_I : in std_logic_vector(31 downto 0); -- Data input |
WBS_SEL_I : in std_logic_vector(3 downto 0); -- Select |
WBS_ACK_O : out std_logic; -- Acknowledge |
WBS_ERR_O : out std_logic; -- Error |
WBS_RTY_O : out std_logic; -- Retry |
WBS_DAT_O : out std_logic_vector(31 downto 0); -- Data output |
|
-- WISHBONE MASTER signals |
WBM_ACK_I : in std_logic; -- Acknowledge |
WBM_ERR_I : in std_logic; -- Error |
WBM_RTY_I : in std_logic; -- Retry |
WBM_DAT_I : in std_logic_vector(31 downto 0); -- Data input |
WBM_CYC_O : out std_logic; -- Cycle in progress |
WBM_STB_O : out std_logic; -- Strobe |
WBM_WE_O : out std_logic; -- Write enable |
WBM_CAB_O : out std_logic; |
WBM_ADR_O : out std_logic_vector(31 downto 0); -- Address |
WBM_DAT_O : out std_logic_vector(31 downto 0); -- Data output |
WBM_SEL_O : out std_logic_vector( 3 downto 0); -- Select |
|
-- to PCI |
INT_REQ : out std_logic; -- Interrupt request |
|
-- To DSP |
DSP_HAD_O : out std_logic_vector( 7 downto 0); -- HPI Address/Data Output |
DSP_HAD_ENn : out std_logic; -- HPI Address/Data Output Enable |
DSP_RST_PAD_O : out std_logic; -- Reset DSP |
DSP_HCNTL_PAD_O : out std_logic_vector( 1 downto 0); -- HPI Register selection |
DSP_HCS_PAD_O : out std_logic; -- HPI Chip Select |
DSP_HDS1_PAD_O : out std_logic; -- HPI Data Strobe 1 |
DSP_HDS2_PAD_O : out std_logic; -- HPI Data Strobe 2 |
DSP_HRW_PAD_O : out std_logic; -- HPI Read/Write |
DSP_HBIL_PAD_O : out std_logic; -- HPI Byte High/Low |
DSP_HAS_PAD_O : out std_logic; -- HPI HAS |
DSP_INT2_PAD_O : out std_logic; -- HPI Interrupt request 2 |
|
-- From DSP |
DSP_HAD_I : in std_logic_vector( 7 downto 0); -- HPI Address/Data Input |
DSP_HRDY_PAD_I : in std_logic; -- HPI Ready |
DSP_HINT_PAD_I : in std_logic; -- HPI Host Interrupt |
|
-- To Test LED |
LED : out std_logic -- Led diode |
); |
end entity wb2hpi; |
|
--------------------------------------------------------------------- |
-- architecture wb2hpi |
--------------------------------------------------------------------- |
architecture RTL of wb2hpi is |
|
--------------------------------------------------------------------- |
-- component declaration |
--------------------------------------------------------------------- |
component wb2hpi_WBslave is |
port ( |
-- WISHBONE common signals to MASTER and SLAVE |
WB_CLK_I : in std_logic; -- Clock |
WB_RST_I : in std_logic; -- Reset |
|
-- WISHBONE SLAVE signals |
WBS_CYC_I : in std_logic; -- Cycle in progress |
WBS_STB_I : in std_logic; -- Strobe |
WBS_WE_I : in std_logic; -- Write enable |
WBS_CAB_I : in std_logic; |
WBS_ADR_I : in std_logic_vector(31 downto 0); -- Address |
WBS_DAT_I : in std_logic_vector(31 downto 0); -- Data input |
WBS_SEL_I : in std_logic_vector(3 downto 0); -- Select |
WBS_ACK_O : out std_logic; -- Acknowledge |
WBS_ERR_O : out std_logic; -- Error |
WBS_RTY_O : out std_logic; -- Retry |
WBS_DAT_O : out std_logic_vector(31 downto 0); -- Data output |
|
-- To PCI signals |
int_req : out std_logic; -- Interrupt request |
|
-- To HPI Interface |
hpi_data_r : out std_logic_vector(17 downto 0); -- HPI data (to DSP) |
hpi_address_r : out std_logic_vector(15 downto 0); -- HPI address (to DSP) |
hpi_command_r : out std_logic_vector( 2 downto 0); -- HPI command |
pci_address_r : out std_logic_vector(31 downto 1); -- Memory buffrer address |
pci_counter_r : out std_logic_vector(15 downto 0); -- Number of words for transfer |
start_hpi_comm : out std_logic; -- Strobe Data |
hpi_reset : out std_logic; -- Reset HPI Logic |
dsp_reset : out std_logic; -- Reset DSP |
|
-- From HPI Interface |
hpi_data_out : in std_logic_vector(15 downto 0); -- Data out (To-WB) |
hpi_ready : in std_logic; -- Ready for HPI Access |
hpi_counter : in std_logic_vector(15 downto 0); |
hpi_pci_addr : in std_logic_vector(31 downto 1); |
hpi_int_req1 : in std_logic; -- Interrupt request 1 (End Block Transfer) |
hpi_int_req2 : in std_logic; -- Interrupt request 2 (from DSP) |
dsp_ready : in std_logic; -- DSP Ready |
dsp_hint : in std_logic; -- DSP Host Interrupt |
hpi_end_transfer: in std_logic; -- HPI End Transfer |
hpi_data_is_rdy : in std_logic; -- HPI Data Ready |
|
-- From WB master |
pci_error : in std_logic; -- PCI error |
|
-- To Test LED |
led : out std_logic -- Control LED |
); |
end component wb2hpi_WBslave; |
|
component wb2hpi_WBmaster is |
port ( |
-- WISHBONE common signals to MASTER and SLAVE |
WB_CLK_I : in std_logic; -- Clock |
WB_RST_I : in std_logic; -- Reset |
|
-- WISHBONE MASTER signals |
WBM_ACK_I : in std_logic; -- Acknowledge |
WBM_ERR_I : in std_logic; -- Error |
WBM_RTY_I : in std_logic; -- Retry |
WBM_DAT_I : in std_logic_vector(31 downto 0); -- Data input |
WBM_CYC_O : out std_logic; -- Cycle in progress |
WBM_STB_O : out std_logic; -- Strobe |
WBM_WE_O : out std_logic; -- Write enable |
WBM_CAB_O : out std_logic; -- |
WBM_ADR_O : out std_logic_vector(31 downto 0); -- Address |
WBM_DAT_O : out std_logic_vector(31 downto 0); -- Data output |
WBM_SEL_O : out std_logic_vector(3 downto 0); -- Select |
|
-- From HPI Interface |
pci_address : in std_logic_vector(31 downto 1); -- PCI Address |
pci_counter : in std_logic_vector(15 downto 0); -- Number of bytes for transfer |
pci_data_in : in std_logic_vector(15 downto 0); -- Data |
start_write : in std_logic; -- Start PCI write |
start_read : in std_logic; -- Start PCI read |
|
-- To WB Slave |
pci_error : out std_logic; -- PCI error |
|
-- To HPI Interface |
ready : out std_logic; -- Ready |
pci_data_out : out std_logic_vector(15 downto 0); -- Data |
pci_get_next : out std_logic -- Get next word |
); |
end component wb2hpi_WBmaster; |
|
component wb2hpi_control is |
port( |
clk : in std_logic; -- Clock |
reset : in std_logic; -- Reset |
|
-- From WB Slave |
hpi_data_r : in std_logic_vector(17 downto 0); -- HPI data (to DSP) |
hpi_address_r : in std_logic_vector(15 downto 0); -- HPI address (to DSP) |
hpi_command_r : in std_logic_vector( 2 downto 0); -- HPI command |
pci_address_r : in std_logic_vector(31 downto 1); -- Memory buffrer address |
pci_counter_r : in std_logic_vector(15 downto 0); -- Number of words for transfer |
start : in std_logic; -- Execute command |
|
-- From WB Master |
from_pci_data : in std_logic_vector(15 downto 0); -- From PCI Data (Bus Mastering) |
pci_get_next : in std_logic; -- Prepare next word |
pci_ready : in std_logic; -- WB Master is ready for transfer |
|
-- To WB Slave |
counter : out std_logic_vector(15 downto 0); -- Number of words left for transfer |
ready : out std_logic; -- HPI Interface ready (for status reg) |
end_transfer : out std_logic; -- End block transfer |
hpi_data_is_rdy : out std_logic; -- Data is ready (after HPI read) |
int_req1 : out std_logic; -- Interrupt request 1 (End Block Transfer) |
int_req2 : out std_logic; -- Interrupt request 2 (from DSP) |
|
-- To WB Master |
pci_start_write : out std_logic; -- Write request |
pci_start_read : out std_logic; -- Read request |
pci_counter : out std_logic_vector(15 downto 0); -- Number of words |
pci_address : out std_logic_vector(31 downto 1); -- PCI Address |
to_pci_data : out std_logic_vector(15 downto 0); -- PCI Data (Bus Mastering) |
|
-- From DSP |
hpi_ad_in : in std_logic_vector( 7 downto 0); -- Data in (From-HPI) |
dsp_hint : in std_logic; |
hpi_rdy : in std_logic; -- HPI Ready |
|
-- To DSP |
hpi_ad_out : out std_logic_vector( 7 downto 0); -- Data in (To-HPI) |
hpi_ad_en : out std_logic; -- Data out enable (To-HPI) |
dsp_int2 : out std_logic; |
hpi_cntl : out std_logic_vector( 1 downto 0); -- HPI Control |
hpi_cs_n : out std_logic; -- HPI Chpi Select |
hpi_ds_n : out std_logic; -- HPI Data Stobe |
hpi_rw : out std_logic; -- HPI Read/Write |
hpi_bil : out std_logic -- HPI Byte Low/High |
); |
end component wb2hpi_control; |
|
--------------------------------------------------------------------- |
-- signal declaration |
--------------------------------------------------------------------- |
signal pci_address_r : std_logic_vector(31 downto 1); |
signal pci_counter_r : std_logic_vector(15 downto 0); |
signal hpi_command_r : std_logic_vector( 2 downto 0); |
signal start_hpi_comm : std_logic; |
signal hpi_address_r : std_logic_vector(15 downto 0); |
signal hpi_data_r : std_logic_vector(17 downto 0); |
signal pci_address : std_logic_vector(31 downto 1); |
signal pci_counter : std_logic_vector(15 downto 0); |
signal hpi_counter : std_logic_vector(15 downto 0); |
signal to_pci_data : std_logic_vector(15 downto 0); |
signal from_pci_data : std_logic_vector(15 downto 0); |
signal pci_start_write : std_logic; |
signal pci_start_read : std_logic; |
signal pci_ready : std_logic; |
signal pci_strobe_data : std_logic; |
signal hpi_data_out : std_logic_vector(15 downto 0); |
signal hpi_ready : std_logic; |
signal dsp_err : std_logic; |
signal int_req1 : std_logic; |
signal int_req2 : std_logic; |
signal dsp_reset : std_logic; |
signal hpi_reset : std_logic; |
signal hpi_rst : std_logic; |
signal hpi_end_transfer : std_logic; |
signal hpi_data_is_rdy : std_logic; |
signal pci_error : std_logic; |
|
|
|
begin -- architecture RTL of myTop |
WB_slave : wb2hpi_WBslave port map ( |
WB_CLK_I => WB_CLK_I, |
WB_RST_I => WB_RST_I, |
WBS_CYC_I => WBS_CYC_I, |
WBS_STB_I => WBS_STB_I, |
WBS_WE_I => WBS_WE_I, |
WBS_CAB_I => WBS_CAB_I, |
WBS_ADR_I => WBS_ADR_I, |
WBS_DAT_I => WBS_DAT_I, |
WBS_SEL_I => WBS_SEL_I, |
WBS_ACK_O => WBS_ACK_O, |
WBS_ERR_O => WBS_ERR_O, |
WBS_RTY_O => WBS_RTY_O, |
WBS_DAT_O => WBS_DAT_O, |
int_req => INT_REQ, |
pci_address_r => pci_address_r, |
pci_counter_r => pci_counter_r, |
hpi_command_r => hpi_command_r, |
hpi_address_r => hpi_address_r, |
hpi_data_r => hpi_data_r, |
hpi_data_out => to_pci_data, |
start_hpi_comm => start_hpi_comm, |
hpi_counter => hpi_counter, |
hpi_pci_addr => pci_address, |
hpi_int_req1 => int_req1, |
hpi_int_req2 => int_req2, |
dsp_reset => dsp_reset, |
hpi_reset => hpi_reset, |
dsp_ready => DSP_HRDY_PAD_I, |
dsp_hint => DSP_HINT_PAD_I, |
hpi_ready => hpi_ready, |
hpi_end_transfer=> hpi_end_transfer, |
hpi_data_is_rdy => hpi_data_is_rdy, |
pci_error => pci_error, |
led => LED |
); |
|
WB_master: wb2hpi_WBmaster port map ( |
WB_CLK_I => WB_CLK_I, |
WB_RST_I => WB_RST_I, |
WBM_ACK_I => WBM_ACK_I, |
WBM_ERR_I => WBM_ERR_I, |
WBM_RTY_I => WBM_RTY_I, |
WBM_DAT_I => WBM_DAT_I, |
WBM_CYC_O => WBM_CYC_O, |
WBM_STB_O => WBM_STB_O, |
WBM_WE_O => WBM_WE_O, |
WBM_CAB_O => WBM_CAB_O, |
WBM_ADR_O => WBM_ADR_O, |
WBM_DAT_O => WBM_DAT_O, |
WBM_SEL_O => WBM_SEL_O, |
pci_address => pci_address, |
pci_counter => pci_counter, |
pci_data_in => to_pci_data, |
start_write => pci_start_write, |
start_read => pci_start_read, |
pci_error => pci_error, |
ready => pci_ready, |
pci_data_out => from_pci_data, |
pci_get_next => pci_strobe_data |
); |
|
hpi_rst <= hpi_reset or WB_RST_I; |
|
DSP: wb2hpi_control port map ( |
clk => WB_CLK_I, |
reset => hpi_rst, |
hpi_data_r => hpi_data_r, |
hpi_address_r => hpi_address_r, |
hpi_command_r => hpi_command_r, |
pci_address_r => pci_address_r, |
pci_counter_r => pci_counter_r, |
start => start_hpi_comm, |
from_pci_data => from_pci_data, |
pci_get_next => pci_strobe_data, |
pci_ready => pci_ready, |
pci_start_write => pci_start_write, |
pci_start_read => pci_start_read, |
pci_counter => pci_counter, |
pci_address => pci_address, |
to_pci_data => to_pci_data, |
dsp_hint => DSP_HINT_PAD_I, |
dsp_int2 => DSP_INT2_PAD_O, |
hpi_ad_in => DSP_HAD_I, |
hpi_ad_out => DSP_HAD_O, |
hpi_ad_en => DSP_HAD_ENn, |
hpi_cntl => DSP_HCNTL_PAD_O, |
hpi_cs_n => DSP_HCS_PAD_O, |
hpi_ds_n => DSP_HDS1_PAD_O, |
hpi_rdy => DSP_HRDY_PAD_I, |
hpi_rw => DSP_HRW_PAD_O, |
hpi_bil => DSP_HBIL_PAD_O, |
int_req1 => int_req1, |
int_req2 => int_req2, |
counter => hpi_counter, |
ready => hpi_ready, |
end_transfer => hpi_end_transfer, |
hpi_data_is_rdy => hpi_data_is_rdy |
); |
|
DSP_HDS2_PAD_O <= '1'; |
DSP_HAS_PAD_O <= '1'; |
DSP_RST_PAD_O <= dsp_reset; |
DSP_INT2_PAD_O <= DSP_HINT_PAD_I; |
|
end architecture RTL; |
|
|
|
|
/tags/ver_1_0/rtl/vhdl/wb2hpi_control.vhd
0,0 → 1,630
---------------------------------------------------------------------- |
---- ---- |
---- File name "wb2hpi_control.vhd" ---- |
---- ---- |
---- This file is part of the "WB2HPI" project ---- |
---- http://www.opencores.org/cores/wb2hpi/ ---- |
---- ---- |
---- Author(s): ---- |
---- - Gvozden Marinkovic (gvozden@opencores.org) ---- |
---- - Dusko Krsmanovic (dusko@opencores.org) ---- |
---- ---- |
---- All additional information is avaliable in the README ---- |
---- file. ---- |
---- ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
--==================================================================-- |
-- Design : wb2hpi_control |
-- ( entity i architecture ) |
-- |
-- File : wb2hpi_control.vhd |
-- |
-- Errors : |
-- |
-- Library : ieee.std_logic_1164 |
-- ieee.std_logic_arith.all; |
-- ieee.std_logic_unsigned.all; |
-- |
-- Dependency : |
-- |
-- Author : Gvozden Marinkovic |
-- mgvozden@eunet.yu |
-- |
-- Simulators : ActiveVHDL 3.5 on a WindowsXP PC |
---------------------------------------------------------------------- |
-- Description : HPI control logic for WB2HPI application |
---------------------------------------------------------------------- |
-- Copyright (c) 2002 Gvozden Marinkovic |
-- |
-- This VHDL design file is an open design; you can redistribute it |
-- and/or modify it and/or implement it after contacting the author |
--==================================================================-- |
|
--************************** CVS history ***************************-- |
-- $Author: gvozden $ |
-- $Date: 2003-01-16 18:06:20 $ |
-- $Revision: 1.1.1.1 $ |
-- $Name: not supported by cvs2svn $ |
--************************** CVS history ***************************-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.std_logic_unsigned.all; |
|
---------------------------------------------------------------------- |
-- entity wb2hpi_control |
---------------------------------------------------------------------- |
entity wb2hpi_control is |
port( |
clk : in std_logic; -- Clock |
reset : in std_logic; -- Reset |
|
-- From WB Slave |
hpi_data_r : in std_logic_vector(17 downto 0); -- HPI data (to DSP) |
hpi_address_r : in std_logic_vector(15 downto 0); -- HPI address (to DSP) |
hpi_command_r : in std_logic_vector( 2 downto 0); -- HPI command |
pci_address_r : in std_logic_vector(31 downto 1); -- Memory buffrer address |
pci_counter_r : in std_logic_vector(15 downto 0); -- Number of words for transfer |
start : in std_logic; -- Execute command |
|
-- From WB Master |
from_pci_data : in std_logic_vector(15 downto 0); -- From PCI Data (Bus Mastering) |
pci_get_next : in std_logic; -- Prepare next word |
pci_ready : in std_logic; -- WB Master is ready for transfer |
|
-- To WB Slave |
counter : out std_logic_vector(15 downto 0); -- Number of words left for transfer |
ready : out std_logic; -- HPI Interface ready (for status reg) |
end_transfer : out std_logic; -- End block transfer |
hpi_data_is_rdy : out std_logic; -- Data is ready (after HPI read) |
int_req1 : out std_logic; -- Interrupt request 1 (End Block Transfer) |
int_req2 : out std_logic; -- Interrupt request 2 (from DSP) |
|
-- To WB Master |
pci_start_write : out std_logic; -- Write request |
pci_start_read : out std_logic; -- Read request |
pci_counter : out std_logic_vector(15 downto 0); -- Number of words |
pci_address : out std_logic_vector(31 downto 1); -- PCI Address |
to_pci_data : out std_logic_vector(15 downto 0); -- PCI Data (Bus Mastering) |
|
-- From DSP |
hpi_ad_in : in std_logic_vector( 7 downto 0); -- Data in (From-HPI) |
dsp_hint : in std_logic; |
hpi_rdy : in std_logic; -- HPI Ready |
|
-- To DSP |
hpi_ad_out : out std_logic_vector( 7 downto 0); -- Data in (To-HPI) |
hpi_ad_en : out std_logic; -- Data out enable (To-HPI) |
dsp_int2 : out std_logic; |
hpi_cntl : out std_logic_vector( 1 downto 0); -- HPI Control |
hpi_cs_n : out std_logic; -- HPI Chip Select |
hpi_ds_n : out std_logic; -- HPI Data Stobe |
hpi_rw : out std_logic; -- HPI Read/Write |
hpi_bil : out std_logic -- HPI Byte Low/High |
); |
end entity wb2hpi_control; |
|
---------------------------------------------------------------------- |
-- architecture wb2hpi_control |
---------------------------------------------------------------------- |
architecture behavioral of wb2hpi_control is |
|
---------------------------------------------------------------------- |
-- component declaration |
---------------------------------------------------------------------- |
component wb2hpi_interface is |
port( |
clk : in std_logic; -- Clock |
reset : in std_logic; -- Reset |
we : in std_logic; -- Write Enable |
start : in std_logic; -- Start HPI Access |
address : in std_logic_vector( 1 downto 0); -- HPI Address |
data_in : in std_logic_vector(15 downto 0); -- Data in |
ready : out std_logic; -- Ready |
data_out : out std_logic_vector(15 downto 0); -- Data out |
hpi_err : out std_logic; -- HPI Error (not implemented) |
|
-- From DSP |
hpi_ad_in : in std_logic_vector( 7 downto 0); -- Data in (From-HPI) |
hpi_rdy : in std_logic; -- HPI Ready |
|
-- To DSP |
hpi_ad_out : out std_logic_vector( 7 downto 0); -- Data in (To-HPI) |
hpi_ad_en : out std_logic; -- Data out enable (To-HPI) |
hpi_cntl : out std_logic_vector( 1 downto 0); -- HPI Control |
hpi_cs_n : out std_logic; -- HPI Chip Select |
hpi_ds_n : out std_logic; -- HPI Data Stobe |
hpi_rw : out std_logic; -- HPI Read/Write |
hpi_bil : out std_logic -- HPI Byte Low/High |
); |
end component wb2hpi_interface; |
|
---------------------------------------------------------------------- |
-- type declaration |
---------------------------------------------------------------------- |
type hpi_states is (IDLE, INIT, END_BLOCK_TRANSFER, END_WRITE_BLOCK, |
CHANGE_PHASE, WAIT_PCI_ACK, PCI_ACK, |
WRITE_HPI, READ_HPI, WAIT_HPI, WAIT_HPI_DATA, |
HPI_DATA_READY, READ_PCI, WRITE_PCI, WAIT_PCI, |
PCI_DATA_READY, WAIT_PCI_DATA, WAIT_HPI_END); |
|
---------------------------------------------------------------------- |
-- constant declaration |
---------------------------------------------------------------------- |
-- Commands |
constant COM_WRITE_HPI : std_logic_vector( 2 downto 0):= B"010"; -- Write to DSP |
constant COM_READ_HPI : std_logic_vector( 2 downto 0):= B"011"; -- Read from DSP |
constant COM_READ_BLOCK : std_logic_vector( 2 downto 0):= B"100"; -- Read block from DSP |
constant COM_WRITE_BLOCK: std_logic_vector( 2 downto 0):= B"101"; -- Write block to DSP |
constant COM_MAP_READ : std_logic_vector( 2 downto 0):= B"110"; -- Map DSP read |
constant COM_MAP_WRITE : std_logic_vector( 2 downto 0):= B"111"; -- Map DSP write |
|
constant COUNTER_ZERO : std_logic_vector(15 downto 0):= (others => '0'); |
|
-- HPI Control registers addresses |
constant HPI_A : std_logic_vector( 1 downto 0):= B"10"; -- Address |
constant HPI_D : std_logic_vector( 1 downto 0):= B"11"; -- Data |
constant HPI_D_INC : std_logic_vector( 1 downto 0):= B"01"; -- Data with address increment |
|
---------------------------------------------------------------------- |
-- signal declaration |
---------------------------------------------------------------------- |
signal current_state, next_state: hpi_states; |
signal address_r : std_logic_vector(31 downto 1); |
signal counter_r : std_logic_vector(15 downto 0); |
signal pci_data_buffer : std_logic_vector(15 downto 0); |
signal hpi_address : std_logic_vector( 1 downto 0); |
signal hpi_data_in : std_logic_vector(15 downto 0); |
signal hpi_data_out : std_logic_vector(15 downto 0); |
signal hpi_data_rdy : std_logic; |
signal hpi_we : std_logic; |
signal hpi_start : std_logic; |
signal hpi_ready : std_logic; |
signal hpi_err : std_logic; |
signal pci_data_rdy : boolean; |
signal second_phase : boolean; |
signal finished : boolean; |
signal block_transfer : boolean; |
|
begin |
|
|
-- purpose: number of words to transfer through WB Master to PCI. |
-- In this case only one |
-- type : combinational |
-- outputs: pci_counter |
pci_counter <= "0000000000000001"; |
|
-- purpose: address of mamory buffer |
-- type : combinational |
-- inputs : address_r |
-- outputs: pci_address |
pci_address <= address_r; |
|
-- purpose: activates HPI bootloader after DSP reset (to DSP) |
-- type : combinational |
-- inputs : dsp_hint |
-- outputs: dsp_int2 |
dsp_int2 <= dsp_hint; |
|
-- purpose: for reading number of words left in block transfer. |
-- valid only after BLOCK command execution |
-- type : combinational |
-- inputs : counter_r |
-- outputs: counter |
counter <= counter_r; |
|
-- purpose: finite state machines |
-- type : sequential |
-- inputs : reset, clk, next_state |
-- outputs: current_state |
fsm_set_state: process (clk, reset) is |
begin |
if (reset = '1') then |
current_state <= IDLE; |
elsif rising_edge(clk) then |
current_state <= next_state; |
end if; |
end process fsm_set_state; |
|
-- purpose: fsm combination input/output logic |
-- type : combinational |
-- inputs : current_state, command_r, dsp_hint, dsp_hint, pci_ready, |
-- hpi_ready, pci_data_rdy, start, finished, second_phase |
-- outputs: next_state |
fsm_set_next: process (current_state, hpi_command_r, |
pci_ready, hpi_ready, pci_data_rdy, start, |
finished, second_phase) is |
begin |
next_state <= IDLE; |
|
case (current_state) is |
when IDLE => |
if (start = '1') then |
next_state <= INIT; |
end if; |
|
when INIT => |
case (hpi_command_r) is |
when COM_READ_HPI => |
next_state <= READ_HPI; |
when COM_WRITE_HPI | COM_MAP_READ | COM_MAP_WRITE=> |
next_state <= WRITE_HPI; |
when COM_READ_BLOCK => |
if (not finished) then |
next_state <= READ_HPI; |
end if; |
when COM_WRITE_BLOCK => |
if (not finished) then |
next_state <= READ_PCI; |
if (pci_ready = '0') then |
next_state <= WAIT_PCI; |
end if; |
end if; |
when others => null; |
end case; |
|
when WAIT_HPI => |
next_state <= WAIT_HPI; |
if (hpi_ready = '1') then |
case (hpi_command_r) is |
when COM_WRITE_HPI | COM_WRITE_BLOCK => |
next_state <= WRITE_HPI; |
when COM_READ_BLOCK | COM_READ_HPI => |
next_state <= READ_HPI; |
when COM_MAP_READ | COM_MAP_WRITE=> |
if (not second_phase) then |
next_state <= CHANGE_PHASE; |
end if; |
when others => null; |
end case; |
end if; |
|
when READ_HPI => |
next_state <= WAIT_HPI_DATA; |
|
when WAIT_HPI_DATA => |
next_state <= WAIT_HPI_DATA; |
if (hpi_ready = '1') then |
next_state <= HPI_DATA_READY; |
end if; |
|
when WRITE_HPI => |
next_state <= WAIT_HPI_END; |
case (hpi_command_r) is |
when COM_WRITE_BLOCK => |
if (not finished) then |
if (pci_ready = '1') then |
next_state <= READ_PCI; |
else |
next_state <= WAIT_PCI; |
end if; |
else |
next_state <= WAIT_HPI_END; |
end if; |
when COM_MAP_READ | COM_MAP_WRITE => |
if (not second_phase) then |
next_state <= WAIT_HPI; |
end if; |
when others => null; |
end case; |
|
when WAIT_HPI_END => |
next_state <= WAIT_HPI_END; |
if (hpi_ready = '1') then |
next_state <= IDLE; |
case (hpi_command_r) is |
when COM_WRITE_BLOCK | COM_READ_BLOCK=> |
next_state <= END_BLOCK_TRANSFER; |
when others => null; |
end case; |
end if; |
|
when CHANGE_PHASE => |
case (hpi_command_r) is |
when COM_MAP_READ => |
next_state <= READ_HPI; |
when COM_MAP_WRITE => |
next_state <= WRITE_HPI; |
when others => null; |
end case; |
|
when HPI_DATA_READY => |
case (hpi_command_r) is |
when COM_READ_BLOCK => |
if (pci_ready = '1') then |
next_state <= WRITE_PCI; |
else |
next_state <= WAIT_PCI; |
end if; |
when others => null; |
end case; |
|
when WAIT_PCI => |
next_state <= WAIT_PCI; |
if (pci_ready = '1') then |
case (hpi_command_r) is |
when COM_WRITE_BLOCK => |
next_state <= READ_PCI; |
when COM_READ_BLOCK => |
next_state <= WRITE_PCI; |
when others => null; |
end case; |
end if; |
|
when WRITE_PCI => |
next_state <= WAIT_PCI_ACK; |
|
when WAIT_PCI_ACK => |
next_state <= WAIT_PCI_ACK; |
if (pci_data_rdy) then |
next_state <= PCI_ACK; |
end if; |
|
when PCI_ACK => |
if (not finished) then |
if (hpi_ready = '1') then |
next_state <= READ_HPI; |
else |
next_state <= WAIT_HPI; |
end if; |
else |
next_state <= END_BLOCK_TRANSFER; |
end if; |
|
when END_BLOCK_TRANSFER => null; |
|
when READ_PCI => |
next_state <= WAIT_PCI_DATA; |
|
when WAIT_PCI_DATA => |
next_state <= WAIT_PCI_DATA; |
if (pci_data_rdy) then |
next_state <= PCI_DATA_READY; |
end if; |
|
when PCI_DATA_READY => |
if (hpi_ready = '1') then |
next_state <= WRITE_HPI; |
else |
next_state <= WAIT_HPI; |
end if; |
|
when others => null; |
end case; |
end process fsm_set_next; |
|
-- purpose: setting control signals |
-- type : sequential |
-- inputs : reset, clk, current_state |
-- outputs: hpi_address, hpi_data_in, hpi_we, hpi_start, hpi_data_rdy, |
-- block_transfer, pci_start_read, pci_start_write, int_req1, |
-- second_phase |
start_read_write: process(reset, clk) is |
begin |
if (reset = '1') then |
hpi_we <= '0'; |
hpi_start <= '0'; |
hpi_data_rdy <= '0'; |
block_transfer <= false; |
pci_start_read <= '0'; |
pci_start_write <= '0'; |
int_req1 <='0'; |
second_phase <= false; |
pci_data_buffer <= (others => '0'); |
elsif rising_edge(clk) then |
hpi_start <= '0'; |
pci_start_read <= '0'; |
pci_start_write <= '0'; |
int_req1 <='0'; |
case(next_state) is |
when IDLE => |
block_transfer <= false; |
second_phase <= false; |
when INIT => |
case (hpi_command_r) is |
when COM_READ_BLOCK | COM_WRITE_BLOCK => |
block_transfer <= true; |
when others => null; |
end case; |
when HPI_DATA_READY => |
hpi_data_rdy <= '1'; |
when READ_PCI => |
pci_start_read <= '1'; |
hpi_data_rdy <= '0'; |
when WRITE_PCI => |
pci_start_write <= '1'; |
hpi_data_rdy <= '0'; |
when WRITE_HPI => |
pci_data_buffer <= from_pci_data; |
hpi_we <= '1'; |
hpi_start <= '1'; |
when READ_HPI => |
hpi_we <= '0'; |
hpi_start <= '1'; |
when CHANGE_PHASE => |
second_phase <= true; |
when END_BLOCK_TRANSFER => |
int_req1 <='1'; |
when others => null; |
end case; |
end if; |
end process start_read_write; |
|
-- purpose: select hpi control register and data source |
-- type : combinational |
-- inputs : hpi_data_r, pci_data_buffer, hpi_address_r, hpi_command_r, |
-- block_transfer, second_phase |
-- outputs: hpi_data_in, hpi_address |
sel_hpi_addr_data: process (hpi_data_r, pci_data_buffer, hpi_address_r, hpi_command_r, |
block_transfer, second_phase) is |
begin |
hpi_data_in <= hpi_data_r(15 downto 0); |
hpi_address <= hpi_data_r(17 downto 16); |
case (hpi_command_r) is |
when COM_MAP_READ | COM_MAP_WRITE => |
if (not second_phase) then |
hpi_data_in <= hpi_address_r; |
hpi_address <= HPI_A; |
else |
hpi_address <= HPI_D; |
end if; |
when others => |
if (block_transfer) then |
hpi_data_in <= pci_data_buffer; |
hpi_address <= HPI_D_INC; |
end if; |
end case; |
end process sel_hpi_addr_data; |
|
-- purpose: increment/decrement address and count |
-- type : sequential |
-- inputs : reset, current_state, pci_counter_r, pci_address_r, pci_get_next |
-- outputs: address_r, counter_r |
inc_dec_regs: process (reset, current_state, |
pci_counter_r, pci_address_r, |
pci_get_next) is |
begin |
if (reset = '1') then |
counter_r <= (others => '0'); |
address_r <= (others => '0'); |
elsif (current_state = INIT) then |
counter_r <= pci_counter_r; |
address_r <= pci_address_r; |
elsif rising_edge(pci_get_next) then |
address_r <= address_r + 1; |
counter_r <= counter_r - 1; |
end if; |
end process inc_dec_regs; |
|
-- purpose: sets data ready flag |
-- type : sequential |
-- inputs : current_state, pci_get_next |
-- outputs: pci_data_rdy |
set_pci_data_rdy: process (reset, current_state, pci_get_next) is |
begin |
if (reset = '1') then |
pci_data_rdy <= false; |
elsif (current_state = READ_PCI or current_state = WRITE_PCI) then |
pci_data_rdy <= false; |
elsif rising_edge(pci_get_next) then |
pci_data_rdy <= true; |
end if; |
end process set_pci_data_rdy; |
|
-- purpose: set READY (to WB Slave) |
-- type : combinational |
-- inputs : current_state |
-- outputs: ready |
ready <= '1' when current_state = IDLE else '0'; |
|
-- purpose: block transfer is finished |
-- type : combinational |
-- inputs : counter_r |
-- outputs: finished, end_transfer |
finished <= counter_r = COUNTER_ZERO; |
end_transfer <= '1' when finished else '0'; |
|
-- purpose: propagate data to WB Master (to PCI) |
-- type : combinational |
-- inputs : hpi_data_out |
-- outputs: to_pci_data |
to_pci_data <= hpi_data_out; |
|
-- purpose: propagates data ready flag (data read from HPI is finished) |
-- type : combinational |
-- inputs : hpi_data_out |
-- outputs: to_pci_data |
hpi_data_is_rdy <= hpi_data_rdy; |
|
-- purpose: propagates interrupt from DSP to PCI |
-- type : combinational |
-- inputs : dsp_hint |
-- outputs: int_req2 |
int_req2 <= not dsp_hint; |
|
-- purpose: HPI interface core |
HPI_INTERFACE: wb2hpi_interface port map ( |
clk => clk, |
reset => reset, |
|
address => hpi_address, |
data_in => hpi_data_in, |
data_out => hpi_data_out, |
|
we => hpi_we, |
start => hpi_start, |
ready => hpi_ready, |
|
hpi_ad_in => hpi_ad_in, |
hpi_ad_out => hpi_ad_out, |
hpi_ad_en => hpi_ad_en, |
|
hpi_cntl => hpi_cntl, |
hpi_cs_n => hpi_cs_n, |
hpi_ds_n => hpi_ds_n, |
hpi_rdy => hpi_rdy, |
hpi_rw => hpi_rw, |
hpi_bil => hpi_bil, |
|
hpi_err => hpi_err |
); |
|
end architecture behavioral; |
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/tags/ver_1_0/rtl/vhdl/wb2hpi_interface.vhd
0,0 → 1,336
---------------------------------------------------------------------- |
---- ---- |
---- File name "wb2hpi_interface.vhd" ---- |
---- ---- |
---- This file is part of the "WB2HPI" project ---- |
---- http://www.opencores.org/cores/wb2hpi/ ---- |
---- ---- |
---- Author(s): ---- |
---- - Gvozden Marinkovic (gvozden@opencores.org) ---- |
---- - Dusko Krsmanovic (dusko@opencores.org) ---- |
---- ---- |
---- All additional information is avaliable in the README ---- |
---- file. ---- |
---- ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
--==================================================================-- |
-- Design : wb2hpi_interface |
-- ( entity i architecture ) |
-- |
-- File : wb2hpi_interface.vhd |
-- |
-- Errors : |
-- |
-- Library : ieee.std_logic_1164 |
-- ieee.std_logic_arith.all; |
-- ieee.std_logic_unsigned.all; |
-- |
-- Dependency : |
-- |
-- Author : Gvozden Marinkovic |
-- mgvozden@eunet.yu |
-- |
-- Simulators : ActiveVHDL 3.5 on a WindowsXP PC |
---------------------------------------------------------------------- |
-- Description : HPI interface for WB2HPI application |
---------------------------------------------------------------------- |
-- Copyright (c) 2002 Gvozden Marinkovic |
-- |
-- This VHDL design file is an open design; you can redistribute it |
-- and/or modify it and/or implement it after contacting the author |
--==================================================================-- |
|
--************************** CVS history ***************************-- |
-- $Author: gvozden $ |
-- $Date: 2003-01-16 18:06:20 $ |
-- $Revision: 1.1.1.1 $ |
--************************** CVS history ***************************-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
---------------------------------------------------------------------- |
-- entity wb2hpi_interface |
---------------------------------------------------------------------- |
entity wb2hpi_interface is |
port( |
clk : in std_logic; -- Clock |
reset : in std_logic; -- Reset |
we : in std_logic; -- Write Enable |
start : in std_logic; -- Start HPI Access |
address : in std_logic_vector( 1 downto 0); -- HPI Address |
data_in : in std_logic_vector(15 downto 0); -- Data in |
ready : out std_logic; -- Ready |
data_out : out std_logic_vector(15 downto 0); -- Data out |
hpi_err : out std_logic; -- HPI Error (not implemented) |
|
-- From DSP |
hpi_ad_in : in std_logic_vector( 7 downto 0); -- Data in (From-HPI) |
hpi_rdy : in std_logic; -- HPI Ready |
|
-- To DSP |
hpi_ad_out : out std_logic_vector( 7 downto 0); -- Data in (To-HPI) |
hpi_ad_en : out std_logic; -- Data out enable (To-HPI) |
hpi_cntl : out std_logic_vector( 1 downto 0); -- HPI Control |
hpi_cs_n : out std_logic; -- HPI Chip Select |
hpi_ds_n : out std_logic; -- HPI Data Stobe |
hpi_rw : out std_logic; -- HPI Read/Write |
hpi_bil : out std_logic -- HPI Byte Low/High |
); |
end entity wb2hpi_interface; |
|
------------------------------------------------------------------------ |
-- architecture wb2hpi_interface |
------------------------------------------------------------------------ |
architecture behavioral of wb2hpi_interface is |
|
------------------------------------------------------------------------ |
-- type declaration |
------------------------------------------------------------------------ |
type hpi_state is (IDLE, INIT, SET_DATA1, SET_DATA2, CHANGE_BYTE, |
LATCH_DATA1, LATCH_DATA2, CHECK_READY, END_STATE); |
|
------------------------------------------------------------------------ |
-- signal declaration |
------------------------------------------------------------------------ |
signal current_state, next_state: hpi_state; |
signal hpi_buffer_out : std_logic_vector(15 downto 0); |
signal hpi_buffer_in : std_logic_vector(15 downto 0); |
signal msb_byte : boolean; |
signal hpi_cs : std_logic; |
signal hpi_rdy_q : std_logic; |
|
begin -- architecture fsm of wb_hpi_sm |
-- purpose: finite state machine |
-- type : sequential |
-- inputs : clk, reset, next_state |
-- outputs: current_state |
fsm_set_state: process (clk, reset) is |
begin |
if (reset = '1') then |
current_state <= IDLE; |
elsif rising_edge(clk) then |
current_state <= next_state; |
end if; |
end process fsm_set_state; |
|
-- purpose: sample hpi ready (from DSP) signal |
-- type : sequential |
-- inputs : clk, reset, hpi_rdy |
-- outputs: hpi_rdy_q |
sample_hpi_rdy: process (reset, clk) is |
begin |
if (reset = '1') then |
hpi_rdy_q <= '0'; |
elsif rising_edge(clk) then |
hpi_rdy_q <= hpi_rdy; |
end if; |
end process sample_hpi_rdy; |
|
-- purpose: fsm combination input/output logic |
-- type : combinational |
-- inputs : current_state, start, hpi_rdy_q, second_byte |
-- outputs: next_state |
fsm_set_next: process (current_state, start, hpi_rdy_q) is |
begin |
next_state <= IDLE; |
case (current_state) is |
when IDLE => |
if (start = '1') then |
next_state <= INIT; |
end if; |
when INIT => |
next_state <= SET_DATA1; |
when SET_DATA1 => |
next_state <= CHECK_READY; |
when SET_DATA2 => |
next_state <= LATCH_DATA2; |
when CHECK_READY => |
next_state <= CHECK_READY; |
if (hpi_rdy_q = '1') then |
next_state <= LATCH_DATA1; |
end if; |
when LATCH_DATA1 => |
next_state <= CHANGE_BYTE; |
when LATCH_DATA2 => |
next_state <= END_STATE; |
when CHANGE_BYTE => |
next_state <= SET_DATA2; |
when others => null; |
end case; |
end process fsm_set_next; |
|
-- purpose: loads data into buffer |
-- type : sequential |
-- inputs : reset, clk, we, current_state, second_byte, hpi_ad_in |
-- outputs: hpi_buffer_in |
set_buffer_in: process (reset, clk) is |
begin |
if (reset = '1') then |
hpi_buffer_in <= (others => '0'); |
elsif (rising_edge(clk)) then |
if (we = '0' and next_state = LATCH_DATA1) then |
hpi_buffer_in (15 downto 8) <= hpi_ad_in; |
elsif (we = '0' and next_state = LATCH_DATA2) then |
hpi_buffer_in (7 downto 0) <= hpi_ad_in; |
end if; |
end if; |
end process set_buffer_in; |
|
-- purpose: set ready |
-- type : combinational |
-- inputs : current_state |
-- outputs: ready |
ready <= '1' when (current_state=IDLE or --else '0'; |
current_state=END_STATE) and start = '0' else '0'; |
|
-- purpose: propagate data from DSP |
-- type : combinational |
-- inputs : hpi_buffer_in |
-- outputs: data_out |
data_out <= hpi_buffer_in; |
|
-- purpose: select DSP |
-- type : sequential |
-- inputs : reset, clk, current_state |
-- outputs: hpi_cs_n |
select_hpi: process (reset, clk) is |
begin |
if reset = '1' then |
hpi_cs <= '1'; |
elsif rising_edge(clk) then |
hpi_cs <= '0'; |
case(next_state) is |
when IDLE | END_STATE => hpi_cs <= '1'; |
when others => null; |
end case; |
end if; |
end process select_hpi; |
hpi_cs_n <= hpi_cs; |
|
-- purpose: propagates data to DSP |
-- type : combinational |
-- inputs : data_in |
-- outputs: hpi_buffer_out |
hpi_buffer_out <= data_in; |
|
-- purpose: strobe control (to DSP) |
-- type : sequential |
-- inputs : reset, clk, current_state |
-- outputs: hpi_ds_n |
strobe_control: process(reset, clk) is |
begin |
if reset = '1' then |
hpi_ds_n <= '1'; |
elsif rising_edge(clk) then |
hpi_ds_n <= '1'; |
case(next_state) is |
when SET_DATA1 | CHECK_READY | |
SET_DATA2 => hpi_ds_n <= '0'; |
when others => null; |
end case; |
end if; |
end process strobe_control; |
|
-- purpose: select read/write (to DSP) |
-- type : combinational |
-- inputs : we |
-- outputs: hpi_rw |
hpi_rw <= not we; |
|
-- purpose: set HPI address/data output enable |
-- type : combinational |
-- inputs : we, hpi_cs |
-- outputs: hpi_ad_en |
hpi_ad_en <= '0' when (we = '1' and hpi_cs = '0') else '1'; |
|
-- purpose: set HPI address/data |
-- type : combinational |
-- inputs : hpi_buffer_out, second_byte |
-- outputs: hpi_ad_out |
hpi_ad_out <= hpi_buffer_out (15 downto 8) when msb_byte else |
hpi_buffer_out ( 7 downto 0); |
|
-- purpose: select first/second byte (to DSP) |
-- type : combinational |
-- inputs : reset, second_byte, clk, current_state |
-- outputs: hpi_bil |
hpi_byte_control: process(reset, clk) is |
variable changed: boolean; |
begin |
if reset = '1' then |
-- hpi_bil <= '0'; |
msb_byte <= true; |
changed := false; |
elsif rising_edge(clk) then |
msb_byte <= true; |
case(next_state) is |
when CHANGE_BYTE | SET_DATA2 | LATCH_DATA2 | END_STATE => |
msb_byte <= false; |
when others => null; |
end case; |
end if; |
end process hpi_byte_control; |
|
hpi_bil <= '0' when msb_byte else '1'; |
|
-- purpose: error report (not implemented) |
-- type : combinational |
-- inputs : |
-- outputs: hpi_err |
hpi_err <= '0'; |
|
-- purpose: select DSP register |
-- type : sequential |
-- inputs : address, current_state |
-- outputs: hpi_cntl |
hpi_cntl <= address; |
|
end architecture behavioral; |
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/tags/ver_1_0/rtl/vhdl/wb2hpi_WBslave.vhd
0,0 → 1,506
---------------------------------------------------------------------- |
---- ---- |
---- File name "wb2hpi_WBslave.vhd" ---- |
---- ---- |
---- This file is part of the "WB2HPI" project ---- |
---- http://www.opencores.org/cores/wb2hpi/ ---- |
---- ---- |
---- Author(s): ---- |
---- - Gvozden Marinkovic (gvozden@opencores.org) ---- |
---- - Dusko Krsmanovic (dusko@opencores.org) ---- |
---- ---- |
---- All additional information is avaliable in the README ---- |
---- file. ---- |
---- ---- |
---- ---- |
---------------------------------------------------------------------- |
---- ---- |
---- Copyright (C) 2002 Gvozden Marinkovic, gvozden@opencores.org ---- |
---- ---- |
---- This source file may be used and distributed without ---- |
---- restriction provided that this copyright statement is not ---- |
---- removed from the file and that any derivative work contains ---- |
---- the original copyright notice and the associated disclaimer. ---- |
---- ---- |
---- This source file is free software; you can redistribute it ---- |
---- and/or modify it under the terms of the GNU Lesser General ---- |
---- Public License as published by the Free Software Foundation; ---- |
---- either version 2.1 of the License, or (at your option) any ---- |
---- later version. ---- |
---- ---- |
---- This source is distributed in the hope that it will be ---- |
---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- |
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- |
---- PURPOSE. See the GNU Lesser General Public License for more ---- |
---- details. ---- |
---- ---- |
---- You should have received a copy of the GNU Lesser General ---- |
---- Public License along with this source; if not, download it ---- |
---- from http://www.opencores.org/lgpl.shtml ---- |
---- ---- |
---------------------------------------------------------------------- |
|
--==================================================================-- |
-- Design : wb2hpi_WBslave |
-- ( entity i architecture ) |
-- |
-- File : wb2hpi_WBslave.vhd |
-- |
-- Errors : |
-- |
-- Library : ieee.std_logic_1164 |
-- |
-- Dependency : |
-- |
-- Author : Gvozden Marinkovic |
-- mgvozden@eunet.yu |
-- |
-- Simulators : ActiveVHDL 3.5 on a WindowsXP PC |
---------------------------------------------------------------------- |
-- Description : WB Slave for WB2HPI application |
---------------------------------------------------------------------- |
-- Copyright (c) 2002 Gvozden Marinkovic |
-- |
-- This VHDL design file is an open design; you can redistribute it |
-- and/or modify it and/or implement it after contacting the author |
--==================================================================-- |
|
--************************** CVS history ***************************-- |
-- $Author: gvozden $ |
-- $Date: 2003-01-16 18:06:20 $ |
-- $Revision: 1.1.1.1 $ |
-- $Name: not supported by cvs2svn $ |
--************************** CVS history ***************************-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
---------------------------------------------------------------------- |
-- entity wb2hpi_WBslave |
---------------------------------------------------------------------- |
entity wb2hpi_WBslave is |
port ( |
-- WISHBONE common signals to MASTER and SLAVE |
WB_CLK_I : in std_logic; -- Clock |
WB_RST_I : in std_logic; -- Reset |
|
-- WISHBONE SLAVE signals |
WBS_CYC_I : in std_logic; -- Cycle in progress |
WBS_STB_I : in std_logic; -- Strobe |
WBS_WE_I : in std_logic; -- Write enable |
WBS_CAB_I : in std_logic; |
WBS_ADR_I : in std_logic_vector(31 downto 0); -- Address |
WBS_DAT_I : in std_logic_vector(31 downto 0); -- Data input |
WBS_SEL_I : in std_logic_vector(3 downto 0); -- Select |
WBS_ACK_O : out std_logic; -- Acknowledge |
WBS_ERR_O : out std_logic; -- Error |
WBS_RTY_O : out std_logic; -- Retry |
WBS_DAT_O : out std_logic_vector(31 downto 0); -- Data output |
|
-- To PCI signals |
int_req : out std_logic; -- Interrupt request |
|
-- To HPI Interface |
hpi_data_r : out std_logic_vector(17 downto 0); -- HPI data (to DSP) |
hpi_address_r : out std_logic_vector(15 downto 0); -- HPI address (to DSP) |
hpi_command_r : out std_logic_vector( 2 downto 0); -- HPI command |
pci_address_r : out std_logic_vector(31 downto 1); -- Memory buffrer address |
pci_counter_r : out std_logic_vector(15 downto 0); -- Number of words for transfer |
start_hpi_comm : out std_logic; -- Start HPI command |
hpi_reset : out std_logic; -- Reset HPI Logic |
dsp_reset : out std_logic; -- Reset DSP |
|
-- From HPI Interface |
hpi_data_out : in std_logic_vector(15 downto 0); -- Data out (To-WB) |
hpi_ready : in std_logic; -- Ready for HPI Access |
hpi_counter : in std_logic_vector(15 downto 0); |
hpi_pci_addr : in std_logic_vector(31 downto 1); |
hpi_int_req1 : in std_logic; -- Interrupt request 1 (End Block Transfer) |
hpi_int_req2 : in std_logic; -- Interrupt request 2 (from DSP) |
dsp_ready : in std_logic; -- DSP Ready |
dsp_hint : in std_logic; -- DSP Host Interrupt |
hpi_end_transfer: in std_logic; -- HPI End Transfer |
hpi_data_is_rdy : in std_logic; -- HPI Data Ready |
|
-- From WB master |
pci_error : in std_logic; -- PCI error |
|
-- To Test LED |
led : out std_logic -- Control LED |
); |
end entity wb2hpi_WBslave; |
|
---------------------------------------------------------------------- |
-- architecture wb2hpi_WBslave |
---------------------------------------------------------------------- |
architecture behavioral of wb2hpi_WBslave is |
|
---------------------------------------------------------------------- |
-- constant declaration |
---------------------------------------------------------------------- |
-- Registers Addresses |
constant ADR_IR : std_logic_vector(3 downto 0):="0001";-- Interrupt requests |
constant ADR_MR : std_logic_vector(3 downto 0):="0010";-- Interrupt mask |
constant ADR_LED : std_logic_vector(3 downto 0):="0111";-- LED |
constant ADR_HPI_COMM : std_logic_vector(3 downto 0):="1000";-- HPI command |
constant ADR_HPI_PCI_ADR: std_logic_vector(3 downto 0):="1001";-- PCI address |
constant ADR_HPI_READ : std_logic_vector(3 downto 0):="1010";-- HPI data |
constant ADR_HPI_CNT : std_logic_vector(3 downto 0):="1011";-- HPI word counter |
constant ADR_CONTROL : std_logic_vector(3 downto 0):="1100";-- DSP control |
constant ADR_STATUS : std_logic_vector(3 downto 0):="1101";-- DSP status |
constant ADR_MAP_DSP : std_logic_vector(3 downto 0):="1111";-- MAP DSP |
|
constant COM_MAP_READ : std_logic_vector(2 downto 0):= "110";-- Map DSP read |
constant COM_MAP_WRITE : std_logic_vector(2 downto 0):= "111";-- Map DSP write |
|
---------------------------------------------------------------------- |
-- type declaration |
---------------------------------------------------------------------- |
type wbs_state is (IDLE, RTY, ACK, START_MAP_READ, WAIT_HPI);-- WB Slave states |
type pci_state is (IDLE, SET_START, WAIT_END); |
|
---------------------------------------------------------------------- |
-- signal declaration |
---------------------------------------------------------------------- |
-- Registers |
signal ctl_mr : std_logic_vector( 1 downto 0); -- Interrupt mask |
signal ctl_ir : std_logic_vector( 1 downto 0); -- Interrupt requests |
signal led_r : std_logic_vector( 0 downto 0); -- LED |
signal control_r : std_logic_vector( 1 downto 0); -- DSP control |
signal status_r : std_logic_vector( 5 downto 0); -- DSP status |
signal hpi_dat_r : std_logic_vector(17 downto 0); |
signal hpi_com_r : std_logic_vector(2 downto 0); |
|
-- Control signals |
signal sel : std_logic_vector(15 downto 0); -- Register selections |
signal valid_access : boolean; -- Valid address detected |
signal write_ir : std_logic; -- Strobe |
|
-- FSM States |
signal current_state, next_state: wbs_state; |
|
---------------------------------------------------------------------- |
-- alias declaration |
---------------------------------------------------------------------- |
alias local_address : std_logic_vector(3 downto 0) is WBS_ADR_I(19 downto 16); |
|
-- Register selection signals |
alias sel_led : std_logic is sel(0); |
alias sel_mr : std_logic is sel(1); |
alias sel_ir : std_logic is sel(2); |
alias sel_pci_address : std_logic is sel(3); |
alias sel_pci_counter : std_logic is sel(4); |
alias sel_hpi_command : std_logic is sel(5); |
alias sel_hpi_data : std_logic is sel(6); |
alias sel_control : std_logic is sel(7); |
alias sel_status : std_logic is sel(8); |
alias sel_map_dsp : std_logic is sel(10); |
|
-- HPI |
alias WBS_HPI_COMM : std_logic_vector(2 downto 0) is WBS_DAT_I(18 downto 16); |
alias WBS_HPI_REG : std_logic_vector(1 downto 0) is WBS_DAT_I(21 downto 20); |
alias WBS_HPI_DATA : std_logic_vector(15 downto 0) is WBS_DAT_I(15 downto 0); |
|
begin -- architecture Behavioral of myWBSlave |
|
-- purpose: access cycle validation |
-- type : combinational |
-- inputs : WBS_SEL_I, WBS_CYC_I, WBS_STB_I, sel_map_dsp |
-- outputs: valid_access |
valid_access <= (WBS_CYC_I = '1' and |
WBS_STB_I = '1') and ( |
(WBS_SEL_I = "1111" and sel_map_dsp = '0') or |
(WBS_SEL_I = "1100" and sel_map_dsp = '1') or |
(WBS_SEL_I = "0011" and sel_map_dsp = '1') |
); |
|
-- purpose: ack or retry on valid cycle |
-- type : combinational |
-- inputs : valid_access, WBS_WE_I, current_state, sel, hpi_ready |
-- outputs: next_state |
fsm_set_next: process (valid_access, WBS_WE_I, |
current_state, sel_map_dsp, |
sel, hpi_ready) is |
begin |
next_state <= IDLE; -- Default state is IDLE |
|
case (current_state) is |
when IDLE => |
if (valid_access) then -- Valid cycle detected |
next_state <= ACK; |
if ((sel_hpi_command = '1' or -- Retry if HPI interface |
sel_hpi_data = '1' or -- is busy |
sel_pci_address = '1' or |
sel_map_dsp = '1') and |
hpi_ready ='0') then |
next_state <= RTY; |
elsif (sel_map_dsp = '1' and WBS_WE_I = '0') then |
next_state <= START_MAP_READ; |
end if; |
end if; |
when START_MAP_READ => |
next_state <= WAIT_HPI; |
when WAIT_HPI => |
next_state <= WAIT_HPI; |
if (hpi_ready = '1') then |
next_state <= ACK; |
end if; |
when ACK | RTY => |
next_state <= IDLE; |
when others => null; |
end case; |
end process fsm_set_next; |
|
-- purpose: generate delayed WISHBONE ack/err |
-- type : sequential |
-- inputs : WB_CLK_I, WB_RST_I, WBS_CYC_I, WBS_STB_I, |
-- valid_access, next_state |
-- outputs: WBS_ACK_O, WBS_ERR_O, WBS_RTY_O |
ack_err: process (WB_CLK_I, WB_RST_I) is |
begin |
if (WB_RST_I = '1') then |
WBS_ACK_O <= '0'; |
WBS_ERR_O <= '0'; |
WBS_RTY_O <= '0'; |
elsif rising_edge (WB_CLK_I) then |
WBS_ACK_O <= '0'; |
WBS_ERR_O <= '0'; |
WBS_RTY_O <= '0'; |
if (valid_access) then |
case (next_state) is |
when ACK => WBS_ACK_O <= '1'; |
when RTY => WBS_RTY_O <= '1'; |
when others => null; |
end case; |
elsif (WBS_CYC_I = '1' and WBS_STB_I = '1') then |
WBS_ERR_O <= '1'; |
end if; |
end if; |
end process ack_err; |
|
-- purpose: finite state machines |
-- type : sequential |
-- inputs : WB_CLK_I, WB_RST_I, next_state |
-- outputs: current_state |
fsm_set_state: process (WB_CLK_I, WB_RST_I, next_state) is |
begin |
if (WB_RST_I = '1') then |
current_state <= IDLE; |
elsif rising_edge(WB_CLK_I) then |
current_state <= next_state; |
end if; |
end process fsm_set_state; |
|
-- purpose: address decoder |
-- type : combinational |
-- inputs : local_address |
-- outputs: sel |
address_decode: process (local_address) is |
begin |
sel <= (others => '0'); |
case (local_address) is |
when ADR_LED => sel_led <= '1'; |
when ADR_MR => sel_mr <= '1'; |
when ADR_IR => sel_ir <= '1'; |
when ADR_HPI_PCI_ADR => sel_pci_address <= '1'; |
when ADR_HPI_READ => sel_hpi_data <= '1'; |
when ADR_HPI_CNT => sel_pci_counter <= '1'; |
when ADR_HPI_COMM => sel_hpi_command <= '1'; |
when ADR_CONTROL => sel_control <= '1'; |
when ADR_STATUS => sel_status <= '1'; |
when ADR_MAP_DSP => sel_map_dsp <= '1'; |
when others => null; |
end case; |
end process address_decode; |
|
-- purpose: write access control |
-- type : sequential |
-- inputs : WB_CLK_I, WB_RST_I, WBS_WE_I, next_state, sel, valid_access |
-- outputs: data_str, led_reg, ctl_mr, dsp_control_r |
write: process (WB_CLK_I, WB_RST_I) is |
begin |
if (WB_RST_I = '1') then |
ctl_mr <= (others => '0'); |
led_r <= (others => '0'); |
control_r <= (others => '0'); |
control_r(0) <= '1'; |
start_hpi_comm <= '0'; |
write_ir <= '0'; |
hpi_dat_r <= (others => '0'); |
hpi_address_r <= (others => '0'); |
hpi_com_r <= (others => '0'); |
pci_address_r <= (others => '0'); |
pci_counter_r <= (others => '0'); |
elsif (rising_edge(WB_CLK_I)) then |
start_hpi_comm <= '0'; |
write_ir <= '0'; |
if (next_state = ACK and WBS_WE_I = '1') then |
case (local_address) is |
when ADR_LED => |
led_r <= WBS_DAT_I(led_r'range); |
when ADR_IR => |
write_ir <= '1'; |
when ADR_MR => |
ctl_mr <= WBS_DAT_I(ctl_mr'range); |
when ADR_CONTROL => |
control_r <= WBS_DAT_I(control_r'range); |
when ADR_HPI_COMM => |
start_hpi_comm <= '1'; |
hpi_com_r <= WBS_HPI_COMM; |
hpi_dat_r (15 downto 0) <= WBS_HPI_DATA; |
hpi_dat_r (17 downto 16) <= WBS_HPI_REG; |
when ADR_HPI_PCI_ADR => |
pci_address_r <= WBS_DAT_I(pci_address_r'range); |
when ADR_HPI_CNT => |
pci_counter_r <= WBS_DAT_I(pci_counter_r'range); |
when ADR_MAP_DSP => |
start_hpi_comm <= '1'; |
hpi_com_r <= COM_MAP_WRITE; |
hpi_address_r (15 downto 0) <= '0' & WBS_ADR_I(15 downto 2) & '0'; |
hpi_dat_r (15 downto 0) <= WBS_DAT_I(15 downto 0); |
if (WBS_SEL_I(1) = '0') then |
hpi_address_r (0) <= '1'; |
hpi_dat_r(15 downto 0) <= WBS_DAT_I(31 downto 16); |
end if; |
when others => null; |
end case; |
elsif (next_state = START_MAP_READ) then |
hpi_com_r <= COM_MAP_READ; |
start_hpi_comm <= '1'; |
hpi_address_r (15 downto 0) <= '0' & WBS_ADR_I(15 downto 2) & '0'; |
if (WBS_SEL_I(1) = '0') then |
hpi_address_r (0) <= '1'; |
end if; |
end if; |
end if; |
end process write; |
|
-- purpose: set/reset interrupt request 0 |
-- type : sequential |
-- inputs : WB_RST_I, WBS_DAT_I, data_str, sel_ir, hpi_int_req1 |
-- outputs: ctl_ir(0) |
interrupt_request0: process (WB_RST_I, WBS_DAT_I, |
write_ir, sel_ir, hpi_int_req1) is |
begin |
if (WB_RST_I = '1') then |
ctl_ir(0) <= '0'; |
elsif (sel_ir = '1' and WBS_DAT_I(0) = '1') then |
if (write_ir = '1') then |
ctl_ir(0) <= '0'; |
end if; |
elsif rising_edge(hpi_int_req1) then |
ctl_ir(0) <= '1'; |
end if; |
end process interrupt_request0; |
|
-- purpose: set/reset interrupt request 1 |
-- type : sequential |
-- inputs : WB_RST_I, WBS_DAT_I, data_str, sel_ir, hpi_int_req2 |
-- outputs: ctl_ir(1) |
interrupt_request1: process (WB_RST_I, WBS_DAT_I, |
write_ir, sel_ir, hpi_int_req2) is |
begin |
if (WB_RST_I = '1') then |
ctl_ir(1) <= '0'; |
elsif (sel_ir = '1' and WBS_DAT_I(1) = '1') then |
if (write_ir = '1') then |
ctl_ir(1) <= '0'; |
end if; |
elsif rising_edge(hpi_int_req2) then |
ctl_ir(1) <= '1'; |
end if; |
end process interrupt_request1; |
|
-- purpose: read access control |
-- type : combinational |
-- inputs : local_address, ctl_mr, ctl_ir, led_reg, hpi_counter, hpi_data_out, |
-- hpi_pci_addr, dsp_control_r, dsp_status_r, hpi_comm_r |
-- outputs: WBS_DAT_O |
read: process (local_address, hpi_dat_r, ctl_ir, ctl_mr, led_r, hpi_counter, hpi_data_out, |
control_r, status_r, hpi_pci_addr, hpi_com_r, WBS_SEL_I) is |
begin |
WBS_DAT_O <= (others => '0'); |
case (local_address) is |
when ADR_IR => WBS_DAT_O(ctl_ir'range) <= ctl_ir; |
when ADR_MR => WBS_DAT_O(ctl_mr'range) <= ctl_mr; |
when ADR_LED => WBS_DAT_O(led_r'range) <= led_r; |
when ADR_HPI_PCI_ADR => WBS_DAT_O(hpi_pci_addr'range) <= hpi_pci_addr; |
when ADR_HPI_READ => WBS_DAT_O(hpi_data_out'range) <= hpi_data_out; |
when ADR_HPI_CNT => WBS_DAT_O(hpi_counter'range) <= hpi_counter; |
when ADR_HPI_COMM => WBS_DAT_O(21 downto 20) <= hpi_dat_r(17 downto 16); |
WBS_DAT_O(18 downto 16) <= hpi_com_r; |
when ADR_CONTROL => WBS_DAT_O(control_r'range) <= control_r; |
when ADR_STATUS => WBS_DAT_O(status_r'range) <= status_r; |
when ADR_MAP_DSP => WBS_DAT_O(15 downto 0) <= hpi_data_out; |
if (WBS_SEL_I(1) = '0') then |
WBS_DAT_O(31 downto 16) <= hpi_data_out; |
end if; |
when others => null; |
end case; |
end process read; |
|
hpi_data_r <= hpi_dat_r; |
hpi_command_r <= hpi_com_r; |
|
-- purpose: set WB interrupt request signal (to PCI) |
-- type : combinational |
-- inputs : ctl_ir, ctl_mr |
-- outputs: int_req |
int_req <= (ctl_ir(0) and ctl_mr(0)) or |
(ctl_ir(1) and ctl_mr(1)); |
|
-- purpose: drive dev. board LED |
-- type : combinational |
-- inputs : led_reg |
-- outputs: led |
led <= not led_r(0); |
-- led <= not control_r(0); |
|
-- purpose: Reset DSP |
-- type : combinational |
-- inputs : dsp_control_r(0) |
-- outputs: dsp_reset |
dsp_reset <= not control_r(0); |
|
-- purpose: Reset HPI interface |
-- type : combinational |
-- inputs : dsp_control_r(1) |
-- outputs: hpi_reset |
hpi_reset <= control_r(1); |
|
|
-- purpose: DSP Status register |
-- type : combinational |
-- inputs : hpi_data_is_rdy, hpi_end_transfer, hpi_ready, |
-- dsp_ready, dsp_hint, pci_error |
-- outputs: dsp_status_r |
status_r(0) <= hpi_data_is_rdy; |
status_r(1) <= hpi_end_transfer; |
status_r(2) <= hpi_ready; |
status_r(3) <= pci_error; |
status_r(4) <= dsp_ready; |
status_r(5) <= dsp_hint; |
|
end architecture behavioral; |
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/tags/ver_1_0/doc/wb2hpi.doc
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