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URL https://opencores.org/ocsvn/wb_prefetch_spram/wb_prefetch_spram/trunk

Subversion Repositories wb_prefetch_spram

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Rev 6 → Rev 7

/trunk/rtl/verilog/generic_spram.v
62,7 → 62,10
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2001/07/30 05:38:02 lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
`include "timescale.v"
 
74,8 → 77,8
//
// Default address and data buses width
//
parameter aw = 12;
parameter dw = 16;
parameter aw = 13;
parameter dw = 32;
 
//
// Generic synchronous single-port RAM interface
101,7 → 104,7
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
artisan_ssp #(dw, 2<<aw, aw) artisan_ssp(
art_hssp_8192x32 #(dw, 2<<aw, aw) artisan_ssp(
.CLK(clk),
.CEN(~ce),
.WEN(~we),

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