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URL https://opencores.org/ocsvn/wishbone_bfm/wishbone_bfm/trunk

Subversion Repositories wishbone_bfm

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    from Rev 6 to Rev 7
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Rev 6 → Rev 7

/trunk/rtl/wb_master.vhd
147,12 → 147,14
 
wr_32( x"8000_0001", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
 
clock_wait( 1, bus_c );
rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
 
wr_32( x"8000_0004", x"AA55_55AA", bus_c); -- write 32 bits address of 32 bit data
 
rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
 
 
clock_wait( 5, bus_c );
clock_wait( 1, bus_c );
wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
 
 
/trunk/rtl/wbmem32X16.vhd
0,0 → 1,98
--------------------------------------------------------------------------------
---- ----
---- WISHBONE wishbone out port from b3 spec IP Core ----
---- ----
---- This file is part of the wishbone out port from b3 spec project ----
---- http://www.opencores.org/cores/wishbone_out_port ----
---- ----
---- Description ----
---- Implementation of the wishbone out port from b3 spec IP core ----
---- according to wishbone out port from b3 spec IP core specification ----
---- document. ----
---- ----
---- To Do: ----
---- NA ----
---- ----
---- Taken directly from the wishbone out port from b3 spec, appendix A ----
---- Changes made, 'tidy up', I like things in lines ----
---- change name, as Xilinx tools ( 9.2 sp 4 ) do not like ----
---- entity same name as the file name. ----
---- Used others clause for sync reset. ----
---- ----
---- Author(s): ----
---- Andrew Mulcock, amulcock@opencores.org ----
---- ----
--------------------------------------------------------------------------------
---- ----
---- Copyright (C) 2008 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
--------------------------------------------------------------------------------
---- ----
-- CVS Revision History ----
---- ----
-- $Log: not supported by cvs2svn $ ----
---- ----
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity WB_MEM_32X16 is
port(
-- WISHBONE SLAVE interface:
-- Single-Port RAM with Asynchronous Read
--
ACK_O : out std_logic;
ADR_I : in std_logic_vector( 3 downto 0 );
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 31 downto 0 );
DAT_O : out std_logic_vector( 31 downto 0 );
STB_I : in std_logic;
WE_I : in std_logic
);
end entity WB_MEM_32X16;
 
 
architecture rtl of WB_MEM_32X16 is
 
type ram_type is array (15 downto 0) of std_logic_vector (31 downto 0);
signal RAM : ram_type;
 
begin
 
REG: process( CLK_I )
begin
if( rising_edge( CLK_I ) ) then
if( (STB_I and WE_I) = '1' ) then
RAM(to_integer(unsigned(ADR_I))) <= DAT_I;
end if;
end if;
end process REG;
 
ACK_O <= STB_I;
 
DAT_O <= RAM(to_integer(unsigned(ADR_I)));
 
end architecture rtl;
/trunk/rtl/wbtb_1m_1s.vhd
82,26 → 82,39
-- Component Declaration for wishbone master
COMPONENT wb_master
PORT(
RST_I : IN std_logic;
CLK_I : IN std_logic;
DAT_I : IN std_logic_vector(31 downto 0);
ACK_I : IN std_logic;
ERR_I : IN std_logic;
RTY_I : IN std_logic;
SEL_O : OUT std_logic_vector(3 downto 0);
RST_sys : OUT std_logic;
RST_I : IN std_logic;
CLK_I : IN std_logic;
DAT_I : IN std_logic_vector(31 downto 0);
ACK_I : IN std_logic;
ERR_I : IN std_logic;
RTY_I : IN std_logic;
SEL_O : OUT std_logic_vector(3 downto 0);
RST_sys : OUT std_logic;
CLK_stop : OUT std_logic;
ADR_O : OUT std_logic_vector(31 downto 0);
DAT_O : OUT std_logic_vector(31 downto 0);
WE_O : OUT std_logic;
STB_O : OUT std_logic;
CYC_O : OUT std_logic;
LOCK_O : OUT std_logic;
ADR_O : OUT std_logic_vector(31 downto 0);
DAT_O : OUT std_logic_vector(31 downto 0);
WE_O : OUT std_logic;
STB_O : OUT std_logic;
CYC_O : OUT std_logic;
LOCK_O : OUT std_logic;
CYCLE_IS : OUT cycle_type
);
END COMPONENT;
 
 
-- Component Declaration for wishbone slave
COMPONENT wb_mem_32x16
PORT(
ACK_O : out std_logic;
ADR_I : in std_logic_vector( 3 downto 0 );
CLK_I : in std_logic;
DAT_I : in std_logic_vector( 31 downto 0 );
DAT_O : out std_logic_vector( 31 downto 0 );
STB_I : in std_logic;
WE_I : in std_logic
);
END COMPONENT;
 
--Inputs
SIGNAL RST_I : std_logic := '0';
SIGNAL CLK_I : std_logic := '0';
111,15 → 124,15
SIGNAL DAT_I : std_logic_vector(31 downto 0) := (others=>'0');
 
--Outputs
SIGNAL RST_sys : std_logic;
SIGNAL RST_sys : std_logic;
SIGNAL CLK_stop : std_logic;
SIGNAL ADR_O : std_logic_vector(31 downto 0);
SIGNAL DAT_O : std_logic_vector(31 downto 0);
SIGNAL WE_O : std_logic;
SIGNAL STB_O : std_logic;
SIGNAL CYC_O : std_logic;
SIGNAL LOCK_O : std_logic;
SIGNAL SEL_O : std_logic_vector(3 downto 0);
SIGNAL ADR_O : std_logic_vector(31 downto 0);
SIGNAL DAT_O : std_logic_vector(31 downto 0);
SIGNAL WE_O : std_logic;
SIGNAL STB_O : std_logic;
SIGNAL CYC_O : std_logic;
SIGNAL LOCK_O : std_logic;
SIGNAL SEL_O : std_logic_vector(3 downto 0);
SIGNAL CYCLE_IS : cycle_type;
 
 
126,36 → 139,46
-- ---------------------------------------------------------------
BEGIN
-- ---------------------------------------------------------------
 
-- module port => signal name
-- Instantiate the system controler
sys_con: syscon PORT MAP(
RST_sys => RST_sys,
RST_sys => RST_sys,
CLK_stop => CLK_stop,
RST_O => RST_I,
CLK_O => CLK_I
RST_O => RST_I,
CLK_O => CLK_I
);
 
-- Instantiate the wishbone master
wb_m1: wb_master PORT MAP(
RST_sys => RST_sys,
RST_sys => RST_sys,
CLK_stop => CLK_stop,
RST_I => RST_I,
CLK_I => CLK_I,
ADR_O => ADR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
STB_O => STB_O,
CYC_O => CYC_O,
ACK_I => ACK_I,
ERR_I => ERR_I,
RTY_I => RTY_I,
LOCK_O => LOCK_O,
SEL_O => SEL_O,
RST_I => RST_I,
CLK_I => CLK_I,
ADR_O => ADR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
STB_O => STB_O,
CYC_O => CYC_O,
ACK_I => ACK_I,
ERR_I => ERR_I,
RTY_I => RTY_I,
LOCK_O => LOCK_O,
SEL_O => SEL_O,
CYCLE_IS => CYCLE_IS
);
 
ACK_I <= STB_O; -- temp wire strobe to ack
 
-- Instantiate the wishbone slave
wb_s1: wb_mem_32x16 PORT MAP(
ACK_O => ACK_I,
ADR_I => ADR_O( 3 downto 0 ),
CLK_I => CLK_I,
DAT_I => DAT_O,
DAT_O => DAT_I,
STB_I => STB_O,
WE_I => WE_O
);
 
 
END;

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