OpenCores
URL https://opencores.org/ocsvn/s1_core/s1_core/trunk

Subversion Repositories s1_core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /
    from Rev 60 to Rev 61
    ↔ Reverse comparison
  •

Rev 60 → Rev 61

/trunk/tools/bin/update_sparccore
56,15 → 56,27
for file in $DST_DIR/*.v ; do
sed -e 's/\$error/\$display/g' $file | sed -e 's/negedge rclk or rst_l/negedge rclk/g' > $DST_DIR/temp.v
if(test $1 == "-me" || test $1 == "-se") then
iverilog -E -D FPGA_SYN -D FPGA_SYN_1THREAD -D FPGA_SYN_NO_SPU -I $DST_DIR/include -o$file $DST_DIR/temp.v
iverilog -E -D CMP_CLK_PERIOD=1 -D FPGA_SYN -D FPGA_SYN_1THREAD -D FPGA_SYN_NO_SPU -I $DST_DIR/include -o$file $DST_DIR/temp.v
else
iverilog -E -D FPGA_SYN -D FPGA_SYN_NO_SPU -I $DST_DIR/include -o$file $DST_DIR/temp.v
iverilog -E -D CMP_CLK_PERIOD=1 -D FPGA_SYN -D FPGA_SYN_NO_SPU -I $DST_DIR/include -o$file $DST_DIR/temp.v
fi
sed -e 's/\* ========== Copyright Header Begin/\/\* ========== Copyright Header Begin/g' $file | sed -e 's/if (\$time > (4\* ))/if(\$time>2)/g' > $DST_DIR/temp.v
# These steps are required because Icarus does not allow this kind of comments
sed -e 's/\* ========== Copyright Header Begin/\/\* ========== Copyright Header Begin/g' $file > $DST_DIR/temp.v
mv -f $DST_DIR/temp.v $file
done
 
# Disable L1 Instruction and Data Caches
# Correct some strange strings
sed -e 's/sparc_exu_alulogic logic/sparc_exu_alulogic logic_MAYBEARESERVEDWORD/g' $DST_DIR/sparc_exu_alu.v > $DST_DIR/temp.v
mv $DST_DIR/temp.v $DST_DIR/sparc_exu_alu.v
sed -e 's/logic/logic_MAYBEARESERVEDWORD/g' $DST_DIR/sparc_ffu_ctl_visctl.v > $DST_DIR/temp.v
mv $DST_DIR/temp.v $DST_DIR/sparc_ffu_ctl_visctl.v
sed -e 's/$display(\"ILLEGAL_THR_STATE\"/\/\/$display(\"ILLEGAL_THR_STATE\"/g' sparc_ifu_thrfsm.v > $DST_DIR/temp.v
mv $DST_DIR/temp.v $DST_DIR/sparc_ifu_thrfsm.v
 
# After preprocessing we can safely delete the include directory
rm -f $DST_DIR/include/*.*
 
# Disable L1 Instruction and Data Caches if required
if(test $1 == "-me") then
cp -f $S1_ROOT/tools/src/bw_r_dcd.v $DST_DIR
cp -f $S1_ROOT/tools/src/bw_r_icd.v $DST_DIR
/trunk/tools/bin/build_fpga
1,5 → 1,5
#!/bin/bash
 
cd $S1_ROOT/run/synth/fpga
iverilog -t fpga -o fpga.edif -c$FILELIST_FPGA 2>&1 | tee synth.log
iverilog -g1 -t xnf -o fpga.edif -c$FILELIST_FPGA 2>&1 | tee synth.log
 
/trunk/tools/bin/update_filelist
11,11 → 11,12
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/behav/testbench/mem_harness.v >> $FILELIST_ICARUS
echo $S1_ROOT/hdl/behav/testbench/testbench.v >> $FILELIST_ICARUS
echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_ICARUS
# echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_ICARUS
echo "+incdir+"$S1_ROOT/hdl/rtl/s1_top >> $FILELIST_ICARUS
echo "+define+FPGA_SYN" >> $FILELIST_ICARUS
echo "+define+FPGA_SYN_1THREAD" >> $FILELIST_ICARUS
echo "+define+FPGA_SYN_NO_SPU" >> $FILELIST_ICARUS
echo "+define+DEBUG" >> $FILELIST_ICARUS
 
# Create the VCS filelist (for Synopsys simulation)
rm -f $FILELIST_VCS
30,7 → 31,7
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/behav/testbench/mem_harness.v >> $FILELIST_VCS
echo $S1_ROOT/hdl/behav/testbench/testbench.v >> $FILELIST_VCS
echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_VCS
# echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_VCS
echo "+incdir+"$S1_ROOT/hdl/rtl/s1_top >> $FILELIST_VCS
## TODO
# please find the proper option for the defines and put them here!!!
38,13 → 39,13
# Create the FPGA filelist (for Icarus synthesis)
rm -f $FILELIST_FPGA
touch $FILELIST_FPGA
find $S1_ROOT/hdl/macrocell/sparc_libs -name "*.v" >> $FILELIST_FPGA
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_FPGA
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/spc2wbm.v >> $FILELIST_FPGA
echo $S1_ROOT/hdl/rtl/s1_top/s1_top.v >> $FILELIST_FPGA
echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_FPGA
# echo "+incdir+"`find $S1_ROOT/hdl/rtl/sparc_core -name "include"` >> $FILELIST_FPGA
echo "+incdir+"$S1_ROOT/hdl/rtl/s1_top >> $FILELIST_FPGA
echo "+define+FPGA_SYN" >> $FILELIST_FPGA
echo "+define+FPGA_SYN_1THREAD" >> $FILELIST_FPGA
53,7 → 54,7
# Create the DC filelist (for Synopsys synthesis)
rm -f $FILELIST_DC
touch $FILELIST_DC
find $S1_ROOT/hdl/macrocell/sparc_libs -name "*.v" >> $FILELIST_DC
find $S1_ROOT/hdl/behav/sparc_libs -name "*.v" >> $FILELIST_DC
find $S1_ROOT/hdl/rtl/sparc_core -name "*.v" >> $FILELIST_DC
echo $S1_ROOT/hdl/rtl/s1_top/rst_ctrl.v >> $FILELIST_DC
echo $S1_ROOT/hdl/rtl/s1_top/int_ctrl.v >> $FILELIST_DC

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.