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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
/
- from Rev 608 to Rev 609
- ↔ Reverse comparison
Rev 608 → Rev 609
/trunk/mp3/rtl/verilog/mem_if/flash_top.v
44,6 → 44,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1.1.1 2001/11/04 19:00:09 lampret |
// First import. |
// |
91,8 → 94,10
wire [31:0] adr; |
`ifdef FLASH_GENERIC_REGISTERED |
reg wb_ack_o; |
reg wb_err_o; |
reg [31:0] wb_dat_o; |
`endif |
wire wb_err; |
|
assign flash_rstn = 1'b1; |
assign oen = 1'b1; |
130,8 → 135,18
assign wb_ack_o = wb_cyc_i & wb_stb_i; |
`endif |
|
assign wb_err_o = 1'b0; |
assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored) |
|
`ifdef FLASH_GENERIC_REGISTERED |
always @(posedge clk or negedge rstn) |
if (!rstn) |
wb_err_o <= #1 1'b0; |
else |
wb_err_o <= #1 wb_err & !wb_err_o; |
`else |
assign wb_err_o = wb_err; |
`endif |
|
// synopsys translate_off |
integer fflash; |
initial fflash = $fopen("flash.log"); |
/trunk/mp3/rtl/verilog/mem_if/sram_top.v
46,6 → 46,9
// CVS Revision History |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2002/01/14 06:18:22 lampret |
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. |
// |
// Revision 1.1.1.1 2001/11/04 19:00:09 lampret |
// First import. |
// |
263,14 → 266,9
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assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) | ack_we; |
assign wb_err_o = 1'b0; |
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored) |
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// synopsys translate_off |
integer fsram; |
initial fsram = $fopen("sram.log"); |